OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 46

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 44 unneback 
`ifdef ACTEL
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
`endif
8 
 
9 40 unneback 
`ifdef ALL
10 
 
11 
`define GBUF
12 
`define SYNC_RST
13 
`define PLL
14 
 
15 
`define MULTS
16 
`define MULTS18X18
17 
`define MULT
18 
`define SHIFT_UNIT_32
19 
`define LOGIC_UNIT
20 
 
21 
`define CNT_SHREG_WRAP
22 
`define CNT_SHREG_CE_WRAP
23 
`define CNT_SHREG_CE_CLEAR
24 
`define CNT_SHREG_CE_CLEAR_WRAP
25 
 
26 
`define MUX_ANDOR
27 
`define MUX2_ANDOR
28 
`define MUX3_ANDOR
29 
`define MUX4_ANDOR
30 
`define MUX5_ANDOR
31 
`define MUX6_ANDOR
32 43 unneback 
`define PARITY
33 40 unneback 
 
34 
`define ROM_INIT
35 
`define RAM
36 
`define RAM_BE
37 
`define DPRAM_1R1W
38 
`define DPRAM_2R1W
39 
`define DPRAM_2R2W
40 
`define FIFO_1R1W_FILL_LEVEL_SYNC
41 
`define FIFO_2R2W_SYNC_SIMPLEX
42 
`define FIFO_CMP_ASYNC
43 
`define FIFO_1R1W_ASYNC
44 
`define FIFO_2R2W_ASYNC
45 
`define FIFO_2R2W_ASYNC_SIMPLEX
46 
 
47 
`define DFF
48 
`define DFF_ARRAY
49 
`define DFF_CE
50 
`define DFF_CE_CLEAR
51 
`define DF_CE_SET
52 
`define SPR
53 
`define SRP
54 
`define DFF_SR
55 
`define LATCH
56 
`define SHREG
57 
`define SHREG_CE
58 
`define DELAY
59 
`define DELAY_EMPTYFLAG
60 
 
61 
`define WB3WB3_BRIDGE
62 
`define WB3_ARBITER_TYPE1
63 
`define WB_BOOT_ROM
64 
`define WB_DPRAM
65 
 
66 44 unneback 
`define IO_DFF_OE
67 
`define O_DFF
68 
 
69 40 unneback 
`endif
70 
 
71 
`ifdef PLL
72 
`ifndef SYNC_RST
73 
`define SYNC_RST
74 
`endif
75 
`endif
76 
 
77 
`ifdef SYNC_RST
78 
`ifndef GBUF
79 
`define GBUF
80 
`endif
81 
`endif
82 
 
83 
`ifdef WB_DPRAM
84 
`ifndef DPRAM_2R2W
85 
`define DPRAM_2R2W
86 
`endif
87 
`ifndef SPR
88 
`define SPR
89 
`endif
90 
`endif
91 
 
92 
`ifdef WB3_ARBITER_TYPE1
93 42 unneback 
`ifndef SPR
94 
`define SPR
95 
`endif
96 40 unneback 
`ifndef MUX_ANDOR
97 
`define MUX_ANDOR
98 
`endif
99 
`endif
100 
 
101 
`ifdef WB3WB3_BRIDGE
102 
`ifndef CNT_SHREG_CE_CLEAR
103 
`define CNT_SHREG_CE_CLEAR
104 
`endif
105 
`ifndef DFF
106 
`define DFF
107 
`endif
108 
`ifndef DFF_CE
109 
`define DFF_CE
110 
`endif
111 
`ifndef CNT_SHREG_CE_CLEAR
112 
`define CNT_SHREG_CE_CLEAR
113 
`endif
114 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
115 
`define FIFO_2R2W_ASYNC_SIMPLEX
116 
`endif
117 
`endif
118 
 
119 
`ifdef MULTS18X18
120 
`ifndef MULTS
121 
`define MULTS
122 
`endif
123 
`endif
124 
 
125 
`ifdef SHIFT_UNIT_32
126 
`ifndef MULTS
127 
`define MULTS
128 
`endif
129 
`endif
130 
 
131 
`ifdef MUX2_ANDOR
132 
`ifndef MUX_ANDOR
133 
`define MUX_ANDOR
134 
`endif
135 
`endif
136 
 
137 
`ifdef MUX3_ANDOR
138 
`ifndef MUX_ANDOR
139 
`define MUX_ANDOR
140 
`endif
141 
`endif
142 
 
143 
`ifdef MUX4_ANDOR
144 
`ifndef MUX_ANDOR
145 
`define MUX_ANDOR
146 
`endif
147 
`endif
148 
 
149 
`ifdef MUX5_ANDOR
150 
`ifndef MUX_ANDOR
151 
`define MUX_ANDOR
152 
`endif
153 
`endif
154 
 
155 
`ifdef MUX6_ANDOR
156 
`ifndef MUX_ANDOR
157 
`define MUX_ANDOR
158 
`endif
159 
`endif
160 
 
161 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
162 
`ifndef CNT_BIN_CE
163 
`define CNT_BIN_CE
164 
`endif
165 
`ifndef DPRAM_1R1W
166 
`define DPRAM_1R1W
167 
`endif
168 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
169 
`define CNT_BIN_CE_REW_Q_ZQ_L1
170 
`endif
171 
`endif
172 
 
173 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
174 
`ifndef CNT_LFSR_CE
175 
`define CNT_LFSR_CE
176 
`endif
177 
`ifndef DPRAM_2R2W
178 
`define DPRAM_2R2W
179 
`endif
180 
`ifndef CNT_BIN_CE_REW_ZQ_L1
181 
`define CNT_BIN_CE_REW_ZQ_L1
182 
`endif
183 
`endif
184 
 
185 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
186 
`ifndef CNT_GRAY_CE_BIN
187 
`define CNT_GRAY_CE_BIN
188 
`endif
189 
`ifndef DPRAM_2R2W
190 
`define DPRAM_2R2W
191 
`endif
192 
`ifndef FIFO_CMP_ASYNC
193 
`define FIFO_CMP_ASYNC
194 
`endif
195 
`endif
196 
 
197 
`ifdef FIFO_2R2W_ASYNC
198 
`ifndef FIFO_1R1W_ASYNC
199 
`define FIFO_1R1W_ASYNC
200 
`endif
201 
`endif
202 
 
203 
`ifdef FIFO_1R1W_ASYNC
204 
`ifndef CNT_GRAY_CE_BIN
205 
`define CNT_GRAY_CE_BIN
206 
`endif
207 
`ifndef DPRAM_1R1W
208 
`define DPRAM_1R1W
209 
`endif
210 
`ifndef FIFO_CMP_ASYNC
211 
`define FIFO_CMP_ASYNC
212 
`endif
213 
`endif
214 
 
215 
`ifdef FIFO_CMP_ASYNC
216 
`ifndef DFF_SR
217 
`define DFF_SR
218 
`endif
219 
`ifndef DFF
220 
`define DFF
221 
`endif
222 
`endif
223 6 unneback 
//////////////////////////////////////////////////////////////////////
224 
////                                                              ////
225 
////  Versatile library, clock and reset                          ////
226 
////                                                              ////
227 
////  Description                                                 ////
228 
////  Logic related to clock and reset                            ////
229 
////                                                              ////
230 
////                                                              ////
231 
////  To Do:                                                      ////
232 
////   - add more different registers                             ////
233 
////                                                              ////
234 
////  Author(s):                                                  ////
235 
////      - Michael Unneback, unneback@opencores.org              ////
236 
////        ORSoC AB                                              ////
237 
////                                                              ////
238 
//////////////////////////////////////////////////////////////////////
239 
////                                                              ////
240 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
241 
////                                                              ////
242 
//// This source file may be used and distributed without         ////
243 
//// restriction provided that this copyright statement is not    ////
244 
//// removed from the file and that any derivative work contains  ////
245 
//// the original copyright notice and the associated disclaimer. ////
246 
////                                                              ////
247 
//// This source file is free software; you can redistribute it   ////
248 
//// and/or modify it under the terms of the GNU Lesser General   ////
249 
//// Public License as published by the Free Software Foundation; ////
250 
//// either version 2.1 of the License, or (at your option) any   ////
251 
//// later version.                                               ////
252 
////                                                              ////
253 
//// This source is distributed in the hope that it will be       ////
254 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
255 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
256 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
257 
//// details.                                                     ////
258 
////                                                              ////
259 
//// You should have received a copy of the GNU Lesser General    ////
260 
//// Public License along with this source; if not, download it   ////
261 
//// from http://www.opencores.org/lgpl.shtml                     ////
262 
////                                                              ////
263 
//////////////////////////////////////////////////////////////////////
264 
 
265 
// Global buffer
266 
// usage:
267 
// use to enable global buffers for high fan out signals such as clock and reset
268 
 
269 
`ifdef ACTEL
270 40 unneback 
`ifdef GBUF
271 6 unneback 
`timescale 1 ns/100 ps
272 
// Version: 8.4 8.4.0.33
273 
module gbuf(GL,CLK);
274 
output GL;
275 
input  CLK;
276 
 
277 
    wire GND;
278 
 
279 
    GND GND_1_net(.Y(GND));
280 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
281 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
282 
 
283 
endmodule
284 
`timescale 1 ns/1 ns
285 40 unneback 
`define MODULE gbuf
286 
module `BASE`MODULE ( i, o);
287 
`undef MODULE
288 6 unneback 
input i;
289 
output o;
290 
`ifdef SIM_GBUF
291 
assign o=i;
292 
`else
293 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
294 
`endif
295 
endmodule
296 40 unneback 
`endif
297 33 unneback 
 
298 6 unneback 
`else
299 33 unneback 
 
300 40 unneback 
`ifdef ALTERA
301 
`ifdef GBUF
302 21 unneback 
//altera
303 40 unneback 
`define MODULE gbuf
304 
module `BASE`MODULE ( i, o);
305 
`undef MODULE
306 33 unneback 
input i;
307 
output o;
308 
assign o = i;
309 
endmodule
310 40 unneback 
`endif
311 33 unneback 
 
312 6 unneback 
`else
313 
 
314 40 unneback 
`ifdef GBUF
315 6 unneback 
`timescale 1 ns/100 ps
316 40 unneback 
`define MODULE
317 
module `BASE`MODULE ( i, o);
318 
`undef MODULE
319 6 unneback 
input i;
320 
output o;
321 
assign o = i;
322 
endmodule
323 40 unneback 
`endif
324 6 unneback 
`endif // ALTERA
325 
`endif //ACTEL
326 
 
327 40 unneback 
`ifdef SYNC_RST
328 6 unneback 
// sync reset
329 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
330 6 unneback 
// output active high global reset sync with two DFFs
331 
`timescale 1 ns/100 ps
332 40 unneback 
`define MODULE sync_rst
333 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
334 
`undef MODULE
335 6 unneback 
input rst_n_i, clk;
336 
output rst_o;
337 18 unneback 
reg [1:0] tmp;
338 6 unneback 
always @ (posedge clk or negedge rst_n_i)
339 
if (!rst_n_i)
340 17 unneback 
        tmp <= 2'b11;
341 6 unneback 
else
342 33 unneback 
        tmp <= {1'b0,tmp[1]};
343 40 unneback 
`define MODULE gbuf
344 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
345 
`undef MODULE
346 6 unneback 
endmodule
347 40 unneback 
`endif
348 6 unneback 
 
349 40 unneback 
`ifdef PLL
350 6 unneback 
// vl_pll
351 
`ifdef ACTEL
352 32 unneback 
///////////////////////////////////////////////////////////////////////////////
353 17 unneback 
`timescale 1 ps/1 ps
354 40 unneback 
`define MODULE pll
355 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
356 
`undef MODULE
357 6 unneback 
parameter index = 0;
358 
parameter number_of_clk = 1;
359 17 unneback 
parameter period_time_0 = 20000;
360 
parameter period_time_1 = 20000;
361 
parameter period_time_2 = 20000;
362 
parameter lock_delay = 2000000;
363 6 unneback 
input clk_i, rst_n_i;
364 
output lock;
365 
output reg [0:number_of_clk-1] clk_o;
366 
output [0:number_of_clk-1] rst_o;
367 
 
368 
`ifdef SIM_PLL
369 
 
370 
always
371 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
372 
 
373 
generate if (number_of_clk > 1)
374 
always
375 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
376 
endgenerate
377 
 
378 
generate if (number_of_clk > 2)
379 
always
380 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
381 
endgenerate
382 
 
383 
genvar i;
384 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
385 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
386 
end
387 
endgenerate
388 
 
389 
assign #lock_delay lock = rst_n_i;
390 
 
391 
endmodule
392 
`else
393 
generate if (number_of_clk==1 & index==0) begin
394 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
395 
end
396 
endgenerate // index==0
397 
generate if (number_of_clk==1 & index==1) begin
398 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
399 
end
400 
endgenerate // index==1
401 
generate if (number_of_clk==1 & index==2) begin
402 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
403 
end
404 
endgenerate // index==2
405 
generate if (number_of_clk==1 & index==3) begin
406 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
407 
end
408 
endgenerate // index==0
409 
 
410 
generate if (number_of_clk==2 & index==0) begin
411 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
412 
end
413 
endgenerate // index==0
414 
generate if (number_of_clk==2 & index==1) begin
415 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
416 
end
417 
endgenerate // index==1
418 
generate if (number_of_clk==2 & index==2) begin
419 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
420 
end
421 
endgenerate // index==2
422 
generate if (number_of_clk==2 & index==3) begin
423 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
424 
end
425 
endgenerate // index==0
426 
 
427 
generate if (number_of_clk==3 & index==0) begin
428 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
429 
end
430 
endgenerate // index==0
431 
generate if (number_of_clk==3 & index==1) begin
432 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
433 
end
434 
endgenerate // index==1
435 
generate if (number_of_clk==3 & index==2) begin
436 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
437 
end
438 
endgenerate // index==2
439 
generate if (number_of_clk==3 & index==3) begin
440 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
441 
end
442 
endgenerate // index==0
443 
 
444 
genvar i;
445 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
446 40 unneback 
`define MODULE sync_rst
447 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
448 
`undef MODULE
449 6 unneback 
end
450 
endgenerate
451 
endmodule
452 
`endif
453 32 unneback 
///////////////////////////////////////////////////////////////////////////////
454 6 unneback 
 
455 
`else
456 
 
457 32 unneback 
///////////////////////////////////////////////////////////////////////////////
458 6 unneback 
`ifdef ALTERA
459 
 
460 32 unneback 
`timescale 1 ps/1 ps
461 40 unneback 
`define MODULE pll
462 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
463 
`undef MODULE
464 32 unneback 
parameter index = 0;
465 
parameter number_of_clk = 1;
466 
parameter period_time_0 = 20000;
467 
parameter period_time_1 = 20000;
468 
parameter period_time_2 = 20000;
469 
parameter period_time_3 = 20000;
470 
parameter period_time_4 = 20000;
471 
parameter lock_delay = 2000000;
472 
input clk_i, rst_n_i;
473 
output lock;
474 
output reg [0:number_of_clk-1] clk_o;
475 
output [0:number_of_clk-1] rst_o;
476 
 
477 
`ifdef SIM_PLL
478 
 
479 
always
480 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
481 
 
482 
generate if (number_of_clk > 1)
483 
always
484 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
485 
endgenerate
486 
 
487 
generate if (number_of_clk > 2)
488 
always
489 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
490 
endgenerate
491 
 
492 33 unneback 
generate if (number_of_clk > 3)
493 32 unneback 
always
494 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
495 
endgenerate
496 
 
497 33 unneback 
generate if (number_of_clk > 4)
498 32 unneback 
always
499 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
500 
endgenerate
501 
 
502 
genvar i;
503 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
504 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
505 
end
506 
endgenerate
507 
 
508 33 unneback 
//assign #lock_delay lock = rst_n_i;
509 
assign lock = rst_n_i;
510 32 unneback 
 
511 
endmodule
512 6 unneback 
`else
513 
 
514 33 unneback 
`ifdef VL_PLL0
515 
`ifdef VL_PLL0_CLK1
516 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
517 
`endif
518 
`ifdef VL_PLL0_CLK2
519 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
520 
`endif
521 
`ifdef VL_PLL0_CLK3
522 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
523 
`endif
524 
`ifdef VL_PLL0_CLK4
525 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
526 
`endif
527 
`ifdef VL_PLL0_CLK5
528 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
529 
`endif
530 
`endif
531 32 unneback 
 
532 33 unneback 
`ifdef VL_PLL1
533 
`ifdef VL_PLL1_CLK1
534 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
535 
`endif
536 
`ifdef VL_PLL1_CLK2
537 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
538 
`endif
539 
`ifdef VL_PLL1_CLK3
540 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
541 
`endif
542 
`ifdef VL_PLL1_CLK4
543 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
544 
`endif
545 
`ifdef VL_PLL1_CLK5
546 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
547 
`endif
548 
`endif
549 32 unneback 
 
550 33 unneback 
`ifdef VL_PLL2
551 
`ifdef VL_PLL2_CLK1
552 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
553 
`endif
554 
`ifdef VL_PLL2_CLK2
555 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
556 
`endif
557 
`ifdef VL_PLL2_CLK3
558 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
559 
`endif
560 
`ifdef VL_PLL2_CLK4
561 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
562 
`endif
563 
`ifdef VL_PLL2_CLK5
564 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
565 
`endif
566 
`endif
567 32 unneback 
 
568 33 unneback 
`ifdef VL_PLL3
569 
`ifdef VL_PLL3_CLK1
570 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
571 
`endif
572 
`ifdef VL_PLL3_CLK2
573 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
574 
`endif
575 
`ifdef VL_PLL3_CLK3
576 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
577 
`endif
578 
`ifdef VL_PLL3_CLK4
579 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
580 
`endif
581 
`ifdef VL_PLL3_CLK5
582 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
583 
`endif
584 
`endif
585 32 unneback 
 
586 
genvar i;
587 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
588 40 unneback 
`define MODULE sync_rst
589 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
590 
`undef MODULE
591 32 unneback 
end
592 
endgenerate
593 
endmodule
594 
`endif
595 
///////////////////////////////////////////////////////////////////////////////
596 
 
597 
`else
598 
 
599 6 unneback 
// generic PLL
600 17 unneback 
`timescale 1 ps/1 ps
601 40 unneback 
`define MODULE pll
602 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
603 
`undef MODULE
604 6 unneback 
parameter index = 0;
605 
parameter number_of_clk = 1;
606 17 unneback 
parameter period_time_0 = 20000;
607 
parameter period_time_1 = 20000;
608 
parameter period_time_2 = 20000;
609 6 unneback 
parameter lock_delay = 2000;
610 
input clk_i, rst_n_i;
611 
output lock;
612 
output reg [0:number_of_clk-1] clk_o;
613 
output [0:number_of_clk-1] rst_o;
614 
 
615 
always
616 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
617 
 
618 
generate if (number_of_clk > 1)
619 
always
620 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
621 
endgenerate
622 
 
623 
generate if (number_of_clk > 2)
624 
always
625 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
626 
endgenerate
627 
 
628 
genvar i;
629 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
630 40 unneback 
`define MODULE sync_rst
631 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
632 
`undef MODULE
633 6 unneback 
end
634 
endgenerate
635 
 
636 
assign #lock_delay lock = rst_n_i;
637 
 
638 
endmodule
639 
 
640 
`endif //altera
641 17 unneback 
`endif //actel
642 40 unneback 
`undef MODULE
643 
`endif//////////////////////////////////////////////////////////////////////
644 6 unneback 
////                                                              ////
645 
////  Versatile library, registers                                ////
646 
////                                                              ////
647 
////  Description                                                 ////
648 
////  Different type of registers                                 ////
649 
////                                                              ////
650 
////                                                              ////
651 
////  To Do:                                                      ////
652 
////   - add more different registers                             ////
653 
////                                                              ////
654 
////  Author(s):                                                  ////
655 
////      - Michael Unneback, unneback@opencores.org              ////
656 
////        ORSoC AB                                              ////
657 
////                                                              ////
658 
//////////////////////////////////////////////////////////////////////
659 
////                                                              ////
660 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
661 
////                                                              ////
662 
//// This source file may be used and distributed without         ////
663 
//// restriction provided that this copyright statement is not    ////
664 
//// removed from the file and that any derivative work contains  ////
665 
//// the original copyright notice and the associated disclaimer. ////
666 
////                                                              ////
667 
//// This source file is free software; you can redistribute it   ////
668 
//// and/or modify it under the terms of the GNU Lesser General   ////
669 
//// Public License as published by the Free Software Foundation; ////
670 
//// either version 2.1 of the License, or (at your option) any   ////
671 
//// later version.                                               ////
672 
////                                                              ////
673 
//// This source is distributed in the hope that it will be       ////
674 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
675 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
676 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
677 
//// details.                                                     ////
678 
////                                                              ////
679 
//// You should have received a copy of the GNU Lesser General    ////
680 
//// Public License along with this source; if not, download it   ////
681 
//// from http://www.opencores.org/lgpl.shtml                     ////
682 
////                                                              ////
683 
//////////////////////////////////////////////////////////////////////
684 
 
685 40 unneback 
`ifdef DFF
686 
`define MODULE dff
687 
module `BASE`MODULE ( d, q, clk, rst);
688 
`undef MODULE
689 6 unneback 
        parameter width = 1;
690 
        parameter reset_value = 0;
691 
 
692 
        input [width-1:0] d;
693 
        input clk, rst;
694 
        output reg [width-1:0] q;
695 
 
696 
        always @ (posedge clk or posedge rst)
697 
        if (rst)
698 
                q <= reset_value;
699 
        else
700 
                q <= d;
701 
 
702 
endmodule
703 40 unneback 
`endif
704 6 unneback 
 
705 40 unneback 
`ifdef DFF_ARRAY
706 
`define MODULE dff_array
707 
module `BASE`MODULE ( d, q, clk, rst);
708 
`undef MODULE
709 6 unneback 
 
710 
        parameter width = 1;
711 
        parameter depth = 2;
712 
        parameter reset_value = 1'b0;
713 
 
714 
        input [width-1:0] d;
715 
        input clk, rst;
716 
        output [width-1:0] q;
717 
        reg  [0:depth-1] q_tmp [width-1:0];
718 
        integer i;
719 
        always @ (posedge clk or posedge rst)
720 
        if (rst) begin
721 
            for (i=0;i<depth;i=i+1)
722 
                q_tmp[i] <= {width{reset_value}};
723 
        end else begin
724 
            q_tmp[0] <= d;
725 
            for (i=1;i<depth;i=i+1)
726 
                q_tmp[i] <= q_tmp[i-1];
727 
        end
728 
 
729 
    assign q = q_tmp[depth-1];
730 
 
731 
endmodule
732 40 unneback 
`endif
733 6 unneback 
 
734 40 unneback 
`ifdef DFF_CE
735 
`define MODULE dff_ce
736 
module `BASE`MODULE ( d, ce, q, clk, rst);
737 
`undef MODULE
738 6 unneback 
 
739 
        parameter width = 1;
740 
        parameter reset_value = 0;
741 
 
742 
        input [width-1:0] d;
743 
        input ce, clk, rst;
744 
        output reg [width-1:0] q;
745 
 
746 
        always @ (posedge clk or posedge rst)
747 
        if (rst)
748 
                q <= reset_value;
749 
        else
750 
                if (ce)
751 
                        q <= d;
752 
 
753 
endmodule
754 40 unneback 
`endif
755 6 unneback 
 
756 40 unneback 
`ifdef DFF_CE_CLEAR
757 
`define MODULE dff_ce_clear
758 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
759 
`undef MODULE
760 8 unneback 
 
761 
        parameter width = 1;
762 
        parameter reset_value = 0;
763 
 
764 
        input [width-1:0] d;
765 10 unneback 
        input ce, clear, clk, rst;
766 8 unneback 
        output reg [width-1:0] q;
767 
 
768 
        always @ (posedge clk or posedge rst)
769 
        if (rst)
770 
            q <= reset_value;
771 
        else
772 
            if (ce)
773 
                if (clear)
774 
                    q <= {width{1'b0}};
775 
                else
776 
                    q <= d;
777 
 
778 
endmodule
779 40 unneback 
`endif
780 8 unneback 
 
781 40 unneback 
`ifdef DF_CE_SET
782 
`define MODULE dff_ce_set
783 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
784 
`undef MODULE
785 24 unneback 
 
786 
        parameter width = 1;
787 
        parameter reset_value = 0;
788 
 
789 
        input [width-1:0] d;
790 
        input ce, set, clk, rst;
791 
        output reg [width-1:0] q;
792 
 
793 
        always @ (posedge clk or posedge rst)
794 
        if (rst)
795 
            q <= reset_value;
796 
        else
797 
            if (ce)
798 
                if (set)
799 
                    q <= {width{1'b1}};
800 
                else
801 
                    q <= d;
802 
 
803 
endmodule
804 40 unneback 
`endif
805 24 unneback 
 
806 40 unneback 
`ifdef SPR
807 
`define MODULE spr
808 
module `BASE`MODULE ( sp, r, q, clk, rst);
809 
`undef MODULE
810 
 
811 29 unneback 
        parameter width = 1;
812 
        parameter reset_value = 0;
813 
 
814 
        input sp, r;
815 
        output reg q;
816 
        input clk, rst;
817 
 
818 
        always @ (posedge clk or posedge rst)
819 
        if (rst)
820 
            q <= reset_value;
821 
        else
822 
            if (sp)
823 
                q <= 1'b1;
824 
            else if (r)
825 
                q <= 1'b0;
826 
 
827 
endmodule
828 40 unneback 
`endif
829 29 unneback 
 
830 40 unneback 
`ifdef SRP
831 
`define MODULE srp
832 
module `BASE`MODULE ( s, rp, q, clk, rst);
833 
`undef MODULE
834 
 
835 29 unneback 
        parameter width = 1;
836 
        parameter reset_value = 0;
837 
 
838 
        input s, rp;
839 
        output reg q;
840 
        input clk, rst;
841 
 
842 
        always @ (posedge clk or posedge rst)
843 
        if (rst)
844 
            q <= reset_value;
845 
        else
846 
            if (rp)
847 
                q <= 1'b0;
848 
            else if (s)
849 
                q <= 1'b1;
850 
 
851 
endmodule
852 40 unneback 
`endif
853 29 unneback 
 
854 40 unneback 
`ifdef ALTERA
855 29 unneback 
 
856 40 unneback 
`ifdef DFF_SR
857 6 unneback 
// megafunction wizard: %LPM_FF%
858 
// GENERATION: STANDARD
859 
// VERSION: WM1.0
860 
// MODULE: lpm_ff
861 
 
862 
// ============================================================
863 
// File Name: dff_sr.v
864 
// Megafunction Name(s):
865 
//                      lpm_ff
866 
//
867 
// Simulation Library Files(s):
868 
//                      lpm
869 
// ============================================================
870 
// ************************************************************
871 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
872 
//
873 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
874 
// ************************************************************
875 
 
876 
 
877 
//Copyright (C) 1991-2010 Altera Corporation
878 
//Your use of Altera Corporation's design tools, logic functions
879 
//and other software and tools, and its AMPP partner logic
880 
//functions, and any output files from any of the foregoing
881 
//(including device programming or simulation files), and any
882 
//associated documentation or information are expressly subject
883 
//to the terms and conditions of the Altera Program License
884 
//Subscription Agreement, Altera MegaCore Function License
885 
//Agreement, or other applicable license agreement, including,
886 
//without limitation, that your use is for the sole purpose of
887 
//programming logic devices manufactured by Altera and sold by
888 
//Altera or its authorized distributors.  Please refer to the
889 
//applicable agreement for further details.
890 
 
891 
 
892 
// synopsys translate_off
893 
`timescale 1 ps / 1 ps
894 
// synopsys translate_on
895 40 unneback 
`define MODULE dff_sr
896 
module `BASE`MODULE (
897 
`undef MODULE
898 
 
899 6 unneback 
        aclr,
900 
        aset,
901 
        clock,
902 
        data,
903 
        q);
904 
 
905 
        input     aclr;
906 
        input     aset;
907 
        input     clock;
908 
        input     data;
909 
        output    q;
910 
 
911 
        wire [0:0] sub_wire0;
912 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
913 
        wire  q = sub_wire1;
914 
        wire  sub_wire2 = data;
915 
        wire  sub_wire3 = sub_wire2;
916 
 
917 
        lpm_ff  lpm_ff_component (
918 
                                .aclr (aclr),
919 
                                .clock (clock),
920 
                                .data (sub_wire3),
921 
                                .aset (aset),
922 
                                .q (sub_wire0)
923 
                                // synopsys translate_off
924 
                                ,
925 
                                .aload (),
926 
                                .enable (),
927 
                                .sclr (),
928 
                                .sload (),
929 
                                .sset ()
930 
                                // synopsys translate_on
931 
                                );
932 
        defparam
933 
                lpm_ff_component.lpm_fftype = "DFF",
934 
                lpm_ff_component.lpm_type = "LPM_FF",
935 
                lpm_ff_component.lpm_width = 1;
936 
 
937 
 
938 
endmodule
939 
 
940 
// ============================================================
941 
// CNX file retrieval info
942 
// ============================================================
943 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
944 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
945 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
946 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
947 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
948 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
949 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
950 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
951 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
952 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
953 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
954 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
955 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
956 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
957 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
958 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
959 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
960 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
961 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
962 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
963 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
964 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
965 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
966 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
967 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
968 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
969 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
970 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
971 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
972 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
973 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
974 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
975 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
976 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
977 
// Retrieval info: LIB_FILE: lpm
978 40 unneback 
`endif
979 6 unneback 
 
980 
`else
981 
 
982 40 unneback 
`ifdef DFF_SR
983 
`define MODULE dff_sr
984 
module `BASE`MODULE ( aclr, aset, clock, data, q);
985 
`undef MODULE
986 6 unneback 
 
987 
    input         aclr;
988 
    input         aset;
989 
    input         clock;
990 
    input         data;
991 
    output reg    q;
992 
 
993 
   always @ (posedge clock or posedge aclr or posedge aset)
994 
     if (aclr)
995 
       q <= 1'b0;
996 
     else if (aset)
997 
       q <= 1'b1;
998 
     else
999 
       q <= data;
1000 
 
1001 
endmodule
1002 40 unneback 
`endif
1003 6 unneback 
 
1004 
`endif
1005 
 
1006 
// LATCH
1007 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1008 
`ifdef ALTERA
1009 40 unneback 
 
1010 
`ifdef LATCH
1011 
`define MODULE latch
1012 
module `BASE`MODULE ( d, le, q, clk);
1013 
`undef MODULE
1014 6 unneback 
input d, le;
1015 
output q;
1016 
input clk;
1017 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1018 
endmodule
1019 40 unneback 
`endif
1020 
 
1021 6 unneback 
`else
1022 40 unneback 
 
1023 
`ifdef LATCH
1024 
`define MODULE latch
1025 
module `BASE`MODULE ( d, le, q, clk);
1026 
`undef MODULE
1027 6 unneback 
input d, le;
1028 
output q;
1029 
input clk;/*
1030 
   always @ (posedge direction_set or posedge direction_clr)
1031 
     if (direction_clr)
1032 
       direction <= going_empty;
1033 
     else
1034 
       direction <= going_full;*/
1035 
endmodule
1036 15 unneback 
`endif
1037 
 
1038 40 unneback 
`endif
1039 
 
1040 
`ifdef SHREG
1041 
`define MODULE shreg
1042 
module `BASE`MODULE ( d, q, clk, rst);
1043 
`undef MODULE
1044 
 
1045 17 unneback 
parameter depth = 10;
1046 
input d;
1047 
output q;
1048 
input clk, rst;
1049 
 
1050 
reg [1:depth] dffs;
1051 
 
1052 
always @ (posedge clk or posedge rst)
1053 
if (rst)
1054 
    dffs <= {depth{1'b0}};
1055 
else
1056 
    dffs <= {d,dffs[1:depth-1]};
1057 
assign q = dffs[depth];
1058 
endmodule
1059 40 unneback 
`endif
1060 17 unneback 
 
1061 40 unneback 
`ifdef SHREG_CE
1062 
`define MODULE shreg_ce
1063 
module `BASE`MODULE ( d, ce, q, clk, rst);
1064 
`undef MODULE
1065 17 unneback 
parameter depth = 10;
1066 
input d, ce;
1067 
output q;
1068 
input clk, rst;
1069 
 
1070 
reg [1:depth] dffs;
1071 
 
1072 
always @ (posedge clk or posedge rst)
1073 
if (rst)
1074 
    dffs <= {depth{1'b0}};
1075 
else
1076 
    if (ce)
1077 
        dffs <= {d,dffs[1:depth-1]};
1078 
assign q = dffs[depth];
1079 
endmodule
1080 40 unneback 
`endif
1081 17 unneback 
 
1082 40 unneback 
`ifdef DELAY
1083 
`define MODULE delay
1084 
module `BASE`MODULE ( d, q, clk, rst);
1085 
`undef MODULE
1086 15 unneback 
parameter depth = 10;
1087 
input d;
1088 
output q;
1089 
input clk, rst;
1090 
 
1091 
reg [1:depth] dffs;
1092 
 
1093 
always @ (posedge clk or posedge rst)
1094 
if (rst)
1095 
    dffs <= {depth{1'b0}};
1096 
else
1097 
    dffs <= {d,dffs[1:depth-1]};
1098 
assign q = dffs[depth];
1099 17 unneback 
endmodule
1100 40 unneback 
`endif
1101 17 unneback 
 
1102 40 unneback 
`ifdef DELAY_EMPTYFLAG
1103 
`define MODULE delay_emptyflag
1104 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1105 40 unneback 
`undef MODULE
1106 17 unneback 
parameter depth = 10;
1107 
input d;
1108 
output q, emptyflag;
1109 
input clk, rst;
1110 
 
1111 
reg [1:depth] dffs;
1112 
 
1113 
always @ (posedge clk or posedge rst)
1114 
if (rst)
1115 
    dffs <= {depth{1'b0}};
1116 
else
1117 
    dffs <= {d,dffs[1:depth-1]};
1118 
assign q = dffs[depth];
1119 
assign emptyflag = !(|dffs);
1120 
endmodule
1121 40 unneback 
`endif
1122 17 unneback 
//////////////////////////////////////////////////////////////////////
1123 6 unneback 
////                                                              ////
1124 18 unneback 
////  Logic functions                                             ////
1125 
////                                                              ////
1126 
////  Description                                                 ////
1127 
////  Logic functions such as multiplexers                        ////
1128 
////                                                              ////
1129 
////                                                              ////
1130 
////  To Do:                                                      ////
1131 
////   -                                                          ////
1132 
////                                                              ////
1133 
////  Author(s):                                                  ////
1134 
////      - Michael Unneback, unneback@opencores.org              ////
1135 
////        ORSoC AB                                              ////
1136 
////                                                              ////
1137 
//////////////////////////////////////////////////////////////////////
1138 
////                                                              ////
1139 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1140 
////                                                              ////
1141 
//// This source file may be used and distributed without         ////
1142 
//// restriction provided that this copyright statement is not    ////
1143 
//// removed from the file and that any derivative work contains  ////
1144 
//// the original copyright notice and the associated disclaimer. ////
1145 
////                                                              ////
1146 
//// This source file is free software; you can redistribute it   ////
1147 
//// and/or modify it under the terms of the GNU Lesser General   ////
1148 
//// Public License as published by the Free Software Foundation; ////
1149 
//// either version 2.1 of the License, or (at your option) any   ////
1150 
//// later version.                                               ////
1151 
////                                                              ////
1152 
//// This source is distributed in the hope that it will be       ////
1153 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1154 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1155 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1156 
//// details.                                                     ////
1157 
////                                                              ////
1158 
//// You should have received a copy of the GNU Lesser General    ////
1159 
//// Public License along with this source; if not, download it   ////
1160 
//// from http://www.opencores.org/lgpl.shtml                     ////
1161 
////                                                              ////
1162 
//////////////////////////////////////////////////////////////////////
1163 40 unneback 
`ifdef MUX_ANDOR
1164 
`define MODULE mux_andor
1165 
module `BASE`MODULE ( a, sel, dout);
1166 
`undef MODULE
1167 36 unneback 
 
1168 
parameter width = 32;
1169 
parameter nr_of_ports = 4;
1170 
 
1171 
input [nr_of_ports*width-1:0] a;
1172 
input [nr_of_ports-1:0] sel;
1173 
output reg [width-1:0] dout;
1174 
 
1175 38 unneback 
integer i,j;
1176 
 
1177 36 unneback 
always @ (a, sel)
1178 
begin
1179 
    dout = a[width-1:0] & {width{sel[0]}};
1180 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1181 
        for (j=0;j<width;j=j+1)
1182 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1183 36 unneback 
end
1184 
 
1185 
endmodule
1186 40 unneback 
`endif
1187 36 unneback 
 
1188 40 unneback 
`ifdef MUX2_ANDOR
1189 
`define MODULE mux2_andor
1190 
module `BASE`MODULE ( a1, a0, sel, dout);
1191 
`undef MODULE
1192 18 unneback 
 
1193 34 unneback 
parameter width = 32;
1194 35 unneback 
localparam nr_of_ports = 2;
1195 34 unneback 
input [width-1:0] a1, a0;
1196 
input [nr_of_ports-1:0] sel;
1197 
output [width-1:0] dout;
1198 
 
1199 40 unneback 
`define MODULE mux_andor
1200 
`BASE`MODULE
1201 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1202 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1203 40 unneback 
`undef MODULE
1204 
 
1205 34 unneback 
endmodule
1206 40 unneback 
`endif
1207 34 unneback 
 
1208 40 unneback 
`ifdef MUX3_ANDOR
1209 
`define MODULE mux3_andor
1210 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1211 
`undef MODULE
1212 34 unneback 
 
1213 
parameter width = 32;
1214 35 unneback 
localparam nr_of_ports = 3;
1215 34 unneback 
input [width-1:0] a2, a1, a0;
1216 
input [nr_of_ports-1:0] sel;
1217 
output [width-1:0] dout;
1218 
 
1219 40 unneback 
`define MODULE mux_andor
1220 
`BASE`MODULE
1221 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1222 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1223 40 unneback 
`undef MODULE
1224 34 unneback 
endmodule
1225 40 unneback 
`endif
1226 34 unneback 
 
1227 40 unneback 
`ifdef MUX4_ANDOR
1228 
`define MODULE mux4_andor
1229 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1230 
`undef MODULE
1231 18 unneback 
 
1232 
parameter width = 32;
1233 35 unneback 
localparam nr_of_ports = 4;
1234 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1235 
input [nr_of_ports-1:0] sel;
1236 22 unneback 
output [width-1:0] dout;
1237 18 unneback 
 
1238 40 unneback 
`define MODULE mux_andor
1239 
`BASE`MODULE
1240 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1241 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1242 40 unneback 
`undef MODULE
1243 18 unneback 
 
1244 
endmodule
1245 40 unneback 
`endif
1246 18 unneback 
 
1247 40 unneback 
`ifdef MUX5_ANDOR
1248 
`define MODULE mux5_andor
1249 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1250 
`undef MODULE
1251 18 unneback 
 
1252 
parameter width = 32;
1253 35 unneback 
localparam nr_of_ports = 5;
1254 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1255 
input [nr_of_ports-1:0] sel;
1256 22 unneback 
output [width-1:0] dout;
1257 18 unneback 
 
1258 40 unneback 
`define MODULE mux_andor
1259 
`BASE`MODULE
1260 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1261 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1262 40 unneback 
`undef MODULE
1263 18 unneback 
 
1264 
endmodule
1265 40 unneback 
`endif
1266 18 unneback 
 
1267 40 unneback 
`ifdef MUX6_ANDOR
1268 
`define MODULE mux6_andor
1269 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1270 
`undef MODULE
1271 18 unneback 
 
1272 
parameter width = 32;
1273 35 unneback 
localparam nr_of_ports = 6;
1274 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1275 
input [nr_of_ports-1:0] sel;
1276 22 unneback 
output [width-1:0] dout;
1277 18 unneback 
 
1278 40 unneback 
`define MODULE mux_andor
1279 
`BASE`MODULE
1280 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1281 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1282 40 unneback 
`undef MODULE
1283 18 unneback 
 
1284 
endmodule
1285 40 unneback 
`endif
1286 43 unneback 
 
1287 
`ifdef PARITY
1288 
 
1289 
`define MODULE parity_generate
1290 
module `BASE`MODULE (data, parity);
1291 
`undef MODULE
1292 
parameter word_size = 32;
1293 
parameter chunk_size = 8;
1294 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1295 
input [word_size-1:0] data;
1296 
output reg [word_size/chunk_size-1:0] parity;
1297 
integer i,j;
1298 
always @ (data)
1299 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1300 
    parity[i] = parity_type;
1301 
    for (j=0;j<chunk_size;j=j+1) begin
1302 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1303 43 unneback 
    end
1304 
end
1305 
endmodule
1306 
 
1307 
`define MODULE parity_check
1308 
module `BASE`MODULE( data, parity, parity_error);
1309 
`undef MODULE
1310 
parameter word_size = 32;
1311 
parameter chunk_size = 8;
1312 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1313 
input [word_size-1:0] data;
1314 
input [word_size/chunk_size-1:0] parity;
1315 
output parity_error;
1316 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1317 43 unneback 
integer i,j;
1318 
always @ (data or parity)
1319 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1320 
    error_flag[i] = parity[i] ^ parity_type;
1321 
    for (j=0;j<chunk_size;j=j+1) begin
1322 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1323 43 unneback 
    end
1324 
end
1325 
assign parity_error = |error_flag;
1326 
endmodule
1327 
 
1328 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1329 
////                                                              ////
1330 
////  IO functions                                                ////
1331 
////                                                              ////
1332 
////  Description                                                 ////
1333 
////  IO functions such as IOB flip-flops                         ////
1334 
////                                                              ////
1335 
////                                                              ////
1336 
////  To Do:                                                      ////
1337 
////   -                                                          ////
1338 
////                                                              ////
1339 
////  Author(s):                                                  ////
1340 
////      - Michael Unneback, unneback@opencores.org              ////
1341 
////        ORSoC AB                                              ////
1342 
////                                                              ////
1343 18 unneback 
//////////////////////////////////////////////////////////////////////
1344 
////                                                              ////
1345 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1346 
////                                                              ////
1347 
//// This source file may be used and distributed without         ////
1348 
//// restriction provided that this copyright statement is not    ////
1349 
//// removed from the file and that any derivative work contains  ////
1350 
//// the original copyright notice and the associated disclaimer. ////
1351 
////                                                              ////
1352 
//// This source file is free software; you can redistribute it   ////
1353 
//// and/or modify it under the terms of the GNU Lesser General   ////
1354 
//// Public License as published by the Free Software Foundation; ////
1355 
//// either version 2.1 of the License, or (at your option) any   ////
1356 
//// later version.                                               ////
1357 
////                                                              ////
1358 
//// This source is distributed in the hope that it will be       ////
1359 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1360 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1361 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1362 
//// details.                                                     ////
1363 
////                                                              ////
1364 
//// You should have received a copy of the GNU Lesser General    ////
1365 
//// Public License along with this source; if not, download it   ////
1366 
//// from http://www.opencores.org/lgpl.shtml                     ////
1367 
////                                                              ////
1368 
//////////////////////////////////////////////////////////////////////
1369 45 unneback 
`timescale 1ns/1ns
1370 44 unneback 
`ifdef O_DFF
1371 
`define MODULE o_dff
1372 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1373 
`undef MODULE
1374 
parameter width = 1;
1375 45 unneback 
parameter reset_value = {width{1'b0}};
1376 
input  [width-1:0]  d_i;
1377 44 unneback 
output [width-1:0] o_pad;
1378 
input clk, rst;
1379 
wire [width-1:0] d_i_int `SYN_KEEP;
1380 45 unneback 
reg  [width-1:0] o_pad_int;
1381 44 unneback 
assign d_i_int = d_i;
1382 
genvar i;
1383 45 unneback 
generate
1384 44 unneback 
for (i=0;i<width;i=i+1) begin
1385 
    always @ (posedge clk or posedge rst)
1386 
    if (rst)
1387 45 unneback 
        o_pad_int[i] <= reset_value[i];
1388 44 unneback 
    else
1389 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1390 
    assign #1 o_pad[i] = o_pad_int[i];
1391 44 unneback 
end
1392 
endgenerate
1393 
endmodule
1394 
`endif
1395 
 
1396 45 unneback 
`timescale 1ns/1ns
1397 44 unneback 
`ifdef IO_DFF_OE
1398 
`define MODULE io_dff_oe
1399 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1400 
`undef MODULE
1401 
parameter width = 1;
1402 
input  [width-1:0] d_o;
1403 
output reg [width-1:0] d_i;
1404 
input oe;
1405 
inout [width-1:0] io_pad;
1406 
input clk, rst;
1407 
wire [width-1:0] oe_d `SYN_KEEP;
1408 
reg [width-1:0] oe_q;
1409 
reg [width-1:0] d_o_q;
1410 
assign oe_d = {width{oe}};
1411 
genvar i;
1412 
generate
1413 
for (i=0;i<width;i=i+1) begin
1414 
    always @ (posedge clk or posedge rst)
1415 
    if (rst)
1416 
        oe_q[i] <= 1'b0;
1417 
    else
1418 
        oe_q[i] <= oe_d[i];
1419 
    always @ (posedge clk or posedge rst)
1420 
    if (rst)
1421 
        d_o_q[i] <= 1'b0;
1422 
    else
1423 
        d_o_q[i] <= d_o[i];
1424 
    always @ (posedge clk or posedge rst)
1425 
    if (rst)
1426 
        d_i[i] <= 1'b0;
1427 
    else
1428 
        d_i[i] <= io_pad[i];
1429 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1430 44 unneback 
end
1431 
endgenerate
1432 
endmodule
1433 
`endif
1434 
`ifdef CNT_BIN
1435 
//////////////////////////////////////////////////////////////////////
1436 
////                                                              ////
1437 6 unneback 
////  Versatile counter                                           ////
1438 
////                                                              ////
1439 
////  Description                                                 ////
1440 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1441 
////  counter                                                     ////
1442 
////                                                              ////
1443 
////  To Do:                                                      ////
1444 
////   - add LFSR with more taps                                  ////
1445 
////                                                              ////
1446 
////  Author(s):                                                  ////
1447 
////      - Michael Unneback, unneback@opencores.org              ////
1448 
////        ORSoC AB                                              ////
1449 
////                                                              ////
1450 
//////////////////////////////////////////////////////////////////////
1451 
////                                                              ////
1452 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1453 
////                                                              ////
1454 
//// This source file may be used and distributed without         ////
1455 
//// restriction provided that this copyright statement is not    ////
1456 
//// removed from the file and that any derivative work contains  ////
1457 
//// the original copyright notice and the associated disclaimer. ////
1458 
////                                                              ////
1459 
//// This source file is free software; you can redistribute it   ////
1460 
//// and/or modify it under the terms of the GNU Lesser General   ////
1461 
//// Public License as published by the Free Software Foundation; ////
1462 
//// either version 2.1 of the License, or (at your option) any   ////
1463 
//// later version.                                               ////
1464 
////                                                              ////
1465 
//// This source is distributed in the hope that it will be       ////
1466 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1467 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1468 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1469 
//// details.                                                     ////
1470 
////                                                              ////
1471 
//// You should have received a copy of the GNU Lesser General    ////
1472 
//// Public License along with this source; if not, download it   ////
1473 
//// from http://www.opencores.org/lgpl.shtml                     ////
1474 
////                                                              ////
1475 
//////////////////////////////////////////////////////////////////////
1476 
 
1477 
// binary counter
1478 22 unneback 
 
1479 40 unneback 
`define MODULE cnt_bin
1480 
module `BASE`MODULE (
1481 
`undef MODULE
1482 
 q, rst, clk);
1483 
 
1484 22 unneback 
   parameter length = 4;
1485 
   output [length:1] q;
1486 
   input rst;
1487 
   input clk;
1488 
 
1489 
   parameter clear_value = 0;
1490 
   parameter set_value = 1;
1491 
   parameter wrap_value = 0;
1492 
   parameter level1_value = 15;
1493 
 
1494 
   reg  [length:1] qi;
1495 
   wire [length:1] q_next;
1496 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1497 
 
1498 
   always @ (posedge clk or posedge rst)
1499 
     if (rst)
1500 
       qi <= {length{1'b0}};
1501 
     else
1502 
       qi <= q_next;
1503 
 
1504 
   assign q = qi;
1505 
 
1506 
endmodule
1507 40 unneback 
`endif
1508 
`ifdef CNT_BIN_CLEAR
1509 22 unneback 
//////////////////////////////////////////////////////////////////////
1510 
////                                                              ////
1511 
////  Versatile counter                                           ////
1512 
////                                                              ////
1513 
////  Description                                                 ////
1514 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1515 
////  counter                                                     ////
1516 
////                                                              ////
1517 
////  To Do:                                                      ////
1518 
////   - add LFSR with more taps                                  ////
1519 
////                                                              ////
1520 
////  Author(s):                                                  ////
1521 
////      - Michael Unneback, unneback@opencores.org              ////
1522 
////        ORSoC AB                                              ////
1523 
////                                                              ////
1524 
//////////////////////////////////////////////////////////////////////
1525 
////                                                              ////
1526 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1527 
////                                                              ////
1528 
//// This source file may be used and distributed without         ////
1529 
//// restriction provided that this copyright statement is not    ////
1530 
//// removed from the file and that any derivative work contains  ////
1531 
//// the original copyright notice and the associated disclaimer. ////
1532 
////                                                              ////
1533 
//// This source file is free software; you can redistribute it   ////
1534 
//// and/or modify it under the terms of the GNU Lesser General   ////
1535 
//// Public License as published by the Free Software Foundation; ////
1536 
//// either version 2.1 of the License, or (at your option) any   ////
1537 
//// later version.                                               ////
1538 
////                                                              ////
1539 
//// This source is distributed in the hope that it will be       ////
1540 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1541 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1542 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1543 
//// details.                                                     ////
1544 
////                                                              ////
1545 
//// You should have received a copy of the GNU Lesser General    ////
1546 
//// Public License along with this source; if not, download it   ////
1547 
//// from http://www.opencores.org/lgpl.shtml                     ////
1548 
////                                                              ////
1549 
//////////////////////////////////////////////////////////////////////
1550 
 
1551 
// binary counter
1552 
 
1553 40 unneback 
`define MODULE cnt_bin_clear
1554 
module `BASE`MODULE (
1555 
`undef MODULE
1556 
 clear, q, rst, clk);
1557 
 
1558 22 unneback 
   parameter length = 4;
1559 
   input clear;
1560 
   output [length:1] q;
1561 
   input rst;
1562 
   input clk;
1563 
 
1564 
   parameter clear_value = 0;
1565 
   parameter set_value = 1;
1566 
   parameter wrap_value = 0;
1567 
   parameter level1_value = 15;
1568 
 
1569 
   reg  [length:1] qi;
1570 
   wire [length:1] q_next;
1571 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1572 
 
1573 
   always @ (posedge clk or posedge rst)
1574 
     if (rst)
1575 
       qi <= {length{1'b0}};
1576 
     else
1577 
       qi <= q_next;
1578 
 
1579 
   assign q = qi;
1580 
 
1581 
endmodule
1582 40 unneback 
`endif
1583 
`ifdef CNT_BIN_CE
1584 22 unneback 
//////////////////////////////////////////////////////////////////////
1585 
////                                                              ////
1586 
////  Versatile counter                                           ////
1587 
////                                                              ////
1588 
////  Description                                                 ////
1589 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1590 
////  counter                                                     ////
1591 
////                                                              ////
1592 
////  To Do:                                                      ////
1593 
////   - add LFSR with more taps                                  ////
1594 
////                                                              ////
1595 
////  Author(s):                                                  ////
1596 
////      - Michael Unneback, unneback@opencores.org              ////
1597 
////        ORSoC AB                                              ////
1598 
////                                                              ////
1599 
//////////////////////////////////////////////////////////////////////
1600 
////                                                              ////
1601 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1602 
////                                                              ////
1603 
//// This source file may be used and distributed without         ////
1604 
//// restriction provided that this copyright statement is not    ////
1605 
//// removed from the file and that any derivative work contains  ////
1606 
//// the original copyright notice and the associated disclaimer. ////
1607 
////                                                              ////
1608 
//// This source file is free software; you can redistribute it   ////
1609 
//// and/or modify it under the terms of the GNU Lesser General   ////
1610 
//// Public License as published by the Free Software Foundation; ////
1611 
//// either version 2.1 of the License, or (at your option) any   ////
1612 
//// later version.                                               ////
1613 
////                                                              ////
1614 
//// This source is distributed in the hope that it will be       ////
1615 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1616 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1617 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1618 
//// details.                                                     ////
1619 
////                                                              ////
1620 
//// You should have received a copy of the GNU Lesser General    ////
1621 
//// Public License along with this source; if not, download it   ////
1622 
//// from http://www.opencores.org/lgpl.shtml                     ////
1623 
////                                                              ////
1624 
//////////////////////////////////////////////////////////////////////
1625 
 
1626 
// binary counter
1627 6 unneback 
 
1628 40 unneback 
`define MODULE cnt_bin_ce
1629 
module `BASE`MODULE (
1630 
`undef MODULE
1631 
 cke, q, rst, clk);
1632 
 
1633 6 unneback 
   parameter length = 4;
1634 
   input cke;
1635 
   output [length:1] q;
1636 
   input rst;
1637 
   input clk;
1638 
 
1639 
   parameter clear_value = 0;
1640 
   parameter set_value = 1;
1641 
   parameter wrap_value = 0;
1642 
   parameter level1_value = 15;
1643 
 
1644 
   reg  [length:1] qi;
1645 
   wire [length:1] q_next;
1646 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1647 
 
1648 
   always @ (posedge clk or posedge rst)
1649 
     if (rst)
1650 
       qi <= {length{1'b0}};
1651 
     else
1652 
     if (cke)
1653 
       qi <= q_next;
1654 
 
1655 
   assign q = qi;
1656 
 
1657 
endmodule
1658 40 unneback 
`endif
1659 
`ifdef CNT_BIN_CE_CLEAR
1660 6 unneback 
//////////////////////////////////////////////////////////////////////
1661 
////                                                              ////
1662 
////  Versatile counter                                           ////
1663 
////                                                              ////
1664 
////  Description                                                 ////
1665 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1666 
////  counter                                                     ////
1667 
////                                                              ////
1668 
////  To Do:                                                      ////
1669 
////   - add LFSR with more taps                                  ////
1670 
////                                                              ////
1671 
////  Author(s):                                                  ////
1672 
////      - Michael Unneback, unneback@opencores.org              ////
1673 
////        ORSoC AB                                              ////
1674 
////                                                              ////
1675 
//////////////////////////////////////////////////////////////////////
1676 
////                                                              ////
1677 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1678 
////                                                              ////
1679 
//// This source file may be used and distributed without         ////
1680 
//// restriction provided that this copyright statement is not    ////
1681 
//// removed from the file and that any derivative work contains  ////
1682 
//// the original copyright notice and the associated disclaimer. ////
1683 
////                                                              ////
1684 
//// This source file is free software; you can redistribute it   ////
1685 
//// and/or modify it under the terms of the GNU Lesser General   ////
1686 
//// Public License as published by the Free Software Foundation; ////
1687 
//// either version 2.1 of the License, or (at your option) any   ////
1688 
//// later version.                                               ////
1689 
////                                                              ////
1690 
//// This source is distributed in the hope that it will be       ////
1691 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1692 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1693 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1694 
//// details.                                                     ////
1695 
////                                                              ////
1696 
//// You should have received a copy of the GNU Lesser General    ////
1697 
//// Public License along with this source; if not, download it   ////
1698 
//// from http://www.opencores.org/lgpl.shtml                     ////
1699 
////                                                              ////
1700 
//////////////////////////////////////////////////////////////////////
1701 
 
1702 
// binary counter
1703 
 
1704 40 unneback 
`define MODULE cnt_bin_ce_clear
1705 
module `BASE`MODULE (
1706 
`undef MODULE
1707 
 clear, cke, q, rst, clk);
1708 
 
1709 6 unneback 
   parameter length = 4;
1710 
   input clear;
1711 
   input cke;
1712 
   output [length:1] q;
1713 
   input rst;
1714 
   input clk;
1715 
 
1716 
   parameter clear_value = 0;
1717 
   parameter set_value = 1;
1718 
   parameter wrap_value = 0;
1719 
   parameter level1_value = 15;
1720 
 
1721 
   reg  [length:1] qi;
1722 
   wire [length:1] q_next;
1723 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1724 
 
1725 
   always @ (posedge clk or posedge rst)
1726 
     if (rst)
1727 
       qi <= {length{1'b0}};
1728 
     else
1729 
     if (cke)
1730 
       qi <= q_next;
1731 
 
1732 
   assign q = qi;
1733 
 
1734 
endmodule
1735 40 unneback 
`endif
1736 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1737 6 unneback 
//////////////////////////////////////////////////////////////////////
1738 
////                                                              ////
1739 
////  Versatile counter                                           ////
1740 
////                                                              ////
1741 
////  Description                                                 ////
1742 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1743 
////  counter                                                     ////
1744 
////                                                              ////
1745 
////  To Do:                                                      ////
1746 
////   - add LFSR with more taps                                  ////
1747 
////                                                              ////
1748 
////  Author(s):                                                  ////
1749 
////      - Michael Unneback, unneback@opencores.org              ////
1750 
////        ORSoC AB                                              ////
1751 
////                                                              ////
1752 
//////////////////////////////////////////////////////////////////////
1753 
////                                                              ////
1754 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1755 
////                                                              ////
1756 
//// This source file may be used and distributed without         ////
1757 
//// restriction provided that this copyright statement is not    ////
1758 
//// removed from the file and that any derivative work contains  ////
1759 
//// the original copyright notice and the associated disclaimer. ////
1760 
////                                                              ////
1761 
//// This source file is free software; you can redistribute it   ////
1762 
//// and/or modify it under the terms of the GNU Lesser General   ////
1763 
//// Public License as published by the Free Software Foundation; ////
1764 
//// either version 2.1 of the License, or (at your option) any   ////
1765 
//// later version.                                               ////
1766 
////                                                              ////
1767 
//// This source is distributed in the hope that it will be       ////
1768 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1769 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1770 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1771 
//// details.                                                     ////
1772 
////                                                              ////
1773 
//// You should have received a copy of the GNU Lesser General    ////
1774 
//// Public License along with this source; if not, download it   ////
1775 
//// from http://www.opencores.org/lgpl.shtml                     ////
1776 
////                                                              ////
1777 
//////////////////////////////////////////////////////////////////////
1778 
 
1779 
// binary counter
1780 29 unneback 
 
1781 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1782 
module `BASE`MODULE (
1783 
`undef MODULE
1784 
 clear, cke, q, level1, level2, rst, clk);
1785 
 
1786 29 unneback 
   parameter length = 4;
1787 
   input clear;
1788 
   input cke;
1789 
   output [length:1] q;
1790 
   output reg level1;
1791 
   output reg level2;
1792 
   input rst;
1793 
   input clk;
1794 
 
1795 
   parameter clear_value = 0;
1796 
   parameter set_value = 1;
1797 30 unneback 
   parameter wrap_value = 15;
1798 
   parameter level1_value = 8;
1799 
   parameter level2_value = 15;
1800 29 unneback 
 
1801 
   wire rew;
1802 30 unneback 
   assign rew = 1'b0;
1803 29 unneback 
   reg  [length:1] qi;
1804 
   wire [length:1] q_next;
1805 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1806 
 
1807 
   always @ (posedge clk or posedge rst)
1808 
     if (rst)
1809 
       qi <= {length{1'b0}};
1810 
     else
1811 
     if (cke)
1812 
       qi <= q_next;
1813 
 
1814 
   assign q = qi;
1815 
 
1816 
 
1817 
    always @ (posedge clk or posedge rst)
1818 
    if (rst)
1819 
        level1 <= 1'b0;
1820 
    else
1821 
    if (cke)
1822 
    if (clear)
1823 
        level1 <= 1'b0;
1824 
    else if (q_next == level1_value)
1825 
        level1 <= 1'b1;
1826 
    else if (qi == level1_value & rew)
1827 
        level1 <= 1'b0;
1828 
 
1829 
    always @ (posedge clk or posedge rst)
1830 
    if (rst)
1831 
        level2 <= 1'b0;
1832 
    else
1833 
    if (cke)
1834 
    if (clear)
1835 
        level2 <= 1'b0;
1836 
    else if (q_next == level2_value)
1837 
        level2 <= 1'b1;
1838 
    else if (qi == level2_value & rew)
1839 
        level2 <= 1'b0;
1840 
endmodule
1841 40 unneback 
`endif
1842 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1843 29 unneback 
//////////////////////////////////////////////////////////////////////
1844 
////                                                              ////
1845 
////  Versatile counter                                           ////
1846 
////                                                              ////
1847 
////  Description                                                 ////
1848 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1849 
////  counter                                                     ////
1850 
////                                                              ////
1851 
////  To Do:                                                      ////
1852 
////   - add LFSR with more taps                                  ////
1853 
////                                                              ////
1854 
////  Author(s):                                                  ////
1855 
////      - Michael Unneback, unneback@opencores.org              ////
1856 
////        ORSoC AB                                              ////
1857 
////                                                              ////
1858 
//////////////////////////////////////////////////////////////////////
1859 
////                                                              ////
1860 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1861 
////                                                              ////
1862 
//// This source file may be used and distributed without         ////
1863 
//// restriction provided that this copyright statement is not    ////
1864 
//// removed from the file and that any derivative work contains  ////
1865 
//// the original copyright notice and the associated disclaimer. ////
1866 
////                                                              ////
1867 
//// This source file is free software; you can redistribute it   ////
1868 
//// and/or modify it under the terms of the GNU Lesser General   ////
1869 
//// Public License as published by the Free Software Foundation; ////
1870 
//// either version 2.1 of the License, or (at your option) any   ////
1871 
//// later version.                                               ////
1872 
////                                                              ////
1873 
//// This source is distributed in the hope that it will be       ////
1874 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1875 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1876 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1877 
//// details.                                                     ////
1878 
////                                                              ////
1879 
//// You should have received a copy of the GNU Lesser General    ////
1880 
//// Public License along with this source; if not, download it   ////
1881 
//// from http://www.opencores.org/lgpl.shtml                     ////
1882 
////                                                              ////
1883 
//////////////////////////////////////////////////////////////////////
1884 
 
1885 
// binary counter
1886 6 unneback 
 
1887 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1888 
module `BASE`MODULE (
1889 
`undef MODULE
1890 
 clear, set, cke, rew, q, rst, clk);
1891 
 
1892 6 unneback 
   parameter length = 4;
1893 
   input clear;
1894 
   input set;
1895 
   input cke;
1896 
   input rew;
1897 
   output [length:1] q;
1898 
   input rst;
1899 
   input clk;
1900 
 
1901 
   parameter clear_value = 0;
1902 
   parameter set_value = 1;
1903 
   parameter wrap_value = 0;
1904 
   parameter level1_value = 15;
1905 
 
1906 
   reg  [length:1] qi;
1907 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1908 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1909 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1910 
   assign q_next = rew ? q_next_rew : q_next_fw;
1911 
 
1912 
   always @ (posedge clk or posedge rst)
1913 
     if (rst)
1914 
       qi <= {length{1'b0}};
1915 
     else
1916 
     if (cke)
1917 
       qi <= q_next;
1918 
 
1919 
   assign q = qi;
1920 
 
1921 
endmodule
1922 40 unneback 
`endif
1923 
`ifdef CNT_BIN_CE_REW_L1
1924 6 unneback 
//////////////////////////////////////////////////////////////////////
1925 
////                                                              ////
1926 
////  Versatile counter                                           ////
1927 
////                                                              ////
1928 
////  Description                                                 ////
1929 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1930 
////  counter                                                     ////
1931 
////                                                              ////
1932 
////  To Do:                                                      ////
1933 
////   - add LFSR with more taps                                  ////
1934 
////                                                              ////
1935 
////  Author(s):                                                  ////
1936 
////      - Michael Unneback, unneback@opencores.org              ////
1937 
////        ORSoC AB                                              ////
1938 
////                                                              ////
1939 
//////////////////////////////////////////////////////////////////////
1940 
////                                                              ////
1941 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1942 
////                                                              ////
1943 
//// This source file may be used and distributed without         ////
1944 
//// restriction provided that this copyright statement is not    ////
1945 
//// removed from the file and that any derivative work contains  ////
1946 
//// the original copyright notice and the associated disclaimer. ////
1947 
////                                                              ////
1948 
//// This source file is free software; you can redistribute it   ////
1949 
//// and/or modify it under the terms of the GNU Lesser General   ////
1950 
//// Public License as published by the Free Software Foundation; ////
1951 
//// either version 2.1 of the License, or (at your option) any   ////
1952 
//// later version.                                               ////
1953 
////                                                              ////
1954 
//// This source is distributed in the hope that it will be       ////
1955 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1956 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1957 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1958 
//// details.                                                     ////
1959 
////                                                              ////
1960 
//// You should have received a copy of the GNU Lesser General    ////
1961 
//// Public License along with this source; if not, download it   ////
1962 
//// from http://www.opencores.org/lgpl.shtml                     ////
1963 
////                                                              ////
1964 
//////////////////////////////////////////////////////////////////////
1965 
 
1966 
// binary counter
1967 
 
1968 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
1969 
module `BASE`MODULE (
1970 
`undef MODULE
1971 
 cke, rew, level1, rst, clk);
1972 
 
1973 6 unneback 
   parameter length = 4;
1974 
   input cke;
1975 
   input rew;
1976 
   output reg level1;
1977 
   input rst;
1978 
   input clk;
1979 
 
1980 
   parameter clear_value = 0;
1981 
   parameter set_value = 1;
1982 
   parameter wrap_value = 1;
1983 
   parameter level1_value = 15;
1984 
 
1985 29 unneback 
   wire clear;
1986 30 unneback 
   assign clear = 1'b0;
1987 6 unneback 
   reg  [length:1] qi;
1988 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1989 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1990 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1991 
   assign q_next = rew ? q_next_rew : q_next_fw;
1992 
 
1993 
   always @ (posedge clk or posedge rst)
1994 
     if (rst)
1995 
       qi <= {length{1'b0}};
1996 
     else
1997 
     if (cke)
1998 
       qi <= q_next;
1999 
 
2000 
 
2001 
 
2002 
    always @ (posedge clk or posedge rst)
2003 
    if (rst)
2004 
        level1 <= 1'b0;
2005 
    else
2006 
    if (cke)
2007 29 unneback 
    if (clear)
2008 
        level1 <= 1'b0;
2009 
    else if (q_next == level1_value)
2010 6 unneback 
        level1 <= 1'b1;
2011 
    else if (qi == level1_value & rew)
2012 
        level1 <= 1'b0;
2013 
endmodule
2014 40 unneback 
`endif
2015 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2016 6 unneback 
//////////////////////////////////////////////////////////////////////
2017 
////                                                              ////
2018 
////  Versatile counter                                           ////
2019 
////                                                              ////
2020 
////  Description                                                 ////
2021 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2022 
////  counter                                                     ////
2023 
////                                                              ////
2024 
////  To Do:                                                      ////
2025 
////   - add LFSR with more taps                                  ////
2026 
////                                                              ////
2027 
////  Author(s):                                                  ////
2028 
////      - Michael Unneback, unneback@opencores.org              ////
2029 
////        ORSoC AB                                              ////
2030 
////                                                              ////
2031 
//////////////////////////////////////////////////////////////////////
2032 
////                                                              ////
2033 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2034 
////                                                              ////
2035 
//// This source file may be used and distributed without         ////
2036 
//// restriction provided that this copyright statement is not    ////
2037 
//// removed from the file and that any derivative work contains  ////
2038 
//// the original copyright notice and the associated disclaimer. ////
2039 
////                                                              ////
2040 
//// This source file is free software; you can redistribute it   ////
2041 
//// and/or modify it under the terms of the GNU Lesser General   ////
2042 
//// Public License as published by the Free Software Foundation; ////
2043 
//// either version 2.1 of the License, or (at your option) any   ////
2044 
//// later version.                                               ////
2045 
////                                                              ////
2046 
//// This source is distributed in the hope that it will be       ////
2047 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2048 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2049 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2050 
//// details.                                                     ////
2051 
////                                                              ////
2052 
//// You should have received a copy of the GNU Lesser General    ////
2053 
//// Public License along with this source; if not, download it   ////
2054 
//// from http://www.opencores.org/lgpl.shtml                     ////
2055 
////                                                              ////
2056 
//////////////////////////////////////////////////////////////////////
2057 
 
2058 25 unneback 
// binary counter
2059 
 
2060 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2061 
module `BASE`MODULE (
2062 
`undef MODULE
2063 
 cke, rew, zq, level1, rst, clk);
2064 
 
2065 25 unneback 
   parameter length = 4;
2066 
   input cke;
2067 
   input rew;
2068 
   output reg zq;
2069 
   output reg level1;
2070 
   input rst;
2071 
   input clk;
2072 
 
2073 
   parameter clear_value = 0;
2074 
   parameter set_value = 1;
2075 
   parameter wrap_value = 1;
2076 
   parameter level1_value = 15;
2077 
 
2078 29 unneback 
   wire clear;
2079 30 unneback 
   assign clear = 1'b0;
2080 25 unneback 
   reg  [length:1] qi;
2081 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2082 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2083 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2084 
   assign q_next = rew ? q_next_rew : q_next_fw;
2085 
 
2086 
   always @ (posedge clk or posedge rst)
2087 
     if (rst)
2088 
       qi <= {length{1'b0}};
2089 
     else
2090 
     if (cke)
2091 
       qi <= q_next;
2092 
 
2093 
 
2094 
 
2095 
   always @ (posedge clk or posedge rst)
2096 
     if (rst)
2097 
       zq <= 1'b1;
2098 
     else
2099 
     if (cke)
2100 
       zq <= q_next == {length{1'b0}};
2101 
 
2102 
    always @ (posedge clk or posedge rst)
2103 
    if (rst)
2104 
        level1 <= 1'b0;
2105 
    else
2106 
    if (cke)
2107 29 unneback 
    if (clear)
2108 
        level1 <= 1'b0;
2109 
    else if (q_next == level1_value)
2110 25 unneback 
        level1 <= 1'b1;
2111 
    else if (qi == level1_value & rew)
2112 
        level1 <= 1'b0;
2113 
endmodule
2114 40 unneback 
`endif
2115 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2116 25 unneback 
//////////////////////////////////////////////////////////////////////
2117 
////                                                              ////
2118 
////  Versatile counter                                           ////
2119 
////                                                              ////
2120 
////  Description                                                 ////
2121 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2122 
////  counter                                                     ////
2123 
////                                                              ////
2124 
////  To Do:                                                      ////
2125 
////   - add LFSR with more taps                                  ////
2126 
////                                                              ////
2127 
////  Author(s):                                                  ////
2128 
////      - Michael Unneback, unneback@opencores.org              ////
2129 
////        ORSoC AB                                              ////
2130 
////                                                              ////
2131 
//////////////////////////////////////////////////////////////////////
2132 
////                                                              ////
2133 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2134 
////                                                              ////
2135 
//// This source file may be used and distributed without         ////
2136 
//// restriction provided that this copyright statement is not    ////
2137 
//// removed from the file and that any derivative work contains  ////
2138 
//// the original copyright notice and the associated disclaimer. ////
2139 
////                                                              ////
2140 
//// This source file is free software; you can redistribute it   ////
2141 
//// and/or modify it under the terms of the GNU Lesser General   ////
2142 
//// Public License as published by the Free Software Foundation; ////
2143 
//// either version 2.1 of the License, or (at your option) any   ////
2144 
//// later version.                                               ////
2145 
////                                                              ////
2146 
//// This source is distributed in the hope that it will be       ////
2147 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2148 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2149 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2150 
//// details.                                                     ////
2151 
////                                                              ////
2152 
//// You should have received a copy of the GNU Lesser General    ////
2153 
//// Public License along with this source; if not, download it   ////
2154 
//// from http://www.opencores.org/lgpl.shtml                     ////
2155 
////                                                              ////
2156 
//////////////////////////////////////////////////////////////////////
2157 
 
2158 
// binary counter
2159 
 
2160 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2161 
module `BASE`MODULE (
2162 
`undef MODULE
2163 
 cke, rew, q, zq, level1, rst, clk);
2164 
 
2165 25 unneback 
   parameter length = 4;
2166 
   input cke;
2167 
   input rew;
2168 
   output [length:1] q;
2169 
   output reg zq;
2170 
   output reg level1;
2171 
   input rst;
2172 
   input clk;
2173 
 
2174 
   parameter clear_value = 0;
2175 
   parameter set_value = 1;
2176 
   parameter wrap_value = 1;
2177 
   parameter level1_value = 15;
2178 
 
2179 29 unneback 
   wire clear;
2180 30 unneback 
   assign clear = 1'b0;
2181 25 unneback 
   reg  [length:1] qi;
2182 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2183 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2184 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2185 
   assign q_next = rew ? q_next_rew : q_next_fw;
2186 
 
2187 
   always @ (posedge clk or posedge rst)
2188 
     if (rst)
2189 
       qi <= {length{1'b0}};
2190 
     else
2191 
     if (cke)
2192 
       qi <= q_next;
2193 
 
2194 
   assign q = qi;
2195 
 
2196 
 
2197 
   always @ (posedge clk or posedge rst)
2198 
     if (rst)
2199 
       zq <= 1'b1;
2200 
     else
2201 
     if (cke)
2202 
       zq <= q_next == {length{1'b0}};
2203 
 
2204 
    always @ (posedge clk or posedge rst)
2205 
    if (rst)
2206 
        level1 <= 1'b0;
2207 
    else
2208 
    if (cke)
2209 29 unneback 
    if (clear)
2210 
        level1 <= 1'b0;
2211 
    else if (q_next == level1_value)
2212 25 unneback 
        level1 <= 1'b1;
2213 
    else if (qi == level1_value & rew)
2214 
        level1 <= 1'b0;
2215 
endmodule
2216 40 unneback 
`endif
2217 
`ifdef CNT_LFSR_ZQ
2218 25 unneback 
//////////////////////////////////////////////////////////////////////
2219 
////                                                              ////
2220 
////  Versatile counter                                           ////
2221 
////                                                              ////
2222 
////  Description                                                 ////
2223 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2224 
////  counter                                                     ////
2225 
////                                                              ////
2226 
////  To Do:                                                      ////
2227 
////   - add LFSR with more taps                                  ////
2228 
////                                                              ////
2229 
////  Author(s):                                                  ////
2230 
////      - Michael Unneback, unneback@opencores.org              ////
2231 
////        ORSoC AB                                              ////
2232 
////                                                              ////
2233 
//////////////////////////////////////////////////////////////////////
2234 
////                                                              ////
2235 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2236 
////                                                              ////
2237 
//// This source file may be used and distributed without         ////
2238 
//// restriction provided that this copyright statement is not    ////
2239 
//// removed from the file and that any derivative work contains  ////
2240 
//// the original copyright notice and the associated disclaimer. ////
2241 
////                                                              ////
2242 
//// This source file is free software; you can redistribute it   ////
2243 
//// and/or modify it under the terms of the GNU Lesser General   ////
2244 
//// Public License as published by the Free Software Foundation; ////
2245 
//// either version 2.1 of the License, or (at your option) any   ////
2246 
//// later version.                                               ////
2247 
////                                                              ////
2248 
//// This source is distributed in the hope that it will be       ////
2249 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2250 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2251 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2252 
//// details.                                                     ////
2253 
////                                                              ////
2254 
//// You should have received a copy of the GNU Lesser General    ////
2255 
//// Public License along with this source; if not, download it   ////
2256 
//// from http://www.opencores.org/lgpl.shtml                     ////
2257 
////                                                              ////
2258 
//////////////////////////////////////////////////////////////////////
2259 
 
2260 6 unneback 
// LFSR counter
2261 
 
2262 40 unneback 
`define MODULE cnt_lfsr_zq
2263 
module `BASE`MODULE (
2264 
`undef MODULE
2265 
 zq, rst, clk);
2266 
 
2267 6 unneback 
   parameter length = 4;
2268 
   output reg zq;
2269 
   input rst;
2270 
   input clk;
2271 
 
2272 
   parameter clear_value = 0;
2273 
   parameter set_value = 1;
2274 
   parameter wrap_value = 8;
2275 
   parameter level1_value = 15;
2276 
 
2277 
   reg  [length:1] qi;
2278 
   reg lfsr_fb;
2279 
   wire [length:1] q_next;
2280 
   reg [32:1] polynom;
2281 
   integer i;
2282 
 
2283 
   always @ (qi)
2284 
   begin
2285 
        case (length)
2286 
         2: polynom = 32'b11;                               // 0x3
2287 
         3: polynom = 32'b110;                              // 0x6
2288 
         4: polynom = 32'b1100;                             // 0xC
2289 
         5: polynom = 32'b10100;                            // 0x14
2290 
         6: polynom = 32'b110000;                           // 0x30
2291 
         7: polynom = 32'b1100000;                          // 0x60
2292 
         8: polynom = 32'b10111000;                         // 0xb8
2293 
         9: polynom = 32'b100010000;                        // 0x110
2294 
        10: polynom = 32'b1001000000;                       // 0x240
2295 
        11: polynom = 32'b10100000000;                      // 0x500
2296 
        12: polynom = 32'b100000101001;                     // 0x829
2297 
        13: polynom = 32'b1000000001100;                    // 0x100C
2298 
        14: polynom = 32'b10000000010101;                   // 0x2015
2299 
        15: polynom = 32'b110000000000000;                  // 0x6000
2300 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2301 
        17: polynom = 32'b10010000000000000;                // 0x12000
2302 
        18: polynom = 32'b100000010000000000;               // 0x20400
2303 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2304 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2305 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2306 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2307 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2308 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2309 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2310 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2311 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2312 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2313 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2314 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2315 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2316 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2317 
        default: polynom = 32'b0;
2318 
        endcase
2319 
        lfsr_fb = qi[length];
2320 
        for (i=length-1; i>=1; i=i-1) begin
2321 
            if (polynom[i])
2322 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2323 
        end
2324 
    end
2325 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2326 
 
2327 
   always @ (posedge clk or posedge rst)
2328 
     if (rst)
2329 
       qi <= {length{1'b0}};
2330 
     else
2331 
       qi <= q_next;
2332 
 
2333 
 
2334 
 
2335 
   always @ (posedge clk or posedge rst)
2336 
     if (rst)
2337 
       zq <= 1'b1;
2338 
     else
2339 
       zq <= q_next == {length{1'b0}};
2340 
endmodule
2341 40 unneback 
`endif
2342 
`ifdef CNT_LFSR_CE_ZQ
2343 6 unneback 
//////////////////////////////////////////////////////////////////////
2344 
////                                                              ////
2345 
////  Versatile counter                                           ////
2346 
////                                                              ////
2347 
////  Description                                                 ////
2348 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2349 
////  counter                                                     ////
2350 
////                                                              ////
2351 
////  To Do:                                                      ////
2352 
////   - add LFSR with more taps                                  ////
2353 
////                                                              ////
2354 
////  Author(s):                                                  ////
2355 
////      - Michael Unneback, unneback@opencores.org              ////
2356 
////        ORSoC AB                                              ////
2357 
////                                                              ////
2358 
//////////////////////////////////////////////////////////////////////
2359 
////                                                              ////
2360 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2361 
////                                                              ////
2362 
//// This source file may be used and distributed without         ////
2363 
//// restriction provided that this copyright statement is not    ////
2364 
//// removed from the file and that any derivative work contains  ////
2365 
//// the original copyright notice and the associated disclaimer. ////
2366 
////                                                              ////
2367 
//// This source file is free software; you can redistribute it   ////
2368 
//// and/or modify it under the terms of the GNU Lesser General   ////
2369 
//// Public License as published by the Free Software Foundation; ////
2370 
//// either version 2.1 of the License, or (at your option) any   ////
2371 
//// later version.                                               ////
2372 
////                                                              ////
2373 
//// This source is distributed in the hope that it will be       ////
2374 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2375 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2376 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2377 
//// details.                                                     ////
2378 
////                                                              ////
2379 
//// You should have received a copy of the GNU Lesser General    ////
2380 
//// Public License along with this source; if not, download it   ////
2381 
//// from http://www.opencores.org/lgpl.shtml                     ////
2382 
////                                                              ////
2383 
//////////////////////////////////////////////////////////////////////
2384 
 
2385 
// LFSR counter
2386 
 
2387 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2388 
module `BASE`MODULE (
2389 
`undef MODULE
2390 
 cke, zq, rst, clk);
2391 
 
2392 6 unneback 
   parameter length = 4;
2393 
   input cke;
2394 
   output reg zq;
2395 
   input rst;
2396 
   input clk;
2397 
 
2398 
   parameter clear_value = 0;
2399 
   parameter set_value = 1;
2400 
   parameter wrap_value = 8;
2401 
   parameter level1_value = 15;
2402 
 
2403 
   reg  [length:1] qi;
2404 
   reg lfsr_fb;
2405 
   wire [length:1] q_next;
2406 
   reg [32:1] polynom;
2407 
   integer i;
2408 
 
2409 
   always @ (qi)
2410 
   begin
2411 
        case (length)
2412 
         2: polynom = 32'b11;                               // 0x3
2413 
         3: polynom = 32'b110;                              // 0x6
2414 
         4: polynom = 32'b1100;                             // 0xC
2415 
         5: polynom = 32'b10100;                            // 0x14
2416 
         6: polynom = 32'b110000;                           // 0x30
2417 
         7: polynom = 32'b1100000;                          // 0x60
2418 
         8: polynom = 32'b10111000;                         // 0xb8
2419 
         9: polynom = 32'b100010000;                        // 0x110
2420 
        10: polynom = 32'b1001000000;                       // 0x240
2421 
        11: polynom = 32'b10100000000;                      // 0x500
2422 
        12: polynom = 32'b100000101001;                     // 0x829
2423 
        13: polynom = 32'b1000000001100;                    // 0x100C
2424 
        14: polynom = 32'b10000000010101;                   // 0x2015
2425 
        15: polynom = 32'b110000000000000;                  // 0x6000
2426 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2427 
        17: polynom = 32'b10010000000000000;                // 0x12000
2428 
        18: polynom = 32'b100000010000000000;               // 0x20400
2429 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2430 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2431 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2432 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2433 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2434 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2435 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2436 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2437 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2438 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2439 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2440 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2441 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2442 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2443 
        default: polynom = 32'b0;
2444 
        endcase
2445 
        lfsr_fb = qi[length];
2446 
        for (i=length-1; i>=1; i=i-1) begin
2447 
            if (polynom[i])
2448 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2449 
        end
2450 
    end
2451 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2452 
 
2453 
   always @ (posedge clk or posedge rst)
2454 
     if (rst)
2455 
       qi <= {length{1'b0}};
2456 
     else
2457 
     if (cke)
2458 
       qi <= q_next;
2459 
 
2460 
 
2461 
 
2462 
   always @ (posedge clk or posedge rst)
2463 
     if (rst)
2464 
       zq <= 1'b1;
2465 
     else
2466 
     if (cke)
2467 
       zq <= q_next == {length{1'b0}};
2468 
endmodule
2469 40 unneback 
`endif
2470 
`ifdef CNT_LFSR_CE_Q
2471 6 unneback 
//////////////////////////////////////////////////////////////////////
2472 
////                                                              ////
2473 
////  Versatile counter                                           ////
2474 
////                                                              ////
2475 
////  Description                                                 ////
2476 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2477 
////  counter                                                     ////
2478 
////                                                              ////
2479 
////  To Do:                                                      ////
2480 
////   - add LFSR with more taps                                  ////
2481 
////                                                              ////
2482 
////  Author(s):                                                  ////
2483 
////      - Michael Unneback, unneback@opencores.org              ////
2484 
////        ORSoC AB                                              ////
2485 
////                                                              ////
2486 
//////////////////////////////////////////////////////////////////////
2487 
////                                                              ////
2488 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2489 
////                                                              ////
2490 
//// This source file may be used and distributed without         ////
2491 
//// restriction provided that this copyright statement is not    ////
2492 
//// removed from the file and that any derivative work contains  ////
2493 
//// the original copyright notice and the associated disclaimer. ////
2494 
////                                                              ////
2495 
//// This source file is free software; you can redistribute it   ////
2496 
//// and/or modify it under the terms of the GNU Lesser General   ////
2497 
//// Public License as published by the Free Software Foundation; ////
2498 
//// either version 2.1 of the License, or (at your option) any   ////
2499 
//// later version.                                               ////
2500 
////                                                              ////
2501 
//// This source is distributed in the hope that it will be       ////
2502 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2503 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2504 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2505 
//// details.                                                     ////
2506 
////                                                              ////
2507 
//// You should have received a copy of the GNU Lesser General    ////
2508 
//// Public License along with this source; if not, download it   ////
2509 
//// from http://www.opencores.org/lgpl.shtml                     ////
2510 
////                                                              ////
2511 
//////////////////////////////////////////////////////////////////////
2512 22 unneback 
 
2513 
// LFSR counter
2514 27 unneback 
 
2515 40 unneback 
`define MODULE cnt_lfsr_ce_q
2516 
module `BASE`MODULE (
2517 
`undef MODULE
2518 
 cke, q, rst, clk);
2519 
 
2520 27 unneback 
   parameter length = 4;
2521 
   input cke;
2522 
   output [length:1] q;
2523 
   input rst;
2524 
   input clk;
2525 
 
2526 
   parameter clear_value = 0;
2527 
   parameter set_value = 1;
2528 
   parameter wrap_value = 8;
2529 
   parameter level1_value = 15;
2530 
 
2531 
   reg  [length:1] qi;
2532 
   reg lfsr_fb;
2533 
   wire [length:1] q_next;
2534 
   reg [32:1] polynom;
2535 
   integer i;
2536 
 
2537 
   always @ (qi)
2538 
   begin
2539 
        case (length)
2540 
         2: polynom = 32'b11;                               // 0x3
2541 
         3: polynom = 32'b110;                              // 0x6
2542 
         4: polynom = 32'b1100;                             // 0xC
2543 
         5: polynom = 32'b10100;                            // 0x14
2544 
         6: polynom = 32'b110000;                           // 0x30
2545 
         7: polynom = 32'b1100000;                          // 0x60
2546 
         8: polynom = 32'b10111000;                         // 0xb8
2547 
         9: polynom = 32'b100010000;                        // 0x110
2548 
        10: polynom = 32'b1001000000;                       // 0x240
2549 
        11: polynom = 32'b10100000000;                      // 0x500
2550 
        12: polynom = 32'b100000101001;                     // 0x829
2551 
        13: polynom = 32'b1000000001100;                    // 0x100C
2552 
        14: polynom = 32'b10000000010101;                   // 0x2015
2553 
        15: polynom = 32'b110000000000000;                  // 0x6000
2554 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2555 
        17: polynom = 32'b10010000000000000;                // 0x12000
2556 
        18: polynom = 32'b100000010000000000;               // 0x20400
2557 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2558 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2559 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2560 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2561 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2562 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2563 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2564 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2565 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2566 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2567 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2568 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2569 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2570 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2571 
        default: polynom = 32'b0;
2572 
        endcase
2573 
        lfsr_fb = qi[length];
2574 
        for (i=length-1; i>=1; i=i-1) begin
2575 
            if (polynom[i])
2576 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2577 
        end
2578 
    end
2579 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2580 
 
2581 
   always @ (posedge clk or posedge rst)
2582 
     if (rst)
2583 
       qi <= {length{1'b0}};
2584 
     else
2585 
     if (cke)
2586 
       qi <= q_next;
2587 
 
2588 
   assign q = qi;
2589 
 
2590 
endmodule
2591 40 unneback 
`endif
2592 
`ifdef CNT_LFSR_CE_CLEAR_Q
2593 27 unneback 
//////////////////////////////////////////////////////////////////////
2594 
////                                                              ////
2595 
////  Versatile counter                                           ////
2596 
////                                                              ////
2597 
////  Description                                                 ////
2598 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2599 
////  counter                                                     ////
2600 
////                                                              ////
2601 
////  To Do:                                                      ////
2602 
////   - add LFSR with more taps                                  ////
2603 
////                                                              ////
2604 
////  Author(s):                                                  ////
2605 
////      - Michael Unneback, unneback@opencores.org              ////
2606 
////        ORSoC AB                                              ////
2607 
////                                                              ////
2608 
//////////////////////////////////////////////////////////////////////
2609 
////                                                              ////
2610 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2611 
////                                                              ////
2612 
//// This source file may be used and distributed without         ////
2613 
//// restriction provided that this copyright statement is not    ////
2614 
//// removed from the file and that any derivative work contains  ////
2615 
//// the original copyright notice and the associated disclaimer. ////
2616 
////                                                              ////
2617 
//// This source file is free software; you can redistribute it   ////
2618 
//// and/or modify it under the terms of the GNU Lesser General   ////
2619 
//// Public License as published by the Free Software Foundation; ////
2620 
//// either version 2.1 of the License, or (at your option) any   ////
2621 
//// later version.                                               ////
2622 
////                                                              ////
2623 
//// This source is distributed in the hope that it will be       ////
2624 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2625 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2626 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2627 
//// details.                                                     ////
2628 
////                                                              ////
2629 
//// You should have received a copy of the GNU Lesser General    ////
2630 
//// Public License along with this source; if not, download it   ////
2631 
//// from http://www.opencores.org/lgpl.shtml                     ////
2632 
////                                                              ////
2633 
//////////////////////////////////////////////////////////////////////
2634 
 
2635 
// LFSR counter
2636 
 
2637 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2638 
module `BASE`MODULE (
2639 
`undef MODULE
2640 
 clear, cke, q, rst, clk);
2641 
 
2642 27 unneback 
   parameter length = 4;
2643 
   input clear;
2644 
   input cke;
2645 
   output [length:1] q;
2646 
   input rst;
2647 
   input clk;
2648 
 
2649 
   parameter clear_value = 0;
2650 
   parameter set_value = 1;
2651 
   parameter wrap_value = 8;
2652 
   parameter level1_value = 15;
2653 
 
2654 
   reg  [length:1] qi;
2655 
   reg lfsr_fb;
2656 
   wire [length:1] q_next;
2657 
   reg [32:1] polynom;
2658 
   integer i;
2659 
 
2660 
   always @ (qi)
2661 
   begin
2662 
        case (length)
2663 
         2: polynom = 32'b11;                               // 0x3
2664 
         3: polynom = 32'b110;                              // 0x6
2665 
         4: polynom = 32'b1100;                             // 0xC
2666 
         5: polynom = 32'b10100;                            // 0x14
2667 
         6: polynom = 32'b110000;                           // 0x30
2668 
         7: polynom = 32'b1100000;                          // 0x60
2669 
         8: polynom = 32'b10111000;                         // 0xb8
2670 
         9: polynom = 32'b100010000;                        // 0x110
2671 
        10: polynom = 32'b1001000000;                       // 0x240
2672 
        11: polynom = 32'b10100000000;                      // 0x500
2673 
        12: polynom = 32'b100000101001;                     // 0x829
2674 
        13: polynom = 32'b1000000001100;                    // 0x100C
2675 
        14: polynom = 32'b10000000010101;                   // 0x2015
2676 
        15: polynom = 32'b110000000000000;                  // 0x6000
2677 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2678 
        17: polynom = 32'b10010000000000000;                // 0x12000
2679 
        18: polynom = 32'b100000010000000000;               // 0x20400
2680 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2681 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2682 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2683 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2684 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2685 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2686 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2687 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2688 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2689 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2690 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2691 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2692 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2693 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2694 
        default: polynom = 32'b0;
2695 
        endcase
2696 
        lfsr_fb = qi[length];
2697 
        for (i=length-1; i>=1; i=i-1) begin
2698 
            if (polynom[i])
2699 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2700 
        end
2701 
    end
2702 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2703 
 
2704 
   always @ (posedge clk or posedge rst)
2705 
     if (rst)
2706 
       qi <= {length{1'b0}};
2707 
     else
2708 
     if (cke)
2709 
       qi <= q_next;
2710 
 
2711 
   assign q = qi;
2712 
 
2713 
endmodule
2714 40 unneback 
`endif
2715 
`ifdef CNT_LFSR_CE_Q_ZQ
2716 27 unneback 
//////////////////////////////////////////////////////////////////////
2717 
////                                                              ////
2718 
////  Versatile counter                                           ////
2719 
////                                                              ////
2720 
////  Description                                                 ////
2721 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2722 
////  counter                                                     ////
2723 
////                                                              ////
2724 
////  To Do:                                                      ////
2725 
////   - add LFSR with more taps                                  ////
2726 
////                                                              ////
2727 
////  Author(s):                                                  ////
2728 
////      - Michael Unneback, unneback@opencores.org              ////
2729 
////        ORSoC AB                                              ////
2730 
////                                                              ////
2731 
//////////////////////////////////////////////////////////////////////
2732 
////                                                              ////
2733 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2734 
////                                                              ////
2735 
//// This source file may be used and distributed without         ////
2736 
//// restriction provided that this copyright statement is not    ////
2737 
//// removed from the file and that any derivative work contains  ////
2738 
//// the original copyright notice and the associated disclaimer. ////
2739 
////                                                              ////
2740 
//// This source file is free software; you can redistribute it   ////
2741 
//// and/or modify it under the terms of the GNU Lesser General   ////
2742 
//// Public License as published by the Free Software Foundation; ////
2743 
//// either version 2.1 of the License, or (at your option) any   ////
2744 
//// later version.                                               ////
2745 
////                                                              ////
2746 
//// This source is distributed in the hope that it will be       ////
2747 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2748 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2749 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2750 
//// details.                                                     ////
2751 
////                                                              ////
2752 
//// You should have received a copy of the GNU Lesser General    ////
2753 
//// Public License along with this source; if not, download it   ////
2754 
//// from http://www.opencores.org/lgpl.shtml                     ////
2755 
////                                                              ////
2756 
//////////////////////////////////////////////////////////////////////
2757 
 
2758 
// LFSR counter
2759 22 unneback 
 
2760 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2761 
module `BASE`MODULE (
2762 
`undef MODULE
2763 
 cke, q, zq, rst, clk);
2764 
 
2765 22 unneback 
   parameter length = 4;
2766 
   input cke;
2767 
   output [length:1] q;
2768 
   output reg zq;
2769 
   input rst;
2770 
   input clk;
2771 
 
2772 
   parameter clear_value = 0;
2773 
   parameter set_value = 1;
2774 
   parameter wrap_value = 8;
2775 
   parameter level1_value = 15;
2776 
 
2777 
   reg  [length:1] qi;
2778 
   reg lfsr_fb;
2779 
   wire [length:1] q_next;
2780 
   reg [32:1] polynom;
2781 
   integer i;
2782 
 
2783 
   always @ (qi)
2784 
   begin
2785 
        case (length)
2786 
         2: polynom = 32'b11;                               // 0x3
2787 
         3: polynom = 32'b110;                              // 0x6
2788 
         4: polynom = 32'b1100;                             // 0xC
2789 
         5: polynom = 32'b10100;                            // 0x14
2790 
         6: polynom = 32'b110000;                           // 0x30
2791 
         7: polynom = 32'b1100000;                          // 0x60
2792 
         8: polynom = 32'b10111000;                         // 0xb8
2793 
         9: polynom = 32'b100010000;                        // 0x110
2794 
        10: polynom = 32'b1001000000;                       // 0x240
2795 
        11: polynom = 32'b10100000000;                      // 0x500
2796 
        12: polynom = 32'b100000101001;                     // 0x829
2797 
        13: polynom = 32'b1000000001100;                    // 0x100C
2798 
        14: polynom = 32'b10000000010101;                   // 0x2015
2799 
        15: polynom = 32'b110000000000000;                  // 0x6000
2800 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2801 
        17: polynom = 32'b10010000000000000;                // 0x12000
2802 
        18: polynom = 32'b100000010000000000;               // 0x20400
2803 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2804 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2805 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2806 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2807 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2808 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2809 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2810 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2811 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2812 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2813 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2814 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2815 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2816 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2817 
        default: polynom = 32'b0;
2818 
        endcase
2819 
        lfsr_fb = qi[length];
2820 
        for (i=length-1; i>=1; i=i-1) begin
2821 
            if (polynom[i])
2822 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2823 
        end
2824 
    end
2825 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2826 
 
2827 
   always @ (posedge clk or posedge rst)
2828 
     if (rst)
2829 
       qi <= {length{1'b0}};
2830 
     else
2831 
     if (cke)
2832 
       qi <= q_next;
2833 
 
2834 
   assign q = qi;
2835 
 
2836 
 
2837 
   always @ (posedge clk or posedge rst)
2838 
     if (rst)
2839 
       zq <= 1'b1;
2840 
     else
2841 
     if (cke)
2842 
       zq <= q_next == {length{1'b0}};
2843 
endmodule
2844 40 unneback 
`endif
2845 
`ifdef CNT_LFSR_CE_REW_L1
2846 22 unneback 
//////////////////////////////////////////////////////////////////////
2847 
////                                                              ////
2848 
////  Versatile counter                                           ////
2849 
////                                                              ////
2850 
////  Description                                                 ////
2851 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2852 
////  counter                                                     ////
2853 
////                                                              ////
2854 
////  To Do:                                                      ////
2855 
////   - add LFSR with more taps                                  ////
2856 
////                                                              ////
2857 
////  Author(s):                                                  ////
2858 
////      - Michael Unneback, unneback@opencores.org              ////
2859 
////        ORSoC AB                                              ////
2860 
////                                                              ////
2861 
//////////////////////////////////////////////////////////////////////
2862 
////                                                              ////
2863 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2864 
////                                                              ////
2865 
//// This source file may be used and distributed without         ////
2866 
//// restriction provided that this copyright statement is not    ////
2867 
//// removed from the file and that any derivative work contains  ////
2868 
//// the original copyright notice and the associated disclaimer. ////
2869 
////                                                              ////
2870 
//// This source file is free software; you can redistribute it   ////
2871 
//// and/or modify it under the terms of the GNU Lesser General   ////
2872 
//// Public License as published by the Free Software Foundation; ////
2873 
//// either version 2.1 of the License, or (at your option) any   ////
2874 
//// later version.                                               ////
2875 
////                                                              ////
2876 
//// This source is distributed in the hope that it will be       ////
2877 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2878 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2879 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2880 
//// details.                                                     ////
2881 
////                                                              ////
2882 
//// You should have received a copy of the GNU Lesser General    ////
2883 
//// Public License along with this source; if not, download it   ////
2884 
//// from http://www.opencores.org/lgpl.shtml                     ////
2885 
////                                                              ////
2886 
//////////////////////////////////////////////////////////////////////
2887 6 unneback 
 
2888 
// LFSR counter
2889 
 
2890 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
2891 
module `BASE`MODULE (
2892 
`undef MODULE
2893 
 cke, rew, level1, rst, clk);
2894 
 
2895 6 unneback 
   parameter length = 4;
2896 
   input cke;
2897 
   input rew;
2898 
   output reg level1;
2899 
   input rst;
2900 
   input clk;
2901 
 
2902 
   parameter clear_value = 0;
2903 
   parameter set_value = 1;
2904 
   parameter wrap_value = 8;
2905 
   parameter level1_value = 15;
2906 
 
2907 29 unneback 
   wire clear;
2908 30 unneback 
   assign clear = 1'b0;
2909 6 unneback 
   reg  [length:1] qi;
2910 
   reg lfsr_fb, lfsr_fb_rew;
2911 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2912 
   reg [32:1] polynom_rew;
2913 
   integer j;
2914 
   reg [32:1] polynom;
2915 
   integer i;
2916 
 
2917 
   always @ (qi)
2918 
   begin
2919 
        case (length)
2920 
         2: polynom = 32'b11;                               // 0x3
2921 
         3: polynom = 32'b110;                              // 0x6
2922 
         4: polynom = 32'b1100;                             // 0xC
2923 
         5: polynom = 32'b10100;                            // 0x14
2924 
         6: polynom = 32'b110000;                           // 0x30
2925 
         7: polynom = 32'b1100000;                          // 0x60
2926 
         8: polynom = 32'b10111000;                         // 0xb8
2927 
         9: polynom = 32'b100010000;                        // 0x110
2928 
        10: polynom = 32'b1001000000;                       // 0x240
2929 
        11: polynom = 32'b10100000000;                      // 0x500
2930 
        12: polynom = 32'b100000101001;                     // 0x829
2931 
        13: polynom = 32'b1000000001100;                    // 0x100C
2932 
        14: polynom = 32'b10000000010101;                   // 0x2015
2933 
        15: polynom = 32'b110000000000000;                  // 0x6000
2934 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2935 
        17: polynom = 32'b10010000000000000;                // 0x12000
2936 
        18: polynom = 32'b100000010000000000;               // 0x20400
2937 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2938 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2939 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2940 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2941 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2942 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2943 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2944 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2945 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2946 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2947 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2948 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2949 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2950 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2951 
        default: polynom = 32'b0;
2952 
        endcase
2953 
        lfsr_fb = qi[length];
2954 
        for (i=length-1; i>=1; i=i-1) begin
2955 
            if (polynom[i])
2956 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2957 
        end
2958 
    end
2959 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2960 
   always @ (qi)
2961 
   begin
2962 
        case (length)
2963 
         2: polynom_rew = 32'b11;
2964 
         3: polynom_rew = 32'b110;
2965 
         4: polynom_rew = 32'b1100;
2966 
         5: polynom_rew = 32'b10100;
2967 
         6: polynom_rew = 32'b110000;
2968 
         7: polynom_rew = 32'b1100000;
2969 
         8: polynom_rew = 32'b10111000;
2970 
         9: polynom_rew = 32'b100010000;
2971 
        10: polynom_rew = 32'b1001000000;
2972 
        11: polynom_rew = 32'b10100000000;
2973 
        12: polynom_rew = 32'b100000101001;
2974 
        13: polynom_rew = 32'b1000000001100;
2975 
        14: polynom_rew = 32'b10000000010101;
2976 
        15: polynom_rew = 32'b110000000000000;
2977 
        16: polynom_rew = 32'b1101000000001000;
2978 
        17: polynom_rew = 32'b10010000000000000;
2979 
        18: polynom_rew = 32'b100000010000000000;
2980 
        19: polynom_rew = 32'b1000000000000100011;
2981 
        20: polynom_rew = 32'b10000010000000000000;
2982 
        21: polynom_rew = 32'b101000000000000000000;
2983 
        22: polynom_rew = 32'b1100000000000000000000;
2984 
        23: polynom_rew = 32'b10000100000000000000000;
2985 
        24: polynom_rew = 32'b111000010000000000000000;
2986 
        25: polynom_rew = 32'b1001000000000000000000000;
2987 
        26: polynom_rew = 32'b10000000000000000000100011;
2988 
        27: polynom_rew = 32'b100000000000000000000010011;
2989 
        28: polynom_rew = 32'b1100100000000000000000000000;
2990 
        29: polynom_rew = 32'b10100000000000000000000000000;
2991 
        30: polynom_rew = 32'b100000000000000000000000101001;
2992 
        31: polynom_rew = 32'b1001000000000000000000000000000;
2993 
        32: polynom_rew = 32'b10000000001000000000000000000011;
2994 
        default: polynom_rew = 32'b0;
2995 
        endcase
2996 
        // rotate left
2997 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2998 
        lfsr_fb_rew = qi[length];
2999 
        for (i=length-1; i>=1; i=i-1) begin
3000 
            if (polynom_rew[i])
3001 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3002 
        end
3003 
    end
3004 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3005 
   assign q_next = rew ? q_next_rew : q_next_fw;
3006 
 
3007 
   always @ (posedge clk or posedge rst)
3008 
     if (rst)
3009 
       qi <= {length{1'b0}};
3010 
     else
3011 
     if (cke)
3012 
       qi <= q_next;
3013 
 
3014 
 
3015 
 
3016 
    always @ (posedge clk or posedge rst)
3017 
    if (rst)
3018 
        level1 <= 1'b0;
3019 
    else
3020 
    if (cke)
3021 29 unneback 
    if (clear)
3022 
        level1 <= 1'b0;
3023 
    else if (q_next == level1_value)
3024 6 unneback 
        level1 <= 1'b1;
3025 
    else if (qi == level1_value & rew)
3026 
        level1 <= 1'b0;
3027 
endmodule
3028 40 unneback 
`endif
3029 
`ifdef CNT_GRAY
3030 6 unneback 
//////////////////////////////////////////////////////////////////////
3031 
////                                                              ////
3032 
////  Versatile counter                                           ////
3033 
////                                                              ////
3034 
////  Description                                                 ////
3035 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3036 
////  counter                                                     ////
3037 
////                                                              ////
3038 
////  To Do:                                                      ////
3039 
////   - add LFSR with more taps                                  ////
3040 
////                                                              ////
3041 
////  Author(s):                                                  ////
3042 
////      - Michael Unneback, unneback@opencores.org              ////
3043 
////        ORSoC AB                                              ////
3044 
////                                                              ////
3045 
//////////////////////////////////////////////////////////////////////
3046 
////                                                              ////
3047 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3048 
////                                                              ////
3049 
//// This source file may be used and distributed without         ////
3050 
//// restriction provided that this copyright statement is not    ////
3051 
//// removed from the file and that any derivative work contains  ////
3052 
//// the original copyright notice and the associated disclaimer. ////
3053 
////                                                              ////
3054 
//// This source file is free software; you can redistribute it   ////
3055 
//// and/or modify it under the terms of the GNU Lesser General   ////
3056 
//// Public License as published by the Free Software Foundation; ////
3057 
//// either version 2.1 of the License, or (at your option) any   ////
3058 
//// later version.                                               ////
3059 
////                                                              ////
3060 
//// This source is distributed in the hope that it will be       ////
3061 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3062 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3063 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3064 
//// details.                                                     ////
3065 
////                                                              ////
3066 
//// You should have received a copy of the GNU Lesser General    ////
3067 
//// Public License along with this source; if not, download it   ////
3068 
//// from http://www.opencores.org/lgpl.shtml                     ////
3069 
////                                                              ////
3070 
//////////////////////////////////////////////////////////////////////
3071 
 
3072 
// GRAY counter
3073 
 
3074 40 unneback 
`define MODULE cnt_gray
3075 
module `BASE`MODULE (
3076 
`undef MODULE
3077 
 q, rst, clk);
3078 
 
3079 6 unneback 
   parameter length = 4;
3080 
   output reg [length:1] q;
3081 
   input rst;
3082 
   input clk;
3083 
 
3084 
   parameter clear_value = 0;
3085 
   parameter set_value = 1;
3086 
   parameter wrap_value = 8;
3087 
   parameter level1_value = 15;
3088 
 
3089 
   reg  [length:1] qi;
3090 
   wire [length:1] q_next;
3091 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3092 
 
3093 
   always @ (posedge clk or posedge rst)
3094 
     if (rst)
3095 
       qi <= {length{1'b0}};
3096 
     else
3097 
       qi <= q_next;
3098 
 
3099 
   always @ (posedge clk or posedge rst)
3100 
     if (rst)
3101 
       q <= {length{1'b0}};
3102 
     else
3103 
         q <= (q_next>>1) ^ q_next;
3104 
 
3105 
endmodule
3106 40 unneback 
`endif
3107 
`ifdef CNT_GRAY_CE
3108 6 unneback 
//////////////////////////////////////////////////////////////////////
3109 
////                                                              ////
3110 
////  Versatile counter                                           ////
3111 
////                                                              ////
3112 
////  Description                                                 ////
3113 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3114 
////  counter                                                     ////
3115 
////                                                              ////
3116 
////  To Do:                                                      ////
3117 
////   - add LFSR with more taps                                  ////
3118 
////                                                              ////
3119 
////  Author(s):                                                  ////
3120 
////      - Michael Unneback, unneback@opencores.org              ////
3121 
////        ORSoC AB                                              ////
3122 
////                                                              ////
3123 
//////////////////////////////////////////////////////////////////////
3124 
////                                                              ////
3125 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3126 
////                                                              ////
3127 
//// This source file may be used and distributed without         ////
3128 
//// restriction provided that this copyright statement is not    ////
3129 
//// removed from the file and that any derivative work contains  ////
3130 
//// the original copyright notice and the associated disclaimer. ////
3131 
////                                                              ////
3132 
//// This source file is free software; you can redistribute it   ////
3133 
//// and/or modify it under the terms of the GNU Lesser General   ////
3134 
//// Public License as published by the Free Software Foundation; ////
3135 
//// either version 2.1 of the License, or (at your option) any   ////
3136 
//// later version.                                               ////
3137 
////                                                              ////
3138 
//// This source is distributed in the hope that it will be       ////
3139 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3140 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3141 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3142 
//// details.                                                     ////
3143 
////                                                              ////
3144 
//// You should have received a copy of the GNU Lesser General    ////
3145 
//// Public License along with this source; if not, download it   ////
3146 
//// from http://www.opencores.org/lgpl.shtml                     ////
3147 
////                                                              ////
3148 
//////////////////////////////////////////////////////////////////////
3149 
 
3150 
// GRAY counter
3151 
 
3152 40 unneback 
`define MODULE cnt_gray_ce
3153 
module `BASE`MODULE (
3154 
`undef MODULE
3155 
 cke, q, rst, clk);
3156 
 
3157 6 unneback 
   parameter length = 4;
3158 
   input cke;
3159 
   output reg [length:1] q;
3160 
   input rst;
3161 
   input clk;
3162 
 
3163 
   parameter clear_value = 0;
3164 
   parameter set_value = 1;
3165 
   parameter wrap_value = 8;
3166 
   parameter level1_value = 15;
3167 
 
3168 
   reg  [length:1] qi;
3169 
   wire [length:1] q_next;
3170 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3171 
 
3172 
   always @ (posedge clk or posedge rst)
3173 
     if (rst)
3174 
       qi <= {length{1'b0}};
3175 
     else
3176 
     if (cke)
3177 
       qi <= q_next;
3178 
 
3179 
   always @ (posedge clk or posedge rst)
3180 
     if (rst)
3181 
       q <= {length{1'b0}};
3182 
     else
3183 
       if (cke)
3184 
         q <= (q_next>>1) ^ q_next;
3185 
 
3186 
endmodule
3187 40 unneback 
`endif
3188 
`ifdef CNT_GRAY_CE_BIN
3189 6 unneback 
//////////////////////////////////////////////////////////////////////
3190 
////                                                              ////
3191 
////  Versatile counter                                           ////
3192 
////                                                              ////
3193 
////  Description                                                 ////
3194 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3195 
////  counter                                                     ////
3196 
////                                                              ////
3197 
////  To Do:                                                      ////
3198 
////   - add LFSR with more taps                                  ////
3199 
////                                                              ////
3200 
////  Author(s):                                                  ////
3201 
////      - Michael Unneback, unneback@opencores.org              ////
3202 
////        ORSoC AB                                              ////
3203 
////                                                              ////
3204 
//////////////////////////////////////////////////////////////////////
3205 
////                                                              ////
3206 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3207 
////                                                              ////
3208 
//// This source file may be used and distributed without         ////
3209 
//// restriction provided that this copyright statement is not    ////
3210 
//// removed from the file and that any derivative work contains  ////
3211 
//// the original copyright notice and the associated disclaimer. ////
3212 
////                                                              ////
3213 
//// This source file is free software; you can redistribute it   ////
3214 
//// and/or modify it under the terms of the GNU Lesser General   ////
3215 
//// Public License as published by the Free Software Foundation; ////
3216 
//// either version 2.1 of the License, or (at your option) any   ////
3217 
//// later version.                                               ////
3218 
////                                                              ////
3219 
//// This source is distributed in the hope that it will be       ////
3220 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3221 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3222 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3223 
//// details.                                                     ////
3224 
////                                                              ////
3225 
//// You should have received a copy of the GNU Lesser General    ////
3226 
//// Public License along with this source; if not, download it   ////
3227 
//// from http://www.opencores.org/lgpl.shtml                     ////
3228 
////                                                              ////
3229 
//////////////////////////////////////////////////////////////////////
3230 
 
3231 
// GRAY counter
3232 
 
3233 40 unneback 
`define MODULE cnt_gray_ce_bin
3234 
module `BASE`MODULE (
3235 
`undef MODULE
3236 
 cke, q, q_bin, rst, clk);
3237 
 
3238 6 unneback 
   parameter length = 4;
3239 
   input cke;
3240 
   output reg [length:1] q;
3241 
   output [length:1] q_bin;
3242 
   input rst;
3243 
   input clk;
3244 
 
3245 
   parameter clear_value = 0;
3246 
   parameter set_value = 1;
3247 
   parameter wrap_value = 8;
3248 
   parameter level1_value = 15;
3249 
 
3250 
   reg  [length:1] qi;
3251 
   wire [length:1] q_next;
3252 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3253 
 
3254 
   always @ (posedge clk or posedge rst)
3255 
     if (rst)
3256 
       qi <= {length{1'b0}};
3257 
     else
3258 
     if (cke)
3259 
       qi <= q_next;
3260 
 
3261 
   always @ (posedge clk or posedge rst)
3262 
     if (rst)
3263 
       q <= {length{1'b0}};
3264 
     else
3265 
       if (cke)
3266 
         q <= (q_next>>1) ^ q_next;
3267 
 
3268 
   assign q_bin = qi;
3269 
 
3270 
endmodule
3271 40 unneback 
`endif
3272 6 unneback 
//////////////////////////////////////////////////////////////////////
3273 
////                                                              ////
3274 
////  Versatile library, counters                                 ////
3275 
////                                                              ////
3276 
////  Description                                                 ////
3277 
////  counters                                                    ////
3278 
////                                                              ////
3279 
////                                                              ////
3280 
////  To Do:                                                      ////
3281 
////   - add more counters                                        ////
3282 
////                                                              ////
3283 
////  Author(s):                                                  ////
3284 
////      - Michael Unneback, unneback@opencores.org              ////
3285 
////        ORSoC AB                                              ////
3286 
////                                                              ////
3287 
//////////////////////////////////////////////////////////////////////
3288 
////                                                              ////
3289 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3290 
////                                                              ////
3291 
//// This source file may be used and distributed without         ////
3292 
//// restriction provided that this copyright statement is not    ////
3293 
//// removed from the file and that any derivative work contains  ////
3294 
//// the original copyright notice and the associated disclaimer. ////
3295 
////                                                              ////
3296 
//// This source file is free software; you can redistribute it   ////
3297 
//// and/or modify it under the terms of the GNU Lesser General   ////
3298 
//// Public License as published by the Free Software Foundation; ////
3299 
//// either version 2.1 of the License, or (at your option) any   ////
3300 
//// later version.                                               ////
3301 
////                                                              ////
3302 
//// This source is distributed in the hope that it will be       ////
3303 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3304 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3305 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3306 
//// details.                                                     ////
3307 
////                                                              ////
3308 
//// You should have received a copy of the GNU Lesser General    ////
3309 
//// Public License along with this source; if not, download it   ////
3310 
//// from http://www.opencores.org/lgpl.shtml                     ////
3311 
////                                                              ////
3312 
//////////////////////////////////////////////////////////////////////
3313 
 
3314 40 unneback 
`ifdef CNT_SHREG_WRAP
3315 
`define MODULE cnt_shreg_wrap
3316 
module `BASE`MODULE ( q, rst, clk);
3317 
`undef MODULE
3318 6 unneback 
 
3319 
   parameter length = 4;
3320 
   output reg [0:length-1] q;
3321 
   input rst;
3322 
   input clk;
3323 
 
3324 
    always @ (posedge clk or posedge rst)
3325 
    if (rst)
3326 
        q <= {1'b1,{length-1{1'b0}}};
3327 
    else
3328 
        q <= {q[length-1],q[0:length-2]};
3329 
 
3330 
endmodule
3331 40 unneback 
`endif
3332 6 unneback 
 
3333 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3334 
`define MODULE cnt_shreg_ce_wrap
3335 
module `BASE`MODULE ( cke, q, rst, clk);
3336 
`undef MODULE
3337 6 unneback 
 
3338 
   parameter length = 4;
3339 
   input cke;
3340 
   output reg [0:length-1] q;
3341 
   input rst;
3342 
   input clk;
3343 
 
3344 
    always @ (posedge clk or posedge rst)
3345 
    if (rst)
3346 
        q <= {1'b1,{length-1{1'b0}}};
3347 
    else
3348 
        if (cke)
3349 
            q <= {q[length-1],q[0:length-2]};
3350 
 
3351 
endmodule
3352 40 unneback 
`endif
3353 6 unneback 
 
3354 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3355 
`define MODULE cnt_shreg_ce_clear
3356 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3357 
`undef MODULE
3358 6 unneback 
 
3359 
   parameter length = 4;
3360 
   input cke, clear;
3361 
   output reg [0:length-1] q;
3362 
   input rst;
3363 
   input clk;
3364 
 
3365 
    always @ (posedge clk or posedge rst)
3366 
    if (rst)
3367 
        q <= {1'b1,{length-1{1'b0}}};
3368 
    else
3369 
        if (cke)
3370 
            if (clear)
3371 
                q <= {1'b1,{length-1{1'b0}}};
3372 
            else
3373 
                q <= q >> 1;
3374 
 
3375 
endmodule
3376 40 unneback 
`endif
3377 6 unneback 
 
3378 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3379 
`define MODULE cnt_shreg_ce_clear_wrap
3380 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3381 
`undef MODULE
3382 6 unneback 
 
3383 
   parameter length = 4;
3384 
   input cke, clear;
3385 
   output reg [0:length-1] q;
3386 
   input rst;
3387 
   input clk;
3388 
 
3389 
    always @ (posedge clk or posedge rst)
3390 
    if (rst)
3391 
        q <= {1'b1,{length-1{1'b0}}};
3392 
    else
3393 
        if (cke)
3394 
            if (clear)
3395 
                q <= {1'b1,{length-1{1'b0}}};
3396 
            else
3397 
            q <= {q[length-1],q[0:length-2]};
3398 
 
3399 
endmodule
3400 40 unneback 
`endif
3401 6 unneback 
//////////////////////////////////////////////////////////////////////
3402 
////                                                              ////
3403 
////  Versatile library, memories                                 ////
3404 
////                                                              ////
3405 
////  Description                                                 ////
3406 
////  memories                                                    ////
3407 
////                                                              ////
3408 
////                                                              ////
3409 
////  To Do:                                                      ////
3410 
////   - add more memory types                                    ////
3411 
////                                                              ////
3412 
////  Author(s):                                                  ////
3413 
////      - Michael Unneback, unneback@opencores.org              ////
3414 
////        ORSoC AB                                              ////
3415 
////                                                              ////
3416 
//////////////////////////////////////////////////////////////////////
3417 
////                                                              ////
3418 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3419 
////                                                              ////
3420 
//// This source file may be used and distributed without         ////
3421 
//// restriction provided that this copyright statement is not    ////
3422 
//// removed from the file and that any derivative work contains  ////
3423 
//// the original copyright notice and the associated disclaimer. ////
3424 
////                                                              ////
3425 
//// This source file is free software; you can redistribute it   ////
3426 
//// and/or modify it under the terms of the GNU Lesser General   ////
3427 
//// Public License as published by the Free Software Foundation; ////
3428 
//// either version 2.1 of the License, or (at your option) any   ////
3429 
//// later version.                                               ////
3430 
////                                                              ////
3431 
//// This source is distributed in the hope that it will be       ////
3432 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3433 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3434 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3435 
//// details.                                                     ////
3436 
////                                                              ////
3437 
//// You should have received a copy of the GNU Lesser General    ////
3438 
//// Public License along with this source; if not, download it   ////
3439 
//// from http://www.opencores.org/lgpl.shtml                     ////
3440 
////                                                              ////
3441 
//////////////////////////////////////////////////////////////////////
3442 
 
3443 40 unneback 
`ifdef ROM_INIT
3444 6 unneback 
/// ROM
3445 40 unneback 
`define MODULE rom_init
3446 
module `BASE`MODULE ( adr, q, clk);
3447 
`undef MODULE
3448 6 unneback 
 
3449 7 unneback 
   parameter data_width = 32;
3450 
   parameter addr_width = 8;
3451 
   input [(addr_width-1):0]       adr;
3452 
   output reg [(data_width-1):0] q;
3453 
   input                         clk;
3454 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3455 
   parameter memory_file = "vl_rom.vmem";
3456 
   initial
3457 
     begin
3458 
        $readmemh(memory_file, rom);
3459 
     end
3460 
 
3461 
   always @ (posedge clk)
3462 
     q <= rom[adr];
3463 6 unneback 
 
3464 7 unneback 
endmodule
3465 40 unneback 
`endif
3466 7 unneback 
 
3467 14 unneback 
/*
3468 7 unneback 
module vl_rom ( adr, q, clk);
3469 
 
3470 6 unneback 
parameter data_width = 32;
3471 
parameter addr_width = 4;
3472 
 
3473 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
3474 
    {32'h18000000},
3475 
    {32'hA8200000},
3476 
    {32'hA8200000},
3477 
    {32'hA8200000},
3478 
    {32'h44003000},
3479 
    {32'h15000000},
3480 
    {32'h15000000},
3481 
    {32'h15000000},
3482 
    {32'h15000000},
3483 
    {32'h15000000},
3484 
    {32'h15000000},
3485 
    {32'h15000000},
3486 
    {32'h15000000},
3487 
    {32'h15000000},
3488 
    {32'h15000000},
3489 
    {32'h15000000}};
3490 
 
3491 7 unneback 
input [addr_width-1:0] adr;
3492 6 unneback 
output reg [data_width-1:0] q;
3493 
input clk;
3494 
 
3495 
always @ (posedge clk)
3496 7 unneback 
    q <= data[adr];
3497 6 unneback 
 
3498 
endmodule
3499 14 unneback 
*/
3500 40 unneback 
 
3501 
`ifdef RAM
3502 
`define MODULE ram
3503 6 unneback 
// Single port RAM
3504 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3505 
`undef MODULE
3506 6 unneback 
 
3507 
   parameter data_width = 32;
3508 
   parameter addr_width = 8;
3509 
   input [(data_width-1):0]      d;
3510 
   input [(addr_width-1):0]       adr;
3511 
   input                         we;
3512 7 unneback 
   output reg [(data_width-1):0] q;
3513 6 unneback 
   input                         clk;
3514 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3515 7 unneback 
   parameter init = 0;
3516 
   parameter memory_file = "vl_ram.vmem";
3517 
   generate if (init) begin : init_mem
3518 
   initial
3519 
     begin
3520 
        $readmemh(memory_file, ram);
3521 
     end
3522 
   end
3523 
   endgenerate
3524 
 
3525 6 unneback 
   always @ (posedge clk)
3526 
   begin
3527 
   if (we)
3528 
     ram[adr] <= d;
3529 
   q <= ram[adr];
3530 
   end
3531 
 
3532 
endmodule
3533 40 unneback 
`endif
3534 6 unneback 
 
3535 40 unneback 
`ifdef RAM_BE
3536 
`define MODULE ram_be
3537 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3538 
`undef MODULE
3539 
 
3540 7 unneback 
   parameter data_width = 32;
3541 
   parameter addr_width = 8;
3542 
   input [(data_width-1):0]      d;
3543 
   input [(addr_width-1):0]       adr;
3544 
   input [(addr_width/4)-1:0]    be;
3545 
   input                         we;
3546 
   output reg [(data_width-1):0] q;
3547 
   input                         clk;
3548 
 
3549 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3550 
 
3551 
   parameter init = 0;
3552 
   parameter memory_file = "vl_ram.vmem";
3553 
   generate if (init) begin : init_mem
3554 
   initial
3555 
     begin
3556 
        $readmemh(memory_file, ram);
3557 
     end
3558 
   end
3559 
   endgenerate
3560 
 
3561 
   genvar i;
3562 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3563 
      always @ (posedge clk)
3564 
      if (we & be[i])
3565 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3566 
   end
3567 
   endgenerate
3568 
 
3569 
   always @ (posedge clk)
3570 
      q <= ram[adr];
3571 
 
3572 
endmodule
3573 40 unneback 
`endif
3574 7 unneback 
 
3575 6 unneback 
// Dual port RAM
3576 
 
3577 
// ACTEL FPGA should not use logic to handle rw collision
3578 
`ifdef ACTEL
3579 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3580 
`else
3581 
        `define SYN
3582 
`endif
3583 
 
3584 40 unneback 
`ifdef DPRAM_1R1W
3585 
`define MODULE dpram_1r1w
3586 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3587 
`undef MODULE
3588 6 unneback 
   parameter data_width = 32;
3589 
   parameter addr_width = 8;
3590 
   input [(data_width-1):0]      d_a;
3591 
   input [(addr_width-1):0]       adr_a;
3592 
   input [(addr_width-1):0]       adr_b;
3593 
   input                         we_a;
3594 
   output [(data_width-1):0]      q_b;
3595 
   input                         clk_a, clk_b;
3596 
   reg [(addr_width-1):0]         adr_b_reg;
3597 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3598 7 unneback 
 
3599 
   parameter init = 0;
3600 
   parameter memory_file = "vl_ram.vmem";
3601 
   generate if (init) begin : init_mem
3602 
   initial
3603 
     begin
3604 
        $readmemh(memory_file, ram);
3605 
     end
3606 
   end
3607 
   endgenerate
3608 
 
3609 6 unneback 
   always @ (posedge clk_a)
3610 
   if (we_a)
3611 
     ram[adr_a] <= d_a;
3612 
   always @ (posedge clk_b)
3613 
   adr_b_reg <= adr_b;
3614 
   assign q_b = ram[adr_b_reg];
3615 40 unneback 
 
3616 6 unneback 
endmodule
3617 40 unneback 
`endif
3618 6 unneback 
 
3619 40 unneback 
`ifdef DPRAM_2R1W
3620 
`define MODULE dpram_2r1w
3621 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3622 
`undef MODULE
3623 
 
3624 6 unneback 
   parameter data_width = 32;
3625 
   parameter addr_width = 8;
3626 
   input [(data_width-1):0]      d_a;
3627 
   input [(addr_width-1):0]       adr_a;
3628 
   input [(addr_width-1):0]       adr_b;
3629 
   input                         we_a;
3630 
   output [(data_width-1):0]      q_b;
3631 
   output reg [(data_width-1):0] q_a;
3632 
   input                         clk_a, clk_b;
3633 
   reg [(data_width-1):0]         q_b;
3634 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3635 7 unneback 
 
3636 
   parameter init = 0;
3637 
   parameter memory_file = "vl_ram.vmem";
3638 
   generate if (init) begin : init_mem
3639 
   initial
3640 
     begin
3641 
        $readmemh(memory_file, ram);
3642 
     end
3643 
   end
3644 
   endgenerate
3645 
 
3646 6 unneback 
   always @ (posedge clk_a)
3647 
     begin
3648 
        q_a <= ram[adr_a];
3649 
        if (we_a)
3650 
             ram[adr_a] <= d_a;
3651 
     end
3652 
   always @ (posedge clk_b)
3653 
          q_b <= ram[adr_b];
3654 
endmodule
3655 40 unneback 
`endif
3656 6 unneback 
 
3657 40 unneback 
`ifdef DPRAM_2R2W
3658 
`define MODULE dpram_2r2w
3659 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3660 
`undef MODULE
3661 
 
3662 6 unneback 
   parameter data_width = 32;
3663 
   parameter addr_width = 8;
3664 
   input [(data_width-1):0]      d_a;
3665 
   input [(addr_width-1):0]       adr_a;
3666 
   input [(addr_width-1):0]       adr_b;
3667 
   input                         we_a;
3668 
   output [(data_width-1):0]      q_b;
3669 
   input [(data_width-1):0]       d_b;
3670 
   output reg [(data_width-1):0] q_a;
3671 
   input                         we_b;
3672 
   input                         clk_a, clk_b;
3673 
   reg [(data_width-1):0]         q_b;
3674 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3675 7 unneback 
 
3676 
   parameter init = 0;
3677 
   parameter memory_file = "vl_ram.vmem";
3678 
   generate if (init) begin : init_mem
3679 
   initial
3680 
     begin
3681 
        $readmemh(memory_file, ram);
3682 
     end
3683 
   end
3684 
   endgenerate
3685 
 
3686 6 unneback 
   always @ (posedge clk_a)
3687 
     begin
3688 
        q_a <= ram[adr_a];
3689 
        if (we_a)
3690 
             ram[adr_a] <= d_a;
3691 
     end
3692 
   always @ (posedge clk_b)
3693 
     begin
3694 
        q_b <= ram[adr_b];
3695 
        if (we_b)
3696 
          ram[adr_b] <= d_b;
3697 
     end
3698 
endmodule
3699 40 unneback 
`endif
3700 6 unneback 
 
3701 
// Content addresable memory, CAM
3702 
 
3703 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3704 6 unneback 
// FIFO
3705 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
3706 
module `BASE`MODULE (
3707 
`undef MODULE
3708 25 unneback 
    d, wr, fifo_full,
3709 
    q, rd, fifo_empty,
3710 
    fill_level,
3711 
    clk, rst
3712 
    );
3713 
 
3714 
parameter data_width = 18;
3715 
parameter addr_width = 4;
3716 6 unneback 
 
3717 25 unneback 
// write side
3718 
input  [data_width-1:0] d;
3719 
input                   wr;
3720 
output                  fifo_full;
3721 
// read side
3722 
output [data_width-1:0] q;
3723 
input                   rd;
3724 
output                  fifo_empty;
3725 
// common
3726 
output [addr_width:0]   fill_level;
3727 
input rst, clk;
3728 
 
3729 
wire [addr_width:1] wadr, radr;
3730 
 
3731 40 unneback 
`define MODULE cnt_bin_ce
3732 
`BASE`MODULE
3733 25 unneback 
    # ( .length(addr_width))
3734 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3735 40 unneback 
`BASE`MODULE
3736 25 unneback 
    # (.length(addr_width))
3737 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3738 40 unneback 
`undef MODULE
3739 25 unneback 
 
3740 40 unneback 
`define MODULE dpram_1r1w
3741 
`BASE`MODULE
3742 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3743 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3744 40 unneback 
`undef MODULE
3745 25 unneback 
 
3746 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
3747 
`BASE`MODULE
3748 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3749 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3750 40 unneback 
`undef MODULE
3751 25 unneback 
endmodule
3752 40 unneback 
`endif
3753 25 unneback 
 
3754 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3755 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3756 
// RAM is supposed to be larger than the two FIFOs
3757 
// LFSR counters used adr pointers
3758 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
3759 
module `BASE`MODULE (
3760 
`undef MODULE
3761 27 unneback 
    // a side
3762 
    a_d, a_wr, a_fifo_full,
3763 
    a_q, a_rd, a_fifo_empty,
3764 
    a_fill_level,
3765 
    // b side
3766 
    b_d, b_wr, b_fifo_full,
3767 
    b_q, b_rd, b_fifo_empty,
3768 
    b_fill_level,
3769 
    // common
3770 
    clk, rst
3771 
    );
3772 
parameter data_width = 8;
3773 
parameter addr_width = 5;
3774 
parameter fifo_full_level = (1<<addr_width)-1;
3775 
 
3776 
// a side
3777 
input  [data_width-1:0] a_d;
3778 
input                   a_wr;
3779 
output                  a_fifo_full;
3780 
output [data_width-1:0] a_q;
3781 
input                   a_rd;
3782 
output                  a_fifo_empty;
3783 
output [addr_width-1:0] a_fill_level;
3784 
 
3785 
// b side
3786 
input  [data_width-1:0] b_d;
3787 
input                   b_wr;
3788 
output                  b_fifo_full;
3789 
output [data_width-1:0] b_q;
3790 
input                   b_rd;
3791 
output                  b_fifo_empty;
3792 
output [addr_width-1:0] b_fill_level;
3793 
 
3794 
input                   clk;
3795 
input                   rst;
3796 
 
3797 
// adr_gen
3798 
wire [addr_width:1] a_wadr, a_radr;
3799 
wire [addr_width:1] b_wadr, b_radr;
3800 
// dpram
3801 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3802 
 
3803 40 unneback 
`define MODULE cnt_lfsr_ce
3804 
`BASE`MODULE
3805 27 unneback 
    # ( .length(addr_width))
3806 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3807 
 
3808 40 unneback 
`BASE`MODULE
3809 27 unneback 
    # (.length(addr_width))
3810 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3811 
 
3812 40 unneback 
`BASE`MODULE
3813 27 unneback 
    # ( .length(addr_width))
3814 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3815 
 
3816 40 unneback 
`BASE`MODULE
3817 27 unneback 
    # (.length(addr_width))
3818 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3819 40 unneback 
`undef MODULE
3820 27 unneback 
 
3821 
// mux read or write adr to DPRAM
3822 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3823 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3824 
 
3825 40 unneback 
`define MODULE dpram_2r2w
3826 
`BASE`MODULE
3827 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
3828 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3829 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3830 40 unneback 
`undef MODULE
3831 
 
3832 
`define MODULE cnt_bin_ce_rew_zq_l1
3833 
`BASE`MODULE
3834 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3835 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3836 
 
3837 40 unneback 
`BASE`MODULE
3838 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3839 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3840 40 unneback 
`undef MODULE
3841 27 unneback 
 
3842 
endmodule
3843 40 unneback 
`endif
3844 27 unneback 
 
3845 40 unneback 
`ifdef FIFO_CMP_ASYNC
3846 
`define MODULE fifo_cmp_async
3847 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3848 
`undef MODULE
3849 6 unneback 
 
3850 11 unneback 
   parameter addr_width = 4;
3851 
   parameter N = addr_width-1;
3852 6 unneback 
 
3853 
   parameter Q1 = 2'b00;
3854 
   parameter Q2 = 2'b01;
3855 
   parameter Q3 = 2'b11;
3856 
   parameter Q4 = 2'b10;
3857 
 
3858 
   parameter going_empty = 1'b0;
3859 
   parameter going_full  = 1'b1;
3860 
 
3861 
   input [N:0]  wptr, rptr;
3862 14 unneback 
   output       fifo_empty;
3863 6 unneback 
   output       fifo_full;
3864 
   input        wclk, rclk, rst;
3865 
 
3866 
`ifndef GENERATE_DIRECTION_AS_LATCH
3867 
   wire direction;
3868 
`endif
3869 
`ifdef GENERATE_DIRECTION_AS_LATCH
3870 
   reg direction;
3871 
`endif
3872 
   reg  direction_set, direction_clr;
3873 
 
3874 
   wire async_empty, async_full;
3875 
   wire fifo_full2;
3876 14 unneback 
   wire fifo_empty2;
3877 6 unneback 
 
3878 
   // direction_set
3879 
   always @ (wptr[N:N-1] or rptr[N:N-1])
3880 
     case ({wptr[N:N-1],rptr[N:N-1]})
3881 
       {Q1,Q2} : direction_set <= 1'b1;
3882 
       {Q2,Q3} : direction_set <= 1'b1;
3883 
       {Q3,Q4} : direction_set <= 1'b1;
3884 
       {Q4,Q1} : direction_set <= 1'b1;
3885 
       default : direction_set <= 1'b0;
3886 
     endcase
3887 
 
3888 
   // direction_clear
3889 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3890 
     if (rst)
3891 
       direction_clr <= 1'b1;
3892 
     else
3893 
       case ({wptr[N:N-1],rptr[N:N-1]})
3894 
         {Q2,Q1} : direction_clr <= 1'b1;
3895 
         {Q3,Q2} : direction_clr <= 1'b1;
3896 
         {Q4,Q3} : direction_clr <= 1'b1;
3897 
         {Q1,Q4} : direction_clr <= 1'b1;
3898 
         default : direction_clr <= 1'b0;
3899 
       endcase
3900 
 
3901 40 unneback 
`define MODULE dff_sr
3902 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
3903 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3904 6 unneback 
`endif
3905 
 
3906 
`ifdef GENERATE_DIRECTION_AS_LATCH
3907 
   always @ (posedge direction_set or posedge direction_clr)
3908 
     if (direction_clr)
3909 
       direction <= going_empty;
3910 
     else
3911 
       direction <= going_full;
3912 
`endif
3913 
 
3914 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3915 
   assign async_full  = (wptr == rptr) && (direction==going_full);
3916 
 
3917 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3918 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3919 
`undef MODULE
3920 6 unneback 
 
3921 
/*
3922 
   always @ (posedge wclk or posedge rst or posedge async_full)
3923 
     if (rst)
3924 
       {fifo_full, fifo_full2} <= 2'b00;
3925 
     else if (async_full)
3926 
       {fifo_full, fifo_full2} <= 2'b11;
3927 
     else
3928 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3929 
*/
3930 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
3931 6 unneback 
     if (async_empty)
3932 
       {fifo_empty, fifo_empty2} <= 2'b11;
3933 
     else
3934 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3935 40 unneback 
`define MODULE dff
3936 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3937 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3938 
`undef MODULE
3939 27 unneback 
endmodule // async_compb
3940 40 unneback 
`endif
3941 6 unneback 
 
3942 40 unneback 
`ifdef FIFO_1R1W_ASYNC
3943 
`define MODULE fifo_1r1w_async
3944 
module `BASE`MODULE (
3945 
`undef MODULE
3946 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
3947 
    q, rd, fifo_empty, rd_clk, rd_rst
3948 
    );
3949 
 
3950 
parameter data_width = 18;
3951 
parameter addr_width = 4;
3952 
 
3953 
// write side
3954 
input  [data_width-1:0] d;
3955 
input                   wr;
3956 
output                  fifo_full;
3957 
input                   wr_clk;
3958 
input                   wr_rst;
3959 
// read side
3960 
output [data_width-1:0] q;
3961 
input                   rd;
3962 
output                  fifo_empty;
3963 
input                   rd_clk;
3964 
input                   rd_rst;
3965 
 
3966 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3967 23 unneback 
 
3968 40 unneback 
`define MODULE cnt_gray_ce_bin
3969 
`BASE`MODULE
3970 6 unneback 
    # ( .length(addr_width))
3971 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3972 
 
3973 40 unneback 
`BASE`MODULE
3974 6 unneback 
    # (.length(addr_width))
3975 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3976 40 unneback 
`undef MODULE
3977 6 unneback 
 
3978 40 unneback 
`define MODULE dpram_1r1w
3979 
`BASE`MODULE
3980 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3981 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3982 40 unneback 
`undef MODULE
3983 6 unneback 
 
3984 40 unneback 
`define MODULE fifo_cmp_async
3985 
`BASE`MODULE
3986 6 unneback 
    # (.addr_width(addr_width))
3987 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3988 40 unneback 
`undef MODULE
3989 6 unneback 
 
3990 
endmodule
3991 40 unneback 
`endif
3992 6 unneback 
 
3993 40 unneback 
`ifdef FIFO_2R2W_ASYNC
3994 
`define MODULE fifo_2r2w_async
3995 
module `BASE`MODULE (
3996 
`undef MODULE
3997 6 unneback 
    // a side
3998 
    a_d, a_wr, a_fifo_full,
3999 
    a_q, a_rd, a_fifo_empty,
4000 
    a_clk, a_rst,
4001 
    // b side
4002 
    b_d, b_wr, b_fifo_full,
4003 
    b_q, b_rd, b_fifo_empty,
4004 
    b_clk, b_rst
4005 
    );
4006 
 
4007 
parameter data_width = 18;
4008 
parameter addr_width = 4;
4009 
 
4010 
// a side
4011 
input  [data_width-1:0] a_d;
4012 
input                   a_wr;
4013 
output                  a_fifo_full;
4014 
output [data_width-1:0] a_q;
4015 
input                   a_rd;
4016 
output                  a_fifo_empty;
4017 
input                   a_clk;
4018 
input                   a_rst;
4019 
 
4020 
// b side
4021 
input  [data_width-1:0] b_d;
4022 
input                   b_wr;
4023 
output                  b_fifo_full;
4024 
output [data_width-1:0] b_q;
4025 
input                   b_rd;
4026 
output                  b_fifo_empty;
4027 
input                   b_clk;
4028 
input                   b_rst;
4029 
 
4030 40 unneback 
`define MODULE fifo_1r1w_async
4031 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4032 6 unneback 
vl_fifo_1r1w_async_a (
4033 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4034 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4035 
    );
4036 
 
4037 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4038 6 unneback 
vl_fifo_1r1w_async_b (
4039 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4040 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4041 
    );
4042 40 unneback 
`undef MODULE
4043 
 
4044 6 unneback 
endmodule
4045 40 unneback 
`endif
4046 6 unneback 
 
4047 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4048 
`define MODULE fifo_2r2w_async_simplex
4049 
module `BASE`MODULE (
4050 
`undef MODULE
4051 6 unneback 
    // a side
4052 
    a_d, a_wr, a_fifo_full,
4053 
    a_q, a_rd, a_fifo_empty,
4054 
    a_clk, a_rst,
4055 
    // b side
4056 
    b_d, b_wr, b_fifo_full,
4057 
    b_q, b_rd, b_fifo_empty,
4058 
    b_clk, b_rst
4059 
    );
4060 
 
4061 
parameter data_width = 18;
4062 
parameter addr_width = 4;
4063 
 
4064 
// a side
4065 
input  [data_width-1:0] a_d;
4066 
input                   a_wr;
4067 
output                  a_fifo_full;
4068 
output [data_width-1:0] a_q;
4069 
input                   a_rd;
4070 
output                  a_fifo_empty;
4071 
input                   a_clk;
4072 
input                   a_rst;
4073 
 
4074 
// b side
4075 
input  [data_width-1:0] b_d;
4076 
input                   b_wr;
4077 
output                  b_fifo_full;
4078 
output [data_width-1:0] b_q;
4079 
input                   b_rd;
4080 
output                  b_fifo_empty;
4081 
input                   b_clk;
4082 
input                   b_rst;
4083 
 
4084 
// adr_gen
4085 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4086 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4087 
// dpram
4088 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4089 
 
4090 40 unneback 
`define MODULE cnt_gray_ce_bin
4091 
`BASE`MODULE
4092 6 unneback 
    # ( .length(addr_width))
4093 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4094 
 
4095 40 unneback 
`BASE`MODULE
4096 6 unneback 
    # (.length(addr_width))
4097 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4098 
 
4099 40 unneback 
`BASE`MODULE
4100 6 unneback 
    # ( .length(addr_width))
4101 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4102 
 
4103 40 unneback 
`BASE`MODULE
4104 6 unneback 
    # (.length(addr_width))
4105 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4106 40 unneback 
`undef MODULE
4107 6 unneback 
 
4108 
// mux read or write adr to DPRAM
4109 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4110 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4111 
 
4112 40 unneback 
`define MODULE dpram_2r2w
4113 
`BASE`MODULE
4114 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4115 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4116 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4117 40 unneback 
`undef MODULE
4118 6 unneback 
 
4119 40 unneback 
`define MODULE fifo_cmp_async
4120 
`BASE`MODULE
4121 6 unneback 
    # (.addr_width(addr_width))
4122 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4123 
 
4124 40 unneback 
`BASE`MODULE
4125 6 unneback 
    # (.addr_width(addr_width))
4126 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4127 40 unneback 
`undef MODULE
4128 6 unneback 
 
4129 
endmodule
4130 40 unneback 
`endif
4131 12 unneback 
//////////////////////////////////////////////////////////////////////
4132 
////                                                              ////
4133 
////  Versatile library, wishbone stuff                           ////
4134 
////                                                              ////
4135 
////  Description                                                 ////
4136 
////  Wishbone compliant modules                                  ////
4137 
////                                                              ////
4138 
////                                                              ////
4139 
////  To Do:                                                      ////
4140 
////   -                                                          ////
4141 
////                                                              ////
4142 
////  Author(s):                                                  ////
4143 
////      - Michael Unneback, unneback@opencores.org              ////
4144 
////        ORSoC AB                                              ////
4145 
////                                                              ////
4146 
//////////////////////////////////////////////////////////////////////
4147 
////                                                              ////
4148 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4149 
////                                                              ////
4150 
//// This source file may be used and distributed without         ////
4151 
//// restriction provided that this copyright statement is not    ////
4152 
//// removed from the file and that any derivative work contains  ////
4153 
//// the original copyright notice and the associated disclaimer. ////
4154 
////                                                              ////
4155 
//// This source file is free software; you can redistribute it   ////
4156 
//// and/or modify it under the terms of the GNU Lesser General   ////
4157 
//// Public License as published by the Free Software Foundation; ////
4158 
//// either version 2.1 of the License, or (at your option) any   ////
4159 
//// later version.                                               ////
4160 
////                                                              ////
4161 
//// This source is distributed in the hope that it will be       ////
4162 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4163 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4164 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4165 
//// details.                                                     ////
4166 
////                                                              ////
4167 
//// You should have received a copy of the GNU Lesser General    ////
4168 
//// Public License along with this source; if not, download it   ////
4169 
//// from http://www.opencores.org/lgpl.shtml                     ////
4170 
////                                                              ////
4171 
//////////////////////////////////////////////////////////////////////
4172 
 
4173 40 unneback 
`ifdef WB3WB3_BRIDGE
4174 12 unneback 
// async wb3 - wb3 bridge
4175 
`timescale 1ns/1ns
4176 40 unneback 
`define MODULE wb3wb3_bridge
4177 
module `BASE`MODULE (
4178 
`undef MODULE
4179 12 unneback 
        // wishbone slave side
4180 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4181 
        // wishbone master side
4182 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4183 
 
4184 
input [31:0] wbs_dat_i;
4185 
input [31:2] wbs_adr_i;
4186 
input [3:0]  wbs_sel_i;
4187 
input [1:0]  wbs_bte_i;
4188 
input [2:0]  wbs_cti_i;
4189 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4190 
output [31:0] wbs_dat_o;
4191 14 unneback 
output wbs_ack_o;
4192 12 unneback 
input wbs_clk, wbs_rst;
4193 
 
4194 
output [31:0] wbm_dat_o;
4195 
output reg [31:2] wbm_adr_o;
4196 
output [3:0]  wbm_sel_o;
4197 
output reg [1:0]  wbm_bte_o;
4198 
output reg [2:0]  wbm_cti_o;
4199 14 unneback 
output reg wbm_we_o;
4200 
output wbm_cyc_o;
4201 12 unneback 
output wbm_stb_o;
4202 
input [31:0]  wbm_dat_i;
4203 
input wbm_ack_i;
4204 
input wbm_clk, wbm_rst;
4205 
 
4206 
parameter addr_width = 4;
4207 
 
4208 
// bte
4209 
parameter linear       = 2'b00;
4210 
parameter wrap4        = 2'b01;
4211 
parameter wrap8        = 2'b10;
4212 
parameter wrap16       = 2'b11;
4213 
// cti
4214 
parameter classic      = 3'b000;
4215 
parameter incburst     = 3'b010;
4216 
parameter endofburst   = 3'b111;
4217 
 
4218 
parameter wbs_adr  = 1'b0;
4219 
parameter wbs_data = 1'b1;
4220 
 
4221 33 unneback 
parameter wbm_adr0      = 2'b00;
4222 
parameter wbm_adr1      = 2'b01;
4223 
parameter wbm_data      = 2'b10;
4224 
parameter wbm_data_wait = 2'b11;
4225 12 unneback 
 
4226 
reg [1:0] wbs_bte_reg;
4227 
reg wbs;
4228 
wire wbs_eoc_alert, wbm_eoc_alert;
4229 
reg wbs_eoc, wbm_eoc;
4230 
reg [1:0] wbm;
4231 
 
4232 14 unneback 
wire [1:16] wbs_count, wbm_count;
4233 12 unneback 
 
4234 
wire [35:0] a_d, a_q, b_d, b_q;
4235 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4236 
reg a_rd_reg;
4237 
wire b_rd_adr, b_rd_data;
4238 14 unneback 
wire b_rd_data_reg;
4239 
wire [35:0] temp;
4240 12 unneback 
 
4241 
`define WE 5
4242 
`define BTE 4:3
4243 
`define CTI 2:0
4244 
 
4245 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4246 
always @ (posedge wbs_clk or posedge wbs_rst)
4247 
if (wbs_rst)
4248 
        wbs_eoc <= 1'b0;
4249 
else
4250 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4251 
                wbs_eoc <= wbs_bte_i==linear;
4252 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4253 
                wbs_eoc <= 1'b1;
4254 
 
4255 40 unneback 
`define MODULE cnt_shreg_ce_clear
4256 
`BASE`MODULE # ( .length(16))
4257 
`undef MODULE
4258 12 unneback 
    cnt0 (
4259 
        .cke(wbs_ack_o),
4260 
        .clear(wbs_eoc),
4261 
        .q(wbs_count),
4262 
        .rst(wbs_rst),
4263 
        .clk(wbs_clk));
4264 
 
4265 
always @ (posedge wbs_clk or posedge wbs_rst)
4266 
if (wbs_rst)
4267 
        wbs <= wbs_adr;
4268 
else
4269 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4270 
                wbs <= wbs_data;
4271 
        else if (wbs_eoc & wbs_ack_o)
4272 
                wbs <= wbs_adr;
4273 
 
4274 
// wbs FIFO
4275 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4276 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4277 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4278 
              1'b0;
4279 
assign a_rd = !a_fifo_empty;
4280 
always @ (posedge wbs_clk or posedge wbs_rst)
4281 
if (wbs_rst)
4282 
        a_rd_reg <= 1'b0;
4283 
else
4284 
        a_rd_reg <= a_rd;
4285 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4286 
 
4287 
assign wbs_dat_o = a_q[35:4];
4288 
 
4289 
always @ (posedge wbs_clk or posedge wbs_rst)
4290 
if (wbs_rst)
4291 13 unneback 
        wbs_bte_reg <= 2'b00;
4292 12 unneback 
else
4293 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4294 12 unneback 
 
4295 
// wbm FIFO
4296 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4297 
always @ (posedge wbm_clk or posedge wbm_rst)
4298 
if (wbm_rst)
4299 
        wbm_eoc <= 1'b0;
4300 
else
4301 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4302 
                wbm_eoc <= b_q[`BTE] == linear;
4303 
        else if (wbm_eoc_alert & wbm_ack_i)
4304 
                wbm_eoc <= 1'b1;
4305 
 
4306 
always @ (posedge wbm_clk or posedge wbm_rst)
4307 
if (wbm_rst)
4308 
        wbm <= wbm_adr0;
4309 
else
4310 33 unneback 
/*
4311 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4312 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4313 
        (wbm==wbm_adr1 & !wbm_we_o) |
4314 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4315 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4316 33 unneback 
*/
4317 
    case (wbm)
4318 
    wbm_adr0:
4319 
        if (!b_fifo_empty)
4320 
            wbm <= wbm_adr1;
4321 
    wbm_adr1:
4322 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4323 
            wbm <= wbm_data;
4324 
    wbm_data:
4325 
        if (wbm_ack_i & wbm_eoc)
4326 
            wbm <= wbm_adr0;
4327 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4328 
            wbm <= wbm_data_wait;
4329 
    wbm_data_wait:
4330 
        if (!b_fifo_empty)
4331 
            wbm <= wbm_data;
4332 
    endcase
4333 12 unneback 
 
4334 
assign b_d = {wbm_dat_i,4'b1111};
4335 
assign b_wr = !wbm_we_o & wbm_ack_i;
4336 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4337 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4338 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4339 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4340 12 unneback 
                   1'b0;
4341 
assign b_rd = b_rd_adr | b_rd_data;
4342 
 
4343 40 unneback 
`define MODULE dff
4344 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4345 
`undef MODULE
4346 
`define MODULE dff_ce
4347 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4348 
`undef MODULE
4349 12 unneback 
 
4350 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4351 
 
4352 40 unneback 
`define MODULE cnt_shreg_ce_clear
4353 42 unneback 
`BASE`MODULE # ( .length(16))
4354 40 unneback 
`undef MODULE
4355 12 unneback 
    cnt1 (
4356 
        .cke(wbm_ack_i),
4357 
        .clear(wbm_eoc),
4358 
        .q(wbm_count),
4359 
        .rst(wbm_rst),
4360 
        .clk(wbm_clk));
4361 
 
4362 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4363 
assign wbm_stb_o = (wbm==wbm_data);
4364 12 unneback 
 
4365 
always @ (posedge wbm_clk or posedge wbm_rst)
4366 
if (wbm_rst)
4367 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4368 
else begin
4369 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4370 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4371 
        else if (wbm_eoc_alert & wbm_ack_i)
4372 
                wbm_cti_o <= endofburst;
4373 
end
4374 
 
4375 
//async_fifo_dw_simplex_top
4376 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4377 
`BASE`MODULE
4378 
`undef MODULE
4379 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4380 
fifo (
4381 
    // a side
4382 
    .a_d(a_d),
4383 
    .a_wr(a_wr),
4384 
    .a_fifo_full(a_fifo_full),
4385 
    .a_q(a_q),
4386 
    .a_rd(a_rd),
4387 
    .a_fifo_empty(a_fifo_empty),
4388 
    .a_clk(wbs_clk),
4389 
    .a_rst(wbs_rst),
4390 
    // b side
4391 
    .b_d(b_d),
4392 
    .b_wr(b_wr),
4393 
    .b_fifo_full(b_fifo_full),
4394 
    .b_q(b_q),
4395 
    .b_rd(b_rd),
4396 
    .b_fifo_empty(b_fifo_empty),
4397 
    .b_clk(wbm_clk),
4398 
    .b_rst(wbm_rst)
4399 
    );
4400 
 
4401 
endmodule
4402 40 unneback 
`undef WE
4403 
`undef BTE
4404 
`undef CTI
4405 
`endif
4406 17 unneback 
 
4407 40 unneback 
`ifdef WB3_ARBITER_TYPE1
4408 
`define MODULE wb3_arbiter_type1
4409 42 unneback 
module `BASE`MODULE (
4410 40 unneback 
`undef MODULE
4411 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4412 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4413 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4414 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4415 
    wb_clk, wb_rst
4416 
);
4417 
 
4418 
parameter nr_of_ports = 3;
4419 
parameter adr_size = 26;
4420 
parameter adr_lo   = 2;
4421 
parameter dat_size = 32;
4422 
parameter sel_size = dat_size/8;
4423 
 
4424 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4425 
localparam dw = dat_size * nr_of_ports;
4426 
localparam sw = sel_size * nr_of_ports;
4427 
localparam cw = 3 * nr_of_ports;
4428 
localparam bw = 2 * nr_of_ports;
4429 
 
4430 
input  [dw-1:0] wbm_dat_o;
4431 
input  [aw-1:0] wbm_adr_o;
4432 
input  [sw-1:0] wbm_sel_o;
4433 
input  [cw-1:0] wbm_cti_o;
4434 
input  [bw-1:0] wbm_bte_o;
4435 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4436 
output [dw-1:0] wbm_dat_i;
4437 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4438 
 
4439 
output [dat_size-1:0] wbs_dat_i;
4440 
output [adr_size-1:adr_lo] wbs_adr_i;
4441 
output [sel_size-1:0] wbs_sel_i;
4442 
output [2:0] wbs_cti_i;
4443 
output [1:0] wbs_bte_i;
4444 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4445 
input  [dat_size-1:0] wbs_dat_o;
4446 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4447 
 
4448 
input wb_clk, wb_rst;
4449 
 
4450 44 unneback 
reg  [nr_of_ports-1:0] select;
4451 39 unneback 
wire [nr_of_ports-1:0] state;
4452 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4453 
wire [nr_of_ports-1:0] sel;
4454 
wire idle;
4455 
 
4456 
genvar i;
4457 
 
4458 
assign idle = !(|state);
4459 
 
4460 
generate
4461 
if (nr_of_ports == 2) begin
4462 
 
4463 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4464 
 
4465 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4466 
 
4467 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4468 
 
4469 
    always @ (idle or wbm_cyc_o)
4470 
    if (idle)
4471 
        casex (wbm_cyc_o)
4472 
        2'b1x : select = 2'b10;
4473 
        2'b01 : select = 2'b01;
4474 
        default : select = {nr_of_ports{1'b0}};
4475 
        endcase
4476 
    else
4477 
        select = {nr_of_ports{1'b0}};
4478 
 
4479 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4480 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4481 
 
4482 
end
4483 
endgenerate
4484 
 
4485 
generate
4486 
if (nr_of_ports == 3) begin
4487 
 
4488 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4489 
 
4490 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4491 
 
4492 44 unneback 
    always @ (idle or wbm_cyc_o)
4493 
    if (idle)
4494 
        casex (wbm_cyc_o)
4495 
        3'b1xx : select = 3'b100;
4496 
        3'b01x : select = 3'b010;
4497 
        3'b001 : select = 3'b001;
4498 
        default : select = {nr_of_ports{1'b0}};
4499 
        endcase
4500 
    else
4501 
        select = {nr_of_ports{1'b0}};
4502 
 
4503 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4504 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4505 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4506 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4507 
 
4508 
end
4509 
endgenerate
4510 
 
4511 
generate
4512 44 unneback 
if (nr_of_ports == 4) begin
4513 
 
4514 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4515 
 
4516 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4517 
 
4518 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4519 
 
4520 
    always @ (idle or wbm_cyc_o)
4521 
    if (idle)
4522 
        casex (wbm_cyc_o)
4523 
        4'b1xxx : select = 4'b1000;
4524 
        4'b01xx : select = 4'b0100;
4525 
        4'b001x : select = 4'b0010;
4526 
        4'b0001 : select = 4'b0001;
4527 
        default : select = {nr_of_ports{1'b0}};
4528 
        endcase
4529 
    else
4530 
        select = {nr_of_ports{1'b0}};
4531 
 
4532 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4533 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4534 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4535 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4536 
 
4537 
end
4538 
endgenerate
4539 
 
4540 
generate
4541 
if (nr_of_ports == 5) begin
4542 
 
4543 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4544 
 
4545 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4546 
 
4547 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4548 
 
4549 
    always @ (idle or wbm_cyc_o)
4550 
    if (idle)
4551 
        casex (wbm_cyc_o)
4552 
        5'b1xxxx : select = 5'b10000;
4553 
        5'b01xxx : select = 5'b01000;
4554 
        5'b001xx : select = 5'b00100;
4555 
        5'b0001x : select = 5'b00010;
4556 
        5'b00001 : select = 5'b00001;
4557 
        default : select = {nr_of_ports{1'b0}};
4558 
        endcase
4559 
    else
4560 
        select = {nr_of_ports{1'b0}};
4561 
 
4562 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4563 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4564 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4565 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4566 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4567 
 
4568 
end
4569 
endgenerate
4570 
 
4571 
generate
4572 39 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin
4573 42 unneback 
`define MODULE spr
4574 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4575 
`undef MODULE
4576 39 unneback 
end
4577 
endgenerate
4578 
 
4579 
    assign sel = select | state;
4580 
 
4581 40 unneback 
`define MODULE mux_andor
4582 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4583 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4584 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4585 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4586 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4587 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4588 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4589 
`undef MODULE
4590 39 unneback 
    assign wbs_cyc_i = |sel;
4591 
 
4592 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4593 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4594 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4595 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4596 
 
4597 
endmodule
4598 40 unneback 
`endif
4599 39 unneback 
 
4600 40 unneback 
`ifdef WB_BOOT_ROM
4601 17 unneback 
// WB ROM
4602 40 unneback 
`define MODULE wb_boot_rom
4603 
module `BASE`MODULE (
4604 
`undef MODULE
4605 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4606 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4607 17 unneback 
 
4608 18 unneback 
    parameter adr_hi = 31;
4609 
    parameter adr_lo = 28;
4610 
    parameter adr_sel = 4'hf;
4611 
    parameter addr_width = 5;
4612 33 unneback 
/*
4613 17 unneback 
`ifndef BOOT_ROM
4614 
`define BOOT_ROM "boot_rom.v"
4615 
`endif
4616 33 unneback 
*/
4617 18 unneback 
    input [adr_hi:2]    wb_adr_i;
4618 
    input               wb_stb_i;
4619 
    input               wb_cyc_i;
4620 
    output [31:0]        wb_dat_o;
4621 
    output              wb_ack_o;
4622 
    output              hit_o;
4623 
    input               wb_clk;
4624 
    input               wb_rst;
4625 
 
4626 
    wire hit;
4627 
    reg [31:0] wb_dat;
4628 
    reg wb_ack;
4629 
 
4630 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4631 17 unneback 
 
4632 
always @ (posedge wb_clk or posedge wb_rst)
4633 
    if (wb_rst)
4634 18 unneback 
        wb_dat <= 32'h15000000;
4635 17 unneback 
    else
4636 18 unneback 
         case (wb_adr_i[addr_width-1:2])
4637 33 unneback 
`ifdef BOOT_ROM
4638 17 unneback 
`include `BOOT_ROM
4639 33 unneback 
`endif
4640 17 unneback 
           /*
4641 
            // Zero r0 and jump to 0x00000100
4642 18 unneback 
 
4643 
            1 : wb_dat <= 32'hA8200000;
4644 
            2 : wb_dat <= 32'hA8C00100;
4645 
            3 : wb_dat <= 32'h44003000;
4646 
            4 : wb_dat <= 32'h15000000;
4647 17 unneback 
            */
4648 
           default:
4649 18 unneback 
             wb_dat <= 32'h00000000;
4650 17 unneback 
 
4651 
         endcase // case (wb_adr_i)
4652 
 
4653 
 
4654 
always @ (posedge wb_clk or posedge wb_rst)
4655 
    if (wb_rst)
4656 18 unneback 
        wb_ack <= 1'b0;
4657 17 unneback 
    else
4658 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4659 17 unneback 
 
4660 18 unneback 
assign hit_o = hit;
4661 
assign wb_dat_o = wb_dat & {32{wb_ack}};
4662 
assign wb_ack_o = wb_ack;
4663 
 
4664 17 unneback 
endmodule
4665 40 unneback 
`endif
4666 32 unneback 
 
4667 40 unneback 
`ifdef WB_DPRAM
4668 
`define MODULE wb_dpram
4669 
module `BASE`MODULE (
4670 
`undef MODULE
4671 32 unneback 
        // wishbone slave side a
4672 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4673 
        wbsa_clk, wbsa_rst,
4674 
        // wishbone slave side a
4675 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4676 
        wbsb_clk, wbsb_rst);
4677 
 
4678 
parameter data_width = 32;
4679 
parameter addr_width = 8;
4680 
 
4681 
parameter dat_o_mask_a = 1;
4682 
parameter dat_o_mask_b = 1;
4683 
 
4684 
input [31:0] wbsa_dat_i;
4685 
input [addr_width-1:2] wbsa_adr_i;
4686 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4687 
output [31:0] wbsa_dat_o;
4688 
output wbsa_ack_o;
4689 
input wbsa_clk, wbsa_rst;
4690 
 
4691 
input [31:0] wbsb_dat_i;
4692 
input [addr_width-1:2] wbsb_adr_i;
4693 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4694 
output [31:0] wbsb_dat_o;
4695 
output wbsb_ack_o;
4696 
input wbsb_clk, wbsb_rst;
4697 
 
4698 
wire wbsa_dat_tmp, wbsb_dat_tmp;
4699 
 
4700 40 unneback 
`define MODULE dpram_2r2w
4701 
`BASE`MODULE # (
4702 
`undef MODULE
4703 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
4704 32 unneback 
dpram0(
4705 
    .d_a(wbsa_dat_i),
4706 
    .q_a(wbsa_dat_tmp),
4707 
    .adr_a(wbsa_adr_i),
4708 
    .we_a(wbsa_we_i),
4709 
    .clk_a(wbsa_clk),
4710 
    .d_b(wbsb_dat_i),
4711 
    .q_b(wbsb_dat_tmp),
4712 
    .adr_b(wbsb_adr_i),
4713 
    .we_b(wbsb_we_i),
4714 
    .clk_b(wbsb_clk) );
4715 
 
4716 33 unneback 
generate if (dat_o_mask_a==1)
4717 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
4718 
endgenerate
4719 33 unneback 
generate if (dat_o_mask_a==0)
4720 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
4721 
endgenerate
4722 
 
4723 33 unneback 
generate if (dat_o_mask_b==1)
4724 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
4725 
endgenerate
4726 33 unneback 
generate if (dat_o_mask_b==0)
4727 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
4728 
endgenerate
4729 
 
4730 40 unneback 
`define MODULE spr
4731 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4732 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4733 
`undef MODULE
4734 32 unneback 
 
4735 
endmodule
4736 40 unneback 
`endif
4737 18 unneback 
//////////////////////////////////////////////////////////////////////
4738 
////                                                              ////
4739 
////  Arithmetic functions                                        ////
4740 
////                                                              ////
4741 
////  Description                                                 ////
4742 
////  Arithmetic functions for ALU and DSP                        ////
4743 
////                                                              ////
4744 
////                                                              ////
4745 
////  To Do:                                                      ////
4746 
////   -                                                          ////
4747 
////                                                              ////
4748 
////  Author(s):                                                  ////
4749 
////      - Michael Unneback, unneback@opencores.org              ////
4750 
////        ORSoC AB                                              ////
4751 
////                                                              ////
4752 
//////////////////////////////////////////////////////////////////////
4753 
////                                                              ////
4754 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4755 
////                                                              ////
4756 
//// This source file may be used and distributed without         ////
4757 
//// restriction provided that this copyright statement is not    ////
4758 
//// removed from the file and that any derivative work contains  ////
4759 
//// the original copyright notice and the associated disclaimer. ////
4760 
////                                                              ////
4761 
//// This source file is free software; you can redistribute it   ////
4762 
//// and/or modify it under the terms of the GNU Lesser General   ////
4763 
//// Public License as published by the Free Software Foundation; ////
4764 
//// either version 2.1 of the License, or (at your option) any   ////
4765 
//// later version.                                               ////
4766 
////                                                              ////
4767 
//// This source is distributed in the hope that it will be       ////
4768 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4769 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4770 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4771 
//// details.                                                     ////
4772 
////                                                              ////
4773 
//// You should have received a copy of the GNU Lesser General    ////
4774 
//// Public License along with this source; if not, download it   ////
4775 
//// from http://www.opencores.org/lgpl.shtml                     ////
4776 
////                                                              ////
4777 
//////////////////////////////////////////////////////////////////////
4778 
 
4779 40 unneback 
`ifdef MULTS
4780 18 unneback 
// signed multiplication
4781 40 unneback 
`define MODULE mults
4782 
module `BASE`MODULE (a,b,p);
4783 
`undef MODULE
4784 18 unneback 
parameter operand_a_width = 18;
4785 
parameter operand_b_width = 18;
4786 
parameter result_hi = 35;
4787 
parameter result_lo = 0;
4788 
input [operand_a_width-1:0] a;
4789 
input [operand_b_width-1:0] b;
4790 
output [result_hi:result_lo] p;
4791 
wire signed [operand_a_width-1:0] ai;
4792 
wire signed [operand_b_width-1:0] bi;
4793 
wire signed [operand_a_width+operand_b_width-1:0] result;
4794 
 
4795 
    assign ai = a;
4796 
    assign bi = b;
4797 
    assign result = ai * bi;
4798 
    assign p = result[result_hi:result_lo];
4799 
 
4800 
endmodule
4801 40 unneback 
`endif
4802 
`ifdef MULTS18X18
4803 
`define MODULE mults18x18
4804 
module `BASE`MODULE (a,b,p);
4805 
`undef MODULE
4806 18 unneback 
input [17:0] a,b;
4807 
output [35:0] p;
4808 
vl_mult
4809 
    # (.operand_a_width(18), .operand_b_width(18))
4810 
    mult0 (.a(a), .b(b), .p(p));
4811 
endmodule
4812 40 unneback 
`endif
4813 18 unneback 
 
4814 40 unneback 
`ifdef MULT
4815 
`define MODULE mult
4816 18 unneback 
// unsigned multiplication
4817 40 unneback 
module `BASE`MODULE (a,b,p);
4818 
`undef MODULE
4819 18 unneback 
parameter operand_a_width = 18;
4820 
parameter operand_b_width = 18;
4821 
parameter result_hi = 35;
4822 
parameter result_lo = 0;
4823 
input [operand_a_width-1:0] a;
4824 
input [operand_b_width-1:0] b;
4825 
output [result_hi:result_hi] p;
4826 
 
4827 
wire [operand_a_width+operand_b_width-1:0] result;
4828 
 
4829 
    assign result = a * b;
4830 
    assign p = result[result_hi:result_lo];
4831 
 
4832 
endmodule
4833 40 unneback 
`endif
4834 18 unneback 
 
4835 40 unneback 
`ifdef SHIFT_UNIT_32
4836 
`define MODULE shift_unit_32
4837 18 unneback 
// shift unit
4838 
// supporting the following shift functions
4839 
//   SLL
4840 
//   SRL
4841 
//   SRA
4842 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
4843 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
4844 
`undef MODULE
4845 18 unneback 
input [31:0] din; // data in operand
4846 
input [4:0] s; // shift operand
4847 
input [1:0] opcode;
4848 
output [31:0] dout;
4849 
 
4850 
parameter opcode_sll = 2'b00;
4851 
//parameter opcode_srl = 2'b01;
4852 
parameter opcode_sra = 2'b10;
4853 
//parameter opcode_ror = 2'b11;
4854 
 
4855 
wire sll, sra;
4856 
assign sll = opcode == opcode_sll;
4857 
assign sra = opcode == opcode_sra;
4858 
 
4859 
wire [15:1] s1;
4860 
wire [3:0] sign;
4861 
wire [7:0] tmp [0:3];
4862 
 
4863 
// first stage is multiplier based
4864 
// shift operand as fractional 8.7
4865 
assign s1[15] = sll & s[2:0]==3'd7;
4866 
assign s1[14] = sll & s[2:0]==3'd6;
4867 
assign s1[13] = sll & s[2:0]==3'd5;
4868 
assign s1[12] = sll & s[2:0]==3'd4;
4869 
assign s1[11] = sll & s[2:0]==3'd3;
4870 
assign s1[10] = sll & s[2:0]==3'd2;
4871 
assign s1[ 9] = sll & s[2:0]==3'd1;
4872 
assign s1[ 8] = s[2:0]==3'd0;
4873 
assign s1[ 7] = !sll & s[2:0]==3'd1;
4874 
assign s1[ 6] = !sll & s[2:0]==3'd2;
4875 
assign s1[ 5] = !sll & s[2:0]==3'd3;
4876 
assign s1[ 4] = !sll & s[2:0]==3'd4;
4877 
assign s1[ 3] = !sll & s[2:0]==3'd5;
4878 
assign s1[ 2] = !sll & s[2:0]==3'd6;
4879 
assign s1[ 1] = !sll & s[2:0]==3'd7;
4880 
 
4881 
assign sign[3] = din[31] & sra;
4882 
assign sign[2] = sign[3] & (&din[31:24]);
4883 
assign sign[1] = sign[2] & (&din[23:16]);
4884 
assign sign[0] = sign[1] & (&din[15:8]);
4885 40 unneback 
`define MODULE mults
4886 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
4887 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
4888 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
4889 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
4890 
`undef MODULE
4891 18 unneback 
// second stage is multiplexer based
4892 
// shift on byte level
4893 
 
4894 
// mux byte 3
4895 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
4896 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
4897 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
4898 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
4899 
                     {8{sign[3]}};
4900 
 
4901 
// mux byte 2
4902 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
4903 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
4904 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
4905 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4906 
                     (s[4:3]==2'b01) ? tmp[3] :
4907 
                     {8{sign[3]}};
4908 
 
4909 
// mux byte 1
4910 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
4911 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
4912 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
4913 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4914 
                     (s[4:3]==2'b01) ? tmp[2] :
4915 
                     (s[4:3]==2'b10) ? tmp[3] :
4916 
                     {8{sign[3]}};
4917 
 
4918 
// mux byte 0
4919 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
4920 
                     (sll) ?  {8{1'b0}}:
4921 
                     (s[4:3]==2'b01) ? tmp[1] :
4922 
                     (s[4:3]==2'b10) ? tmp[2] :
4923 
                     tmp[3];
4924 
 
4925 
endmodule
4926 40 unneback 
`endif
4927 18 unneback 
 
4928 40 unneback 
`ifdef LOGIC_UNIT
4929 18 unneback 
// logic unit
4930 
// supporting the following logic functions
4931 
//    a and b
4932 
//    a or  b
4933 
//    a xor b
4934 
//    not b
4935 40 unneback 
`define MODULE logic_unit
4936 
module `BASE`MODULE( a, b, result, opcode);
4937 
`undef MODULE
4938 18 unneback 
parameter width = 32;
4939 
parameter opcode_and = 2'b00;
4940 
parameter opcode_or  = 2'b01;
4941 
parameter opcode_xor = 2'b10;
4942 
input [width-1:0] a,b;
4943 
output [width-1:0] result;
4944 
input [1:0] opcode;
4945 
 
4946 
assign result = (opcode==opcode_and) ? a & b :
4947 
                (opcode==opcode_or)  ? a | b :
4948 
                (opcode==opcode_xor) ? a ^ b :
4949 
                b;
4950 
 
4951 
endmodule
4952 
 
4953 
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
4954 
parameter width = 32;
4955 
parameter opcode_add = 1'b0;
4956 
parameter opcode_sub = 1'b1;
4957 
input [width-1:0] a,b;
4958 
input c_in, add_sub, sign;
4959 
output [width-1:0] result;
4960 
output c_out, z, ovfl;
4961 
 
4962 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
4963 
assign z = (result=={width{1'b0}});
4964 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
4965 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
4966 
endmodule
4967 40 unneback 
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.