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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 60

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 
`define FIFO_1R1W_FILL_LEVEL_SYNC
45 
`define FIFO_2R2W_SYNC_SIMPLEX
46 
`define FIFO_CMP_ASYNC
47 
`define FIFO_1R1W_ASYNC
48 
`define FIFO_2R2W_ASYNC
49 
`define FIFO_2R2W_ASYNC_SIMPLEX
50 48 unneback 
`define REG_FILE
51 40 unneback 
 
52 
`define DFF
53 
`define DFF_ARRAY
54 
`define DFF_CE
55 
`define DFF_CE_CLEAR
56 
`define DF_CE_SET
57 
`define SPR
58 
`define SRP
59 
`define DFF_SR
60 
`define LATCH
61 
`define SHREG
62 
`define SHREG_CE
63 
`define DELAY
64 
`define DELAY_EMPTYFLAG
65 
 
66 
`define WB3WB3_BRIDGE
67 
`define WB3_ARBITER_TYPE1
68 59 unneback 
`define WB_B3_RAM_BE
69 49 unneback 
`define WB_B4_RAM_BE
70 48 unneback 
`define WB_B4_ROM
71 40 unneback 
`define WB_BOOT_ROM
72 
`define WB_DPRAM
73 
 
74 44 unneback 
`define IO_DFF_OE
75 
`define O_DFF
76 
 
77 40 unneback 
`endif
78 
 
79 
`ifdef PLL
80 
`ifndef SYNC_RST
81 
`define SYNC_RST
82 
`endif
83 
`endif
84 
 
85 
`ifdef SYNC_RST
86 
`ifndef GBUF
87 
`define GBUF
88 
`endif
89 
`endif
90 
 
91 
`ifdef WB_DPRAM
92 
`ifndef DPRAM_2R2W
93 
`define DPRAM_2R2W
94 
`endif
95 
`ifndef SPR
96 
`define SPR
97 
`endif
98 
`endif
99 
 
100 
`ifdef WB3_ARBITER_TYPE1
101 42 unneback 
`ifndef SPR
102 
`define SPR
103 
`endif
104 40 unneback 
`ifndef MUX_ANDOR
105 
`define MUX_ANDOR
106 
`endif
107 
`endif
108 
 
109 
`ifdef WB3WB3_BRIDGE
110 
`ifndef CNT_SHREG_CE_CLEAR
111 
`define CNT_SHREG_CE_CLEAR
112 
`endif
113 
`ifndef DFF
114 
`define DFF
115 
`endif
116 
`ifndef DFF_CE
117 
`define DFF_CE
118 
`endif
119 
`ifndef CNT_SHREG_CE_CLEAR
120 
`define CNT_SHREG_CE_CLEAR
121 
`endif
122 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
123 
`define FIFO_2R2W_ASYNC_SIMPLEX
124 
`endif
125 
`endif
126 
 
127 
`ifdef MULTS18X18
128 
`ifndef MULTS
129 
`define MULTS
130 
`endif
131 
`endif
132 
 
133 
`ifdef SHIFT_UNIT_32
134 
`ifndef MULTS
135 
`define MULTS
136 
`endif
137 
`endif
138 
 
139 
`ifdef MUX2_ANDOR
140 
`ifndef MUX_ANDOR
141 
`define MUX_ANDOR
142 
`endif
143 
`endif
144 
 
145 
`ifdef MUX3_ANDOR
146 
`ifndef MUX_ANDOR
147 
`define MUX_ANDOR
148 
`endif
149 
`endif
150 
 
151 
`ifdef MUX4_ANDOR
152 
`ifndef MUX_ANDOR
153 
`define MUX_ANDOR
154 
`endif
155 
`endif
156 
 
157 
`ifdef MUX5_ANDOR
158 
`ifndef MUX_ANDOR
159 
`define MUX_ANDOR
160 
`endif
161 
`endif
162 
 
163 
`ifdef MUX6_ANDOR
164 
`ifndef MUX_ANDOR
165 
`define MUX_ANDOR
166 
`endif
167 
`endif
168 
 
169 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
170 
`ifndef CNT_BIN_CE
171 
`define CNT_BIN_CE
172 
`endif
173 
`ifndef DPRAM_1R1W
174 
`define DPRAM_1R1W
175 
`endif
176 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
177 
`define CNT_BIN_CE_REW_Q_ZQ_L1
178 
`endif
179 
`endif
180 
 
181 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
182 
`ifndef CNT_LFSR_CE
183 
`define CNT_LFSR_CE
184 
`endif
185 
`ifndef DPRAM_2R2W
186 
`define DPRAM_2R2W
187 
`endif
188 
`ifndef CNT_BIN_CE_REW_ZQ_L1
189 
`define CNT_BIN_CE_REW_ZQ_L1
190 
`endif
191 
`endif
192 
 
193 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
194 
`ifndef CNT_GRAY_CE_BIN
195 
`define CNT_GRAY_CE_BIN
196 
`endif
197 
`ifndef DPRAM_2R2W
198 
`define DPRAM_2R2W
199 
`endif
200 
`ifndef FIFO_CMP_ASYNC
201 
`define FIFO_CMP_ASYNC
202 
`endif
203 
`endif
204 
 
205 
`ifdef FIFO_2R2W_ASYNC
206 
`ifndef FIFO_1R1W_ASYNC
207 
`define FIFO_1R1W_ASYNC
208 
`endif
209 
`endif
210 
 
211 
`ifdef FIFO_1R1W_ASYNC
212 
`ifndef CNT_GRAY_CE_BIN
213 
`define CNT_GRAY_CE_BIN
214 
`endif
215 
`ifndef DPRAM_1R1W
216 
`define DPRAM_1R1W
217 
`endif
218 
`ifndef FIFO_CMP_ASYNC
219 
`define FIFO_CMP_ASYNC
220 
`endif
221 
`endif
222 
 
223 
`ifdef FIFO_CMP_ASYNC
224 
`ifndef DFF_SR
225 
`define DFF_SR
226 
`endif
227 
`ifndef DFF
228 
`define DFF
229 
`endif
230 
`endif
231 48 unneback 
 
232 
`ifdef REG_FILE
233 
`ifndef DPRAM_1R1W
234 
`define DPRAM_1R1W
235 
`endif
236 
`endif
237 6 unneback 
//////////////////////////////////////////////////////////////////////
238 
////                                                              ////
239 
////  Versatile library, clock and reset                          ////
240 
////                                                              ////
241 
////  Description                                                 ////
242 
////  Logic related to clock and reset                            ////
243 
////                                                              ////
244 
////                                                              ////
245 
////  To Do:                                                      ////
246 
////   - add more different registers                             ////
247 
////                                                              ////
248 
////  Author(s):                                                  ////
249 
////      - Michael Unneback, unneback@opencores.org              ////
250 
////        ORSoC AB                                              ////
251 
////                                                              ////
252 
//////////////////////////////////////////////////////////////////////
253 
////                                                              ////
254 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
255 
////                                                              ////
256 
//// This source file may be used and distributed without         ////
257 
//// restriction provided that this copyright statement is not    ////
258 
//// removed from the file and that any derivative work contains  ////
259 
//// the original copyright notice and the associated disclaimer. ////
260 
////                                                              ////
261 
//// This source file is free software; you can redistribute it   ////
262 
//// and/or modify it under the terms of the GNU Lesser General   ////
263 
//// Public License as published by the Free Software Foundation; ////
264 
//// either version 2.1 of the License, or (at your option) any   ////
265 
//// later version.                                               ////
266 
////                                                              ////
267 
//// This source is distributed in the hope that it will be       ////
268 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
269 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
270 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
271 
//// details.                                                     ////
272 
////                                                              ////
273 
//// You should have received a copy of the GNU Lesser General    ////
274 
//// Public License along with this source; if not, download it   ////
275 
//// from http://www.opencores.org/lgpl.shtml                     ////
276 
////                                                              ////
277 
//////////////////////////////////////////////////////////////////////
278 
 
279 48 unneback 
`ifdef ACTEL
280 
`ifdef GBUF
281 
`timescale 1 ns/100 ps
282 6 unneback 
// Global buffer
283 
// usage:
284 
// use to enable global buffers for high fan out signals such as clock and reset
285 
// Version: 8.4 8.4.0.33
286 
module gbuf(GL,CLK);
287 
output GL;
288 
input  CLK;
289 
 
290 
    wire GND;
291 
 
292 
    GND GND_1_net(.Y(GND));
293 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
294 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
295 
 
296 
endmodule
297 
`timescale 1 ns/1 ns
298 40 unneback 
`define MODULE gbuf
299 
module `BASE`MODULE ( i, o);
300 
`undef MODULE
301 6 unneback 
input i;
302 
output o;
303 
`ifdef SIM_GBUF
304 
assign o=i;
305 
`else
306 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
307 
`endif
308 
endmodule
309 40 unneback 
`endif
310 33 unneback 
 
311 6 unneback 
`else
312 33 unneback 
 
313 40 unneback 
`ifdef ALTERA
314 
`ifdef GBUF
315 21 unneback 
//altera
316 40 unneback 
`define MODULE gbuf
317 
module `BASE`MODULE ( i, o);
318 
`undef MODULE
319 33 unneback 
input i;
320 
output o;
321 
assign o = i;
322 
endmodule
323 40 unneback 
`endif
324 33 unneback 
 
325 6 unneback 
`else
326 
 
327 40 unneback 
`ifdef GBUF
328 6 unneback 
`timescale 1 ns/100 ps
329 40 unneback 
`define MODULE
330 
module `BASE`MODULE ( i, o);
331 
`undef MODULE
332 6 unneback 
input i;
333 
output o;
334 
assign o = i;
335 
endmodule
336 40 unneback 
`endif
337 6 unneback 
`endif // ALTERA
338 
`endif //ACTEL
339 
 
340 40 unneback 
`ifdef SYNC_RST
341 6 unneback 
// sync reset
342 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
343 6 unneback 
// output active high global reset sync with two DFFs
344 
`timescale 1 ns/100 ps
345 40 unneback 
`define MODULE sync_rst
346 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
347 
`undef MODULE
348 6 unneback 
input rst_n_i, clk;
349 
output rst_o;
350 18 unneback 
reg [1:0] tmp;
351 6 unneback 
always @ (posedge clk or negedge rst_n_i)
352 
if (!rst_n_i)
353 17 unneback 
        tmp <= 2'b11;
354 6 unneback 
else
355 33 unneback 
        tmp <= {1'b0,tmp[1]};
356 40 unneback 
`define MODULE gbuf
357 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
358 
`undef MODULE
359 6 unneback 
endmodule
360 40 unneback 
`endif
361 6 unneback 
 
362 40 unneback 
`ifdef PLL
363 6 unneback 
// vl_pll
364 
`ifdef ACTEL
365 32 unneback 
///////////////////////////////////////////////////////////////////////////////
366 17 unneback 
`timescale 1 ps/1 ps
367 40 unneback 
`define MODULE pll
368 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
369 
`undef MODULE
370 6 unneback 
parameter index = 0;
371 
parameter number_of_clk = 1;
372 17 unneback 
parameter period_time_0 = 20000;
373 
parameter period_time_1 = 20000;
374 
parameter period_time_2 = 20000;
375 
parameter lock_delay = 2000000;
376 6 unneback 
input clk_i, rst_n_i;
377 
output lock;
378 
output reg [0:number_of_clk-1] clk_o;
379 
output [0:number_of_clk-1] rst_o;
380 
 
381 
`ifdef SIM_PLL
382 
 
383 
always
384 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
385 
 
386 
generate if (number_of_clk > 1)
387 
always
388 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
389 
endgenerate
390 
 
391 
generate if (number_of_clk > 2)
392 
always
393 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
394 
endgenerate
395 
 
396 
genvar i;
397 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
398 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
399 
end
400 
endgenerate
401 
 
402 
assign #lock_delay lock = rst_n_i;
403 
 
404 
endmodule
405 
`else
406 
generate if (number_of_clk==1 & index==0) begin
407 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
408 
end
409 
endgenerate // index==0
410 
generate if (number_of_clk==1 & index==1) begin
411 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
412 
end
413 
endgenerate // index==1
414 
generate if (number_of_clk==1 & index==2) begin
415 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
416 
end
417 
endgenerate // index==2
418 
generate if (number_of_clk==1 & index==3) begin
419 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
420 
end
421 
endgenerate // index==0
422 
 
423 
generate if (number_of_clk==2 & index==0) begin
424 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
425 
end
426 
endgenerate // index==0
427 
generate if (number_of_clk==2 & index==1) begin
428 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
429 
end
430 
endgenerate // index==1
431 
generate if (number_of_clk==2 & index==2) begin
432 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
433 
end
434 
endgenerate // index==2
435 
generate if (number_of_clk==2 & index==3) begin
436 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
437 
end
438 
endgenerate // index==0
439 
 
440 
generate if (number_of_clk==3 & index==0) begin
441 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
442 
end
443 
endgenerate // index==0
444 
generate if (number_of_clk==3 & index==1) begin
445 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
446 
end
447 
endgenerate // index==1
448 
generate if (number_of_clk==3 & index==2) begin
449 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
450 
end
451 
endgenerate // index==2
452 
generate if (number_of_clk==3 & index==3) begin
453 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
454 
end
455 
endgenerate // index==0
456 
 
457 
genvar i;
458 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
459 40 unneback 
`define MODULE sync_rst
460 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
461 
`undef MODULE
462 6 unneback 
end
463 
endgenerate
464 
endmodule
465 
`endif
466 32 unneback 
///////////////////////////////////////////////////////////////////////////////
467 6 unneback 
 
468 
`else
469 
 
470 32 unneback 
///////////////////////////////////////////////////////////////////////////////
471 6 unneback 
`ifdef ALTERA
472 
 
473 32 unneback 
`timescale 1 ps/1 ps
474 40 unneback 
`define MODULE pll
475 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
476 
`undef MODULE
477 32 unneback 
parameter index = 0;
478 
parameter number_of_clk = 1;
479 
parameter period_time_0 = 20000;
480 
parameter period_time_1 = 20000;
481 
parameter period_time_2 = 20000;
482 
parameter period_time_3 = 20000;
483 
parameter period_time_4 = 20000;
484 
parameter lock_delay = 2000000;
485 
input clk_i, rst_n_i;
486 
output lock;
487 
output reg [0:number_of_clk-1] clk_o;
488 
output [0:number_of_clk-1] rst_o;
489 
 
490 
`ifdef SIM_PLL
491 
 
492 
always
493 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
494 
 
495 
generate if (number_of_clk > 1)
496 
always
497 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
498 
endgenerate
499 
 
500 
generate if (number_of_clk > 2)
501 
always
502 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
503 
endgenerate
504 
 
505 33 unneback 
generate if (number_of_clk > 3)
506 32 unneback 
always
507 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
508 
endgenerate
509 
 
510 33 unneback 
generate if (number_of_clk > 4)
511 32 unneback 
always
512 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
513 
endgenerate
514 
 
515 
genvar i;
516 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
517 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
518 
end
519 
endgenerate
520 
 
521 33 unneback 
//assign #lock_delay lock = rst_n_i;
522 
assign lock = rst_n_i;
523 32 unneback 
 
524 
endmodule
525 6 unneback 
`else
526 
 
527 33 unneback 
`ifdef VL_PLL0
528 
`ifdef VL_PLL0_CLK1
529 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
530 
`endif
531 
`ifdef VL_PLL0_CLK2
532 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
533 
`endif
534 
`ifdef VL_PLL0_CLK3
535 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
536 
`endif
537 
`ifdef VL_PLL0_CLK4
538 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
539 
`endif
540 
`ifdef VL_PLL0_CLK5
541 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
542 
`endif
543 
`endif
544 32 unneback 
 
545 33 unneback 
`ifdef VL_PLL1
546 
`ifdef VL_PLL1_CLK1
547 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
548 
`endif
549 
`ifdef VL_PLL1_CLK2
550 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
551 
`endif
552 
`ifdef VL_PLL1_CLK3
553 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
554 
`endif
555 
`ifdef VL_PLL1_CLK4
556 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
557 
`endif
558 
`ifdef VL_PLL1_CLK5
559 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
560 
`endif
561 
`endif
562 32 unneback 
 
563 33 unneback 
`ifdef VL_PLL2
564 
`ifdef VL_PLL2_CLK1
565 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
566 
`endif
567 
`ifdef VL_PLL2_CLK2
568 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
569 
`endif
570 
`ifdef VL_PLL2_CLK3
571 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
572 
`endif
573 
`ifdef VL_PLL2_CLK4
574 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
575 
`endif
576 
`ifdef VL_PLL2_CLK5
577 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
578 
`endif
579 
`endif
580 32 unneback 
 
581 33 unneback 
`ifdef VL_PLL3
582 
`ifdef VL_PLL3_CLK1
583 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
584 
`endif
585 
`ifdef VL_PLL3_CLK2
586 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
587 
`endif
588 
`ifdef VL_PLL3_CLK3
589 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
590 
`endif
591 
`ifdef VL_PLL3_CLK4
592 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
593 
`endif
594 
`ifdef VL_PLL3_CLK5
595 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
596 
`endif
597 
`endif
598 32 unneback 
 
599 
genvar i;
600 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
601 40 unneback 
`define MODULE sync_rst
602 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
603 
`undef MODULE
604 32 unneback 
end
605 
endgenerate
606 
endmodule
607 
`endif
608 
///////////////////////////////////////////////////////////////////////////////
609 
 
610 
`else
611 
 
612 6 unneback 
// generic PLL
613 17 unneback 
`timescale 1 ps/1 ps
614 40 unneback 
`define MODULE pll
615 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
616 
`undef MODULE
617 6 unneback 
parameter index = 0;
618 
parameter number_of_clk = 1;
619 17 unneback 
parameter period_time_0 = 20000;
620 
parameter period_time_1 = 20000;
621 
parameter period_time_2 = 20000;
622 6 unneback 
parameter lock_delay = 2000;
623 
input clk_i, rst_n_i;
624 
output lock;
625 
output reg [0:number_of_clk-1] clk_o;
626 
output [0:number_of_clk-1] rst_o;
627 
 
628 
always
629 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
630 
 
631 
generate if (number_of_clk > 1)
632 
always
633 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
634 
endgenerate
635 
 
636 
generate if (number_of_clk > 2)
637 
always
638 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
639 
endgenerate
640 
 
641 
genvar i;
642 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
643 40 unneback 
`define MODULE sync_rst
644 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
645 
`undef MODULE
646 6 unneback 
end
647 
endgenerate
648 
 
649 
assign #lock_delay lock = rst_n_i;
650 
 
651 
endmodule
652 
 
653 
`endif //altera
654 17 unneback 
`endif //actel
655 40 unneback 
`undef MODULE
656 
`endif//////////////////////////////////////////////////////////////////////
657 6 unneback 
////                                                              ////
658 
////  Versatile library, registers                                ////
659 
////                                                              ////
660 
////  Description                                                 ////
661 
////  Different type of registers                                 ////
662 
////                                                              ////
663 
////                                                              ////
664 
////  To Do:                                                      ////
665 
////   - add more different registers                             ////
666 
////                                                              ////
667 
////  Author(s):                                                  ////
668 
////      - Michael Unneback, unneback@opencores.org              ////
669 
////        ORSoC AB                                              ////
670 
////                                                              ////
671 
//////////////////////////////////////////////////////////////////////
672 
////                                                              ////
673 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
674 
////                                                              ////
675 
//// This source file may be used and distributed without         ////
676 
//// restriction provided that this copyright statement is not    ////
677 
//// removed from the file and that any derivative work contains  ////
678 
//// the original copyright notice and the associated disclaimer. ////
679 
////                                                              ////
680 
//// This source file is free software; you can redistribute it   ////
681 
//// and/or modify it under the terms of the GNU Lesser General   ////
682 
//// Public License as published by the Free Software Foundation; ////
683 
//// either version 2.1 of the License, or (at your option) any   ////
684 
//// later version.                                               ////
685 
////                                                              ////
686 
//// This source is distributed in the hope that it will be       ////
687 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
688 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
689 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
690 
//// details.                                                     ////
691 
////                                                              ////
692 
//// You should have received a copy of the GNU Lesser General    ////
693 
//// Public License along with this source; if not, download it   ////
694 
//// from http://www.opencores.org/lgpl.shtml                     ////
695 
////                                                              ////
696 
//////////////////////////////////////////////////////////////////////
697 
 
698 40 unneback 
`ifdef DFF
699 
`define MODULE dff
700 
module `BASE`MODULE ( d, q, clk, rst);
701 
`undef MODULE
702 6 unneback 
        parameter width = 1;
703 
        parameter reset_value = 0;
704 
 
705 
        input [width-1:0] d;
706 
        input clk, rst;
707 
        output reg [width-1:0] q;
708 
 
709 
        always @ (posedge clk or posedge rst)
710 
        if (rst)
711 
                q <= reset_value;
712 
        else
713 
                q <= d;
714 
 
715 
endmodule
716 40 unneback 
`endif
717 6 unneback 
 
718 40 unneback 
`ifdef DFF_ARRAY
719 
`define MODULE dff_array
720 
module `BASE`MODULE ( d, q, clk, rst);
721 
`undef MODULE
722 6 unneback 
 
723 
        parameter width = 1;
724 
        parameter depth = 2;
725 
        parameter reset_value = 1'b0;
726 
 
727 
        input [width-1:0] d;
728 
        input clk, rst;
729 
        output [width-1:0] q;
730 
        reg  [0:depth-1] q_tmp [width-1:0];
731 
        integer i;
732 
        always @ (posedge clk or posedge rst)
733 
        if (rst) begin
734 
            for (i=0;i<depth;i=i+1)
735 
                q_tmp[i] <= {width{reset_value}};
736 
        end else begin
737 
            q_tmp[0] <= d;
738 
            for (i=1;i<depth;i=i+1)
739 
                q_tmp[i] <= q_tmp[i-1];
740 
        end
741 
 
742 
    assign q = q_tmp[depth-1];
743 
 
744 
endmodule
745 40 unneback 
`endif
746 6 unneback 
 
747 40 unneback 
`ifdef DFF_CE
748 
`define MODULE dff_ce
749 
module `BASE`MODULE ( d, ce, q, clk, rst);
750 
`undef MODULE
751 6 unneback 
 
752 
        parameter width = 1;
753 
        parameter reset_value = 0;
754 
 
755 
        input [width-1:0] d;
756 
        input ce, clk, rst;
757 
        output reg [width-1:0] q;
758 
 
759 
        always @ (posedge clk or posedge rst)
760 
        if (rst)
761 
                q <= reset_value;
762 
        else
763 
                if (ce)
764 
                        q <= d;
765 
 
766 
endmodule
767 40 unneback 
`endif
768 6 unneback 
 
769 40 unneback 
`ifdef DFF_CE_CLEAR
770 
`define MODULE dff_ce_clear
771 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
772 
`undef MODULE
773 8 unneback 
 
774 
        parameter width = 1;
775 
        parameter reset_value = 0;
776 
 
777 
        input [width-1:0] d;
778 10 unneback 
        input ce, clear, clk, rst;
779 8 unneback 
        output reg [width-1:0] q;
780 
 
781 
        always @ (posedge clk or posedge rst)
782 
        if (rst)
783 
            q <= reset_value;
784 
        else
785 
            if (ce)
786 
                if (clear)
787 
                    q <= {width{1'b0}};
788 
                else
789 
                    q <= d;
790 
 
791 
endmodule
792 40 unneback 
`endif
793 8 unneback 
 
794 40 unneback 
`ifdef DF_CE_SET
795 
`define MODULE dff_ce_set
796 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
797 
`undef MODULE
798 24 unneback 
 
799 
        parameter width = 1;
800 
        parameter reset_value = 0;
801 
 
802 
        input [width-1:0] d;
803 
        input ce, set, clk, rst;
804 
        output reg [width-1:0] q;
805 
 
806 
        always @ (posedge clk or posedge rst)
807 
        if (rst)
808 
            q <= reset_value;
809 
        else
810 
            if (ce)
811 
                if (set)
812 
                    q <= {width{1'b1}};
813 
                else
814 
                    q <= d;
815 
 
816 
endmodule
817 40 unneback 
`endif
818 24 unneback 
 
819 40 unneback 
`ifdef SPR
820 
`define MODULE spr
821 
module `BASE`MODULE ( sp, r, q, clk, rst);
822 
`undef MODULE
823 
 
824 29 unneback 
        parameter width = 1;
825 
        parameter reset_value = 0;
826 
 
827 
        input sp, r;
828 
        output reg q;
829 
        input clk, rst;
830 
 
831 
        always @ (posedge clk or posedge rst)
832 
        if (rst)
833 
            q <= reset_value;
834 
        else
835 
            if (sp)
836 
                q <= 1'b1;
837 
            else if (r)
838 
                q <= 1'b0;
839 
 
840 
endmodule
841 40 unneback 
`endif
842 29 unneback 
 
843 40 unneback 
`ifdef SRP
844 
`define MODULE srp
845 
module `BASE`MODULE ( s, rp, q, clk, rst);
846 
`undef MODULE
847 
 
848 29 unneback 
        parameter width = 1;
849 
        parameter reset_value = 0;
850 
 
851 
        input s, rp;
852 
        output reg q;
853 
        input clk, rst;
854 
 
855 
        always @ (posedge clk or posedge rst)
856 
        if (rst)
857 
            q <= reset_value;
858 
        else
859 
            if (rp)
860 
                q <= 1'b0;
861 
            else if (s)
862 
                q <= 1'b1;
863 
 
864 
endmodule
865 40 unneback 
`endif
866 29 unneback 
 
867 40 unneback 
`ifdef ALTERA
868 29 unneback 
 
869 40 unneback 
`ifdef DFF_SR
870 6 unneback 
// megafunction wizard: %LPM_FF%
871 
// GENERATION: STANDARD
872 
// VERSION: WM1.0
873 
// MODULE: lpm_ff
874 
 
875 
// ============================================================
876 
// File Name: dff_sr.v
877 
// Megafunction Name(s):
878 
//                      lpm_ff
879 
//
880 
// Simulation Library Files(s):
881 
//                      lpm
882 
// ============================================================
883 
// ************************************************************
884 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
885 
//
886 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
887 
// ************************************************************
888 
 
889 
 
890 
//Copyright (C) 1991-2010 Altera Corporation
891 
//Your use of Altera Corporation's design tools, logic functions
892 
//and other software and tools, and its AMPP partner logic
893 
//functions, and any output files from any of the foregoing
894 
//(including device programming or simulation files), and any
895 
//associated documentation or information are expressly subject
896 
//to the terms and conditions of the Altera Program License
897 
//Subscription Agreement, Altera MegaCore Function License
898 
//Agreement, or other applicable license agreement, including,
899 
//without limitation, that your use is for the sole purpose of
900 
//programming logic devices manufactured by Altera and sold by
901 
//Altera or its authorized distributors.  Please refer to the
902 
//applicable agreement for further details.
903 
 
904 
 
905 
// synopsys translate_off
906 
`timescale 1 ps / 1 ps
907 
// synopsys translate_on
908 40 unneback 
`define MODULE dff_sr
909 
module `BASE`MODULE (
910 
`undef MODULE
911 
 
912 6 unneback 
        aclr,
913 
        aset,
914 
        clock,
915 
        data,
916 
        q);
917 
 
918 
        input     aclr;
919 
        input     aset;
920 
        input     clock;
921 
        input     data;
922 
        output    q;
923 
 
924 
        wire [0:0] sub_wire0;
925 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
926 
        wire  q = sub_wire1;
927 
        wire  sub_wire2 = data;
928 
        wire  sub_wire3 = sub_wire2;
929 
 
930 
        lpm_ff  lpm_ff_component (
931 
                                .aclr (aclr),
932 
                                .clock (clock),
933 
                                .data (sub_wire3),
934 
                                .aset (aset),
935 
                                .q (sub_wire0)
936 
                                // synopsys translate_off
937 
                                ,
938 
                                .aload (),
939 
                                .enable (),
940 
                                .sclr (),
941 
                                .sload (),
942 
                                .sset ()
943 
                                // synopsys translate_on
944 
                                );
945 
        defparam
946 
                lpm_ff_component.lpm_fftype = "DFF",
947 
                lpm_ff_component.lpm_type = "LPM_FF",
948 
                lpm_ff_component.lpm_width = 1;
949 
 
950 
 
951 
endmodule
952 
 
953 
// ============================================================
954 
// CNX file retrieval info
955 
// ============================================================
956 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
957 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
958 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
959 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
960 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
961 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
962 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
963 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
964 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
965 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
966 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
967 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
968 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
969 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
970 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
971 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
972 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
973 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
974 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
975 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
976 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
977 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
978 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
979 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
980 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
981 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
982 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
983 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
984 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
985 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
986 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
987 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
988 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
989 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
990 
// Retrieval info: LIB_FILE: lpm
991 40 unneback 
`endif
992 6 unneback 
 
993 
`else
994 
 
995 40 unneback 
`ifdef DFF_SR
996 
`define MODULE dff_sr
997 
module `BASE`MODULE ( aclr, aset, clock, data, q);
998 
`undef MODULE
999 6 unneback 
 
1000 
    input         aclr;
1001 
    input         aset;
1002 
    input         clock;
1003 
    input         data;
1004 
    output reg    q;
1005 
 
1006 
   always @ (posedge clock or posedge aclr or posedge aset)
1007 
     if (aclr)
1008 
       q <= 1'b0;
1009 
     else if (aset)
1010 
       q <= 1'b1;
1011 
     else
1012 
       q <= data;
1013 
 
1014 
endmodule
1015 40 unneback 
`endif
1016 6 unneback 
 
1017 
`endif
1018 
 
1019 
// LATCH
1020 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1021 
`ifdef ALTERA
1022 40 unneback 
 
1023 
`ifdef LATCH
1024 
`define MODULE latch
1025 
module `BASE`MODULE ( d, le, q, clk);
1026 
`undef MODULE
1027 6 unneback 
input d, le;
1028 
output q;
1029 
input clk;
1030 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1031 
endmodule
1032 40 unneback 
`endif
1033 
 
1034 6 unneback 
`else
1035 40 unneback 
 
1036 
`ifdef LATCH
1037 
`define MODULE latch
1038 
module `BASE`MODULE ( d, le, q, clk);
1039 
`undef MODULE
1040 6 unneback 
input d, le;
1041 48 unneback 
input clk;
1042 
always @ (le or d)
1043 60 unneback 
if (le)
1044 48 unneback 
    d <= q;
1045 6 unneback 
endmodule
1046 15 unneback 
`endif
1047 
 
1048 40 unneback 
`endif
1049 
 
1050 
`ifdef SHREG
1051 
`define MODULE shreg
1052 
module `BASE`MODULE ( d, q, clk, rst);
1053 
`undef MODULE
1054 
 
1055 17 unneback 
parameter depth = 10;
1056 
input d;
1057 
output q;
1058 
input clk, rst;
1059 
 
1060 
reg [1:depth] dffs;
1061 
 
1062 
always @ (posedge clk or posedge rst)
1063 
if (rst)
1064 
    dffs <= {depth{1'b0}};
1065 
else
1066 
    dffs <= {d,dffs[1:depth-1]};
1067 
assign q = dffs[depth];
1068 
endmodule
1069 40 unneback 
`endif
1070 17 unneback 
 
1071 40 unneback 
`ifdef SHREG_CE
1072 
`define MODULE shreg_ce
1073 
module `BASE`MODULE ( d, ce, q, clk, rst);
1074 
`undef MODULE
1075 17 unneback 
parameter depth = 10;
1076 
input d, ce;
1077 
output q;
1078 
input clk, rst;
1079 
 
1080 
reg [1:depth] dffs;
1081 
 
1082 
always @ (posedge clk or posedge rst)
1083 
if (rst)
1084 
    dffs <= {depth{1'b0}};
1085 
else
1086 
    if (ce)
1087 
        dffs <= {d,dffs[1:depth-1]};
1088 
assign q = dffs[depth];
1089 
endmodule
1090 40 unneback 
`endif
1091 17 unneback 
 
1092 40 unneback 
`ifdef DELAY
1093 
`define MODULE delay
1094 
module `BASE`MODULE ( d, q, clk, rst);
1095 
`undef MODULE
1096 15 unneback 
parameter depth = 10;
1097 
input d;
1098 
output q;
1099 
input clk, rst;
1100 
 
1101 
reg [1:depth] dffs;
1102 
 
1103 
always @ (posedge clk or posedge rst)
1104 
if (rst)
1105 
    dffs <= {depth{1'b0}};
1106 
else
1107 
    dffs <= {d,dffs[1:depth-1]};
1108 
assign q = dffs[depth];
1109 17 unneback 
endmodule
1110 40 unneback 
`endif
1111 17 unneback 
 
1112 40 unneback 
`ifdef DELAY_EMPTYFLAG
1113 
`define MODULE delay_emptyflag
1114 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1115 40 unneback 
`undef MODULE
1116 17 unneback 
parameter depth = 10;
1117 
input d;
1118 
output q, emptyflag;
1119 
input clk, rst;
1120 
 
1121 
reg [1:depth] dffs;
1122 
 
1123 
always @ (posedge clk or posedge rst)
1124 
if (rst)
1125 
    dffs <= {depth{1'b0}};
1126 
else
1127 
    dffs <= {d,dffs[1:depth-1]};
1128 
assign q = dffs[depth];
1129 
assign emptyflag = !(|dffs);
1130 
endmodule
1131 40 unneback 
`endif
1132 17 unneback 
//////////////////////////////////////////////////////////////////////
1133 6 unneback 
////                                                              ////
1134 18 unneback 
////  Logic functions                                             ////
1135 
////                                                              ////
1136 
////  Description                                                 ////
1137 
////  Logic functions such as multiplexers                        ////
1138 
////                                                              ////
1139 
////                                                              ////
1140 
////  To Do:                                                      ////
1141 
////   -                                                          ////
1142 
////                                                              ////
1143 
////  Author(s):                                                  ////
1144 
////      - Michael Unneback, unneback@opencores.org              ////
1145 
////        ORSoC AB                                              ////
1146 
////                                                              ////
1147 
//////////////////////////////////////////////////////////////////////
1148 
////                                                              ////
1149 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1150 
////                                                              ////
1151 
//// This source file may be used and distributed without         ////
1152 
//// restriction provided that this copyright statement is not    ////
1153 
//// removed from the file and that any derivative work contains  ////
1154 
//// the original copyright notice and the associated disclaimer. ////
1155 
////                                                              ////
1156 
//// This source file is free software; you can redistribute it   ////
1157 
//// and/or modify it under the terms of the GNU Lesser General   ////
1158 
//// Public License as published by the Free Software Foundation; ////
1159 
//// either version 2.1 of the License, or (at your option) any   ////
1160 
//// later version.                                               ////
1161 
////                                                              ////
1162 
//// This source is distributed in the hope that it will be       ////
1163 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1164 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1165 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1166 
//// details.                                                     ////
1167 
////                                                              ////
1168 
//// You should have received a copy of the GNU Lesser General    ////
1169 
//// Public License along with this source; if not, download it   ////
1170 
//// from http://www.opencores.org/lgpl.shtml                     ////
1171 
////                                                              ////
1172 
//////////////////////////////////////////////////////////////////////
1173 40 unneback 
`ifdef MUX_ANDOR
1174 
`define MODULE mux_andor
1175 
module `BASE`MODULE ( a, sel, dout);
1176 
`undef MODULE
1177 36 unneback 
 
1178 
parameter width = 32;
1179 
parameter nr_of_ports = 4;
1180 
 
1181 
input [nr_of_ports*width-1:0] a;
1182 
input [nr_of_ports-1:0] sel;
1183 
output reg [width-1:0] dout;
1184 
 
1185 38 unneback 
integer i,j;
1186 
 
1187 36 unneback 
always @ (a, sel)
1188 
begin
1189 
    dout = a[width-1:0] & {width{sel[0]}};
1190 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1191 
        for (j=0;j<width;j=j+1)
1192 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1193 36 unneback 
end
1194 
 
1195 
endmodule
1196 40 unneback 
`endif
1197 36 unneback 
 
1198 40 unneback 
`ifdef MUX2_ANDOR
1199 
`define MODULE mux2_andor
1200 
module `BASE`MODULE ( a1, a0, sel, dout);
1201 
`undef MODULE
1202 18 unneback 
 
1203 34 unneback 
parameter width = 32;
1204 35 unneback 
localparam nr_of_ports = 2;
1205 34 unneback 
input [width-1:0] a1, a0;
1206 
input [nr_of_ports-1:0] sel;
1207 
output [width-1:0] dout;
1208 
 
1209 40 unneback 
`define MODULE mux_andor
1210 
`BASE`MODULE
1211 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1212 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1213 40 unneback 
`undef MODULE
1214 
 
1215 34 unneback 
endmodule
1216 40 unneback 
`endif
1217 34 unneback 
 
1218 40 unneback 
`ifdef MUX3_ANDOR
1219 
`define MODULE mux3_andor
1220 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1221 
`undef MODULE
1222 34 unneback 
 
1223 
parameter width = 32;
1224 35 unneback 
localparam nr_of_ports = 3;
1225 34 unneback 
input [width-1:0] a2, a1, a0;
1226 
input [nr_of_ports-1:0] sel;
1227 
output [width-1:0] dout;
1228 
 
1229 40 unneback 
`define MODULE mux_andor
1230 
`BASE`MODULE
1231 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1232 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1233 40 unneback 
`undef MODULE
1234 34 unneback 
endmodule
1235 40 unneback 
`endif
1236 34 unneback 
 
1237 40 unneback 
`ifdef MUX4_ANDOR
1238 
`define MODULE mux4_andor
1239 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1240 
`undef MODULE
1241 18 unneback 
 
1242 
parameter width = 32;
1243 35 unneback 
localparam nr_of_ports = 4;
1244 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1245 
input [nr_of_ports-1:0] sel;
1246 22 unneback 
output [width-1:0] dout;
1247 18 unneback 
 
1248 40 unneback 
`define MODULE mux_andor
1249 
`BASE`MODULE
1250 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1251 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1252 40 unneback 
`undef MODULE
1253 18 unneback 
 
1254 
endmodule
1255 40 unneback 
`endif
1256 18 unneback 
 
1257 40 unneback 
`ifdef MUX5_ANDOR
1258 
`define MODULE mux5_andor
1259 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1260 
`undef MODULE
1261 18 unneback 
 
1262 
parameter width = 32;
1263 35 unneback 
localparam nr_of_ports = 5;
1264 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1265 
input [nr_of_ports-1:0] sel;
1266 22 unneback 
output [width-1:0] dout;
1267 18 unneback 
 
1268 40 unneback 
`define MODULE mux_andor
1269 
`BASE`MODULE
1270 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1271 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1272 40 unneback 
`undef MODULE
1273 18 unneback 
 
1274 
endmodule
1275 40 unneback 
`endif
1276 18 unneback 
 
1277 40 unneback 
`ifdef MUX6_ANDOR
1278 
`define MODULE mux6_andor
1279 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1280 
`undef MODULE
1281 18 unneback 
 
1282 
parameter width = 32;
1283 35 unneback 
localparam nr_of_ports = 6;
1284 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1285 
input [nr_of_ports-1:0] sel;
1286 22 unneback 
output [width-1:0] dout;
1287 18 unneback 
 
1288 40 unneback 
`define MODULE mux_andor
1289 
`BASE`MODULE
1290 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1291 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1292 40 unneback 
`undef MODULE
1293 18 unneback 
 
1294 
endmodule
1295 40 unneback 
`endif
1296 43 unneback 
 
1297 
`ifdef PARITY
1298 
 
1299 
`define MODULE parity_generate
1300 
module `BASE`MODULE (data, parity);
1301 
`undef MODULE
1302 
parameter word_size = 32;
1303 
parameter chunk_size = 8;
1304 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1305 
input [word_size-1:0] data;
1306 
output reg [word_size/chunk_size-1:0] parity;
1307 
integer i,j;
1308 
always @ (data)
1309 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1310 
    parity[i] = parity_type;
1311 
    for (j=0;j<chunk_size;j=j+1) begin
1312 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1313 43 unneback 
    end
1314 
end
1315 
endmodule
1316 
 
1317 
`define MODULE parity_check
1318 
module `BASE`MODULE( data, parity, parity_error);
1319 
`undef MODULE
1320 
parameter word_size = 32;
1321 
parameter chunk_size = 8;
1322 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1323 
input [word_size-1:0] data;
1324 
input [word_size/chunk_size-1:0] parity;
1325 
output parity_error;
1326 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1327 43 unneback 
integer i,j;
1328 
always @ (data or parity)
1329 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1330 
    error_flag[i] = parity[i] ^ parity_type;
1331 
    for (j=0;j<chunk_size;j=j+1) begin
1332 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1333 43 unneback 
    end
1334 
end
1335 
assign parity_error = |error_flag;
1336 
endmodule
1337 
 
1338 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1339 
////                                                              ////
1340 
////  IO functions                                                ////
1341 
////                                                              ////
1342 
////  Description                                                 ////
1343 
////  IO functions such as IOB flip-flops                         ////
1344 
////                                                              ////
1345 
////                                                              ////
1346 
////  To Do:                                                      ////
1347 
////   -                                                          ////
1348 
////                                                              ////
1349 
////  Author(s):                                                  ////
1350 
////      - Michael Unneback, unneback@opencores.org              ////
1351 
////        ORSoC AB                                              ////
1352 
////                                                              ////
1353 18 unneback 
//////////////////////////////////////////////////////////////////////
1354 
////                                                              ////
1355 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1356 
////                                                              ////
1357 
//// This source file may be used and distributed without         ////
1358 
//// restriction provided that this copyright statement is not    ////
1359 
//// removed from the file and that any derivative work contains  ////
1360 
//// the original copyright notice and the associated disclaimer. ////
1361 
////                                                              ////
1362 
//// This source file is free software; you can redistribute it   ////
1363 
//// and/or modify it under the terms of the GNU Lesser General   ////
1364 
//// Public License as published by the Free Software Foundation; ////
1365 
//// either version 2.1 of the License, or (at your option) any   ////
1366 
//// later version.                                               ////
1367 
////                                                              ////
1368 
//// This source is distributed in the hope that it will be       ////
1369 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1370 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1371 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1372 
//// details.                                                     ////
1373 
////                                                              ////
1374 
//// You should have received a copy of the GNU Lesser General    ////
1375 
//// Public License along with this source; if not, download it   ////
1376 
//// from http://www.opencores.org/lgpl.shtml                     ////
1377 
////                                                              ////
1378 
//////////////////////////////////////////////////////////////////////
1379 45 unneback 
`timescale 1ns/1ns
1380 44 unneback 
`ifdef O_DFF
1381 
`define MODULE o_dff
1382 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1383 
`undef MODULE
1384 
parameter width = 1;
1385 45 unneback 
parameter reset_value = {width{1'b0}};
1386 
input  [width-1:0]  d_i;
1387 44 unneback 
output [width-1:0] o_pad;
1388 
input clk, rst;
1389 
wire [width-1:0] d_i_int `SYN_KEEP;
1390 45 unneback 
reg  [width-1:0] o_pad_int;
1391 44 unneback 
assign d_i_int = d_i;
1392 
genvar i;
1393 45 unneback 
generate
1394 44 unneback 
for (i=0;i<width;i=i+1) begin
1395 
    always @ (posedge clk or posedge rst)
1396 
    if (rst)
1397 45 unneback 
        o_pad_int[i] <= reset_value[i];
1398 44 unneback 
    else
1399 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1400 
    assign #1 o_pad[i] = o_pad_int[i];
1401 44 unneback 
end
1402 
endgenerate
1403 
endmodule
1404 
`endif
1405 
 
1406 45 unneback 
`timescale 1ns/1ns
1407 44 unneback 
`ifdef IO_DFF_OE
1408 
`define MODULE io_dff_oe
1409 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1410 
`undef MODULE
1411 
parameter width = 1;
1412 
input  [width-1:0] d_o;
1413 
output reg [width-1:0] d_i;
1414 
input oe;
1415 
inout [width-1:0] io_pad;
1416 
input clk, rst;
1417 
wire [width-1:0] oe_d `SYN_KEEP;
1418 
reg [width-1:0] oe_q;
1419 
reg [width-1:0] d_o_q;
1420 
assign oe_d = {width{oe}};
1421 
genvar i;
1422 
generate
1423 
for (i=0;i<width;i=i+1) begin
1424 
    always @ (posedge clk or posedge rst)
1425 
    if (rst)
1426 
        oe_q[i] <= 1'b0;
1427 
    else
1428 
        oe_q[i] <= oe_d[i];
1429 
    always @ (posedge clk or posedge rst)
1430 
    if (rst)
1431 
        d_o_q[i] <= 1'b0;
1432 
    else
1433 
        d_o_q[i] <= d_o[i];
1434 
    always @ (posedge clk or posedge rst)
1435 
    if (rst)
1436 
        d_i[i] <= 1'b0;
1437 
    else
1438 
        d_i[i] <= io_pad[i];
1439 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1440 44 unneback 
end
1441 
endgenerate
1442 
endmodule
1443 
`endif
1444 
`ifdef CNT_BIN
1445 
//////////////////////////////////////////////////////////////////////
1446 
////                                                              ////
1447 6 unneback 
////  Versatile counter                                           ////
1448 
////                                                              ////
1449 
////  Description                                                 ////
1450 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1451 
////  counter                                                     ////
1452 
////                                                              ////
1453 
////  To Do:                                                      ////
1454 
////   - add LFSR with more taps                                  ////
1455 
////                                                              ////
1456 
////  Author(s):                                                  ////
1457 
////      - Michael Unneback, unneback@opencores.org              ////
1458 
////        ORSoC AB                                              ////
1459 
////                                                              ////
1460 
//////////////////////////////////////////////////////////////////////
1461 
////                                                              ////
1462 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1463 
////                                                              ////
1464 
//// This source file may be used and distributed without         ////
1465 
//// restriction provided that this copyright statement is not    ////
1466 
//// removed from the file and that any derivative work contains  ////
1467 
//// the original copyright notice and the associated disclaimer. ////
1468 
////                                                              ////
1469 
//// This source file is free software; you can redistribute it   ////
1470 
//// and/or modify it under the terms of the GNU Lesser General   ////
1471 
//// Public License as published by the Free Software Foundation; ////
1472 
//// either version 2.1 of the License, or (at your option) any   ////
1473 
//// later version.                                               ////
1474 
////                                                              ////
1475 
//// This source is distributed in the hope that it will be       ////
1476 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1477 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1478 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1479 
//// details.                                                     ////
1480 
////                                                              ////
1481 
//// You should have received a copy of the GNU Lesser General    ////
1482 
//// Public License along with this source; if not, download it   ////
1483 
//// from http://www.opencores.org/lgpl.shtml                     ////
1484 
////                                                              ////
1485 
//////////////////////////////////////////////////////////////////////
1486 
 
1487 
// binary counter
1488 22 unneback 
 
1489 40 unneback 
`define MODULE cnt_bin
1490 
module `BASE`MODULE (
1491 
`undef MODULE
1492 
 q, rst, clk);
1493 
 
1494 22 unneback 
   parameter length = 4;
1495 
   output [length:1] q;
1496 
   input rst;
1497 
   input clk;
1498 
 
1499 
   parameter clear_value = 0;
1500 
   parameter set_value = 1;
1501 
   parameter wrap_value = 0;
1502 
   parameter level1_value = 15;
1503 
 
1504 
   reg  [length:1] qi;
1505 
   wire [length:1] q_next;
1506 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1507 
 
1508 
   always @ (posedge clk or posedge rst)
1509 
     if (rst)
1510 
       qi <= {length{1'b0}};
1511 
     else
1512 
       qi <= q_next;
1513 
 
1514 
   assign q = qi;
1515 
 
1516 
endmodule
1517 40 unneback 
`endif
1518 
`ifdef CNT_BIN_CLEAR
1519 22 unneback 
//////////////////////////////////////////////////////////////////////
1520 
////                                                              ////
1521 
////  Versatile counter                                           ////
1522 
////                                                              ////
1523 
////  Description                                                 ////
1524 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1525 
////  counter                                                     ////
1526 
////                                                              ////
1527 
////  To Do:                                                      ////
1528 
////   - add LFSR with more taps                                  ////
1529 
////                                                              ////
1530 
////  Author(s):                                                  ////
1531 
////      - Michael Unneback, unneback@opencores.org              ////
1532 
////        ORSoC AB                                              ////
1533 
////                                                              ////
1534 
//////////////////////////////////////////////////////////////////////
1535 
////                                                              ////
1536 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1537 
////                                                              ////
1538 
//// This source file may be used and distributed without         ////
1539 
//// restriction provided that this copyright statement is not    ////
1540 
//// removed from the file and that any derivative work contains  ////
1541 
//// the original copyright notice and the associated disclaimer. ////
1542 
////                                                              ////
1543 
//// This source file is free software; you can redistribute it   ////
1544 
//// and/or modify it under the terms of the GNU Lesser General   ////
1545 
//// Public License as published by the Free Software Foundation; ////
1546 
//// either version 2.1 of the License, or (at your option) any   ////
1547 
//// later version.                                               ////
1548 
////                                                              ////
1549 
//// This source is distributed in the hope that it will be       ////
1550 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1551 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1552 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1553 
//// details.                                                     ////
1554 
////                                                              ////
1555 
//// You should have received a copy of the GNU Lesser General    ////
1556 
//// Public License along with this source; if not, download it   ////
1557 
//// from http://www.opencores.org/lgpl.shtml                     ////
1558 
////                                                              ////
1559 
//////////////////////////////////////////////////////////////////////
1560 
 
1561 
// binary counter
1562 
 
1563 40 unneback 
`define MODULE cnt_bin_clear
1564 
module `BASE`MODULE (
1565 
`undef MODULE
1566 
 clear, q, rst, clk);
1567 
 
1568 22 unneback 
   parameter length = 4;
1569 
   input clear;
1570 
   output [length:1] q;
1571 
   input rst;
1572 
   input clk;
1573 
 
1574 
   parameter clear_value = 0;
1575 
   parameter set_value = 1;
1576 
   parameter wrap_value = 0;
1577 
   parameter level1_value = 15;
1578 
 
1579 
   reg  [length:1] qi;
1580 
   wire [length:1] q_next;
1581 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1582 
 
1583 
   always @ (posedge clk or posedge rst)
1584 
     if (rst)
1585 
       qi <= {length{1'b0}};
1586 
     else
1587 
       qi <= q_next;
1588 
 
1589 
   assign q = qi;
1590 
 
1591 
endmodule
1592 40 unneback 
`endif
1593 
`ifdef CNT_BIN_CE
1594 22 unneback 
//////////////////////////////////////////////////////////////////////
1595 
////                                                              ////
1596 
////  Versatile counter                                           ////
1597 
////                                                              ////
1598 
////  Description                                                 ////
1599 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1600 
////  counter                                                     ////
1601 
////                                                              ////
1602 
////  To Do:                                                      ////
1603 
////   - add LFSR with more taps                                  ////
1604 
////                                                              ////
1605 
////  Author(s):                                                  ////
1606 
////      - Michael Unneback, unneback@opencores.org              ////
1607 
////        ORSoC AB                                              ////
1608 
////                                                              ////
1609 
//////////////////////////////////////////////////////////////////////
1610 
////                                                              ////
1611 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1612 
////                                                              ////
1613 
//// This source file may be used and distributed without         ////
1614 
//// restriction provided that this copyright statement is not    ////
1615 
//// removed from the file and that any derivative work contains  ////
1616 
//// the original copyright notice and the associated disclaimer. ////
1617 
////                                                              ////
1618 
//// This source file is free software; you can redistribute it   ////
1619 
//// and/or modify it under the terms of the GNU Lesser General   ////
1620 
//// Public License as published by the Free Software Foundation; ////
1621 
//// either version 2.1 of the License, or (at your option) any   ////
1622 
//// later version.                                               ////
1623 
////                                                              ////
1624 
//// This source is distributed in the hope that it will be       ////
1625 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1626 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1627 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1628 
//// details.                                                     ////
1629 
////                                                              ////
1630 
//// You should have received a copy of the GNU Lesser General    ////
1631 
//// Public License along with this source; if not, download it   ////
1632 
//// from http://www.opencores.org/lgpl.shtml                     ////
1633 
////                                                              ////
1634 
//////////////////////////////////////////////////////////////////////
1635 
 
1636 
// binary counter
1637 6 unneback 
 
1638 40 unneback 
`define MODULE cnt_bin_ce
1639 
module `BASE`MODULE (
1640 
`undef MODULE
1641 
 cke, q, rst, clk);
1642 
 
1643 6 unneback 
   parameter length = 4;
1644 
   input cke;
1645 
   output [length:1] q;
1646 
   input rst;
1647 
   input clk;
1648 
 
1649 
   parameter clear_value = 0;
1650 
   parameter set_value = 1;
1651 
   parameter wrap_value = 0;
1652 
   parameter level1_value = 15;
1653 
 
1654 
   reg  [length:1] qi;
1655 
   wire [length:1] q_next;
1656 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1657 
 
1658 
   always @ (posedge clk or posedge rst)
1659 
     if (rst)
1660 
       qi <= {length{1'b0}};
1661 
     else
1662 
     if (cke)
1663 
       qi <= q_next;
1664 
 
1665 
   assign q = qi;
1666 
 
1667 
endmodule
1668 40 unneback 
`endif
1669 
`ifdef CNT_BIN_CE_CLEAR
1670 6 unneback 
//////////////////////////////////////////////////////////////////////
1671 
////                                                              ////
1672 
////  Versatile counter                                           ////
1673 
////                                                              ////
1674 
////  Description                                                 ////
1675 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1676 
////  counter                                                     ////
1677 
////                                                              ////
1678 
////  To Do:                                                      ////
1679 
////   - add LFSR with more taps                                  ////
1680 
////                                                              ////
1681 
////  Author(s):                                                  ////
1682 
////      - Michael Unneback, unneback@opencores.org              ////
1683 
////        ORSoC AB                                              ////
1684 
////                                                              ////
1685 
//////////////////////////////////////////////////////////////////////
1686 
////                                                              ////
1687 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1688 
////                                                              ////
1689 
//// This source file may be used and distributed without         ////
1690 
//// restriction provided that this copyright statement is not    ////
1691 
//// removed from the file and that any derivative work contains  ////
1692 
//// the original copyright notice and the associated disclaimer. ////
1693 
////                                                              ////
1694 
//// This source file is free software; you can redistribute it   ////
1695 
//// and/or modify it under the terms of the GNU Lesser General   ////
1696 
//// Public License as published by the Free Software Foundation; ////
1697 
//// either version 2.1 of the License, or (at your option) any   ////
1698 
//// later version.                                               ////
1699 
////                                                              ////
1700 
//// This source is distributed in the hope that it will be       ////
1701 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1702 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1703 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1704 
//// details.                                                     ////
1705 
////                                                              ////
1706 
//// You should have received a copy of the GNU Lesser General    ////
1707 
//// Public License along with this source; if not, download it   ////
1708 
//// from http://www.opencores.org/lgpl.shtml                     ////
1709 
////                                                              ////
1710 
//////////////////////////////////////////////////////////////////////
1711 
 
1712 
// binary counter
1713 
 
1714 40 unneback 
`define MODULE cnt_bin_ce_clear
1715 
module `BASE`MODULE (
1716 
`undef MODULE
1717 
 clear, cke, q, rst, clk);
1718 
 
1719 6 unneback 
   parameter length = 4;
1720 
   input clear;
1721 
   input cke;
1722 
   output [length:1] q;
1723 
   input rst;
1724 
   input clk;
1725 
 
1726 
   parameter clear_value = 0;
1727 
   parameter set_value = 1;
1728 
   parameter wrap_value = 0;
1729 
   parameter level1_value = 15;
1730 
 
1731 
   reg  [length:1] qi;
1732 
   wire [length:1] q_next;
1733 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1734 
 
1735 
   always @ (posedge clk or posedge rst)
1736 
     if (rst)
1737 
       qi <= {length{1'b0}};
1738 
     else
1739 
     if (cke)
1740 
       qi <= q_next;
1741 
 
1742 
   assign q = qi;
1743 
 
1744 
endmodule
1745 40 unneback 
`endif
1746 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1747 6 unneback 
//////////////////////////////////////////////////////////////////////
1748 
////                                                              ////
1749 
////  Versatile counter                                           ////
1750 
////                                                              ////
1751 
////  Description                                                 ////
1752 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1753 
////  counter                                                     ////
1754 
////                                                              ////
1755 
////  To Do:                                                      ////
1756 
////   - add LFSR with more taps                                  ////
1757 
////                                                              ////
1758 
////  Author(s):                                                  ////
1759 
////      - Michael Unneback, unneback@opencores.org              ////
1760 
////        ORSoC AB                                              ////
1761 
////                                                              ////
1762 
//////////////////////////////////////////////////////////////////////
1763 
////                                                              ////
1764 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1765 
////                                                              ////
1766 
//// This source file may be used and distributed without         ////
1767 
//// restriction provided that this copyright statement is not    ////
1768 
//// removed from the file and that any derivative work contains  ////
1769 
//// the original copyright notice and the associated disclaimer. ////
1770 
////                                                              ////
1771 
//// This source file is free software; you can redistribute it   ////
1772 
//// and/or modify it under the terms of the GNU Lesser General   ////
1773 
//// Public License as published by the Free Software Foundation; ////
1774 
//// either version 2.1 of the License, or (at your option) any   ////
1775 
//// later version.                                               ////
1776 
////                                                              ////
1777 
//// This source is distributed in the hope that it will be       ////
1778 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1779 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1780 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1781 
//// details.                                                     ////
1782 
////                                                              ////
1783 
//// You should have received a copy of the GNU Lesser General    ////
1784 
//// Public License along with this source; if not, download it   ////
1785 
//// from http://www.opencores.org/lgpl.shtml                     ////
1786 
////                                                              ////
1787 
//////////////////////////////////////////////////////////////////////
1788 
 
1789 
// binary counter
1790 29 unneback 
 
1791 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1792 
module `BASE`MODULE (
1793 
`undef MODULE
1794 
 clear, cke, q, level1, level2, rst, clk);
1795 
 
1796 29 unneback 
   parameter length = 4;
1797 
   input clear;
1798 
   input cke;
1799 
   output [length:1] q;
1800 
   output reg level1;
1801 
   output reg level2;
1802 
   input rst;
1803 
   input clk;
1804 
 
1805 
   parameter clear_value = 0;
1806 
   parameter set_value = 1;
1807 30 unneback 
   parameter wrap_value = 15;
1808 
   parameter level1_value = 8;
1809 
   parameter level2_value = 15;
1810 29 unneback 
 
1811 
   wire rew;
1812 30 unneback 
   assign rew = 1'b0;
1813 29 unneback 
   reg  [length:1] qi;
1814 
   wire [length:1] q_next;
1815 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1816 
 
1817 
   always @ (posedge clk or posedge rst)
1818 
     if (rst)
1819 
       qi <= {length{1'b0}};
1820 
     else
1821 
     if (cke)
1822 
       qi <= q_next;
1823 
 
1824 
   assign q = qi;
1825 
 
1826 
 
1827 
    always @ (posedge clk or posedge rst)
1828 
    if (rst)
1829 
        level1 <= 1'b0;
1830 
    else
1831 
    if (cke)
1832 
    if (clear)
1833 
        level1 <= 1'b0;
1834 
    else if (q_next == level1_value)
1835 
        level1 <= 1'b1;
1836 
    else if (qi == level1_value & rew)
1837 
        level1 <= 1'b0;
1838 
 
1839 
    always @ (posedge clk or posedge rst)
1840 
    if (rst)
1841 
        level2 <= 1'b0;
1842 
    else
1843 
    if (cke)
1844 
    if (clear)
1845 
        level2 <= 1'b0;
1846 
    else if (q_next == level2_value)
1847 
        level2 <= 1'b1;
1848 
    else if (qi == level2_value & rew)
1849 
        level2 <= 1'b0;
1850 
endmodule
1851 40 unneback 
`endif
1852 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1853 29 unneback 
//////////////////////////////////////////////////////////////////////
1854 
////                                                              ////
1855 
////  Versatile counter                                           ////
1856 
////                                                              ////
1857 
////  Description                                                 ////
1858 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1859 
////  counter                                                     ////
1860 
////                                                              ////
1861 
////  To Do:                                                      ////
1862 
////   - add LFSR with more taps                                  ////
1863 
////                                                              ////
1864 
////  Author(s):                                                  ////
1865 
////      - Michael Unneback, unneback@opencores.org              ////
1866 
////        ORSoC AB                                              ////
1867 
////                                                              ////
1868 
//////////////////////////////////////////////////////////////////////
1869 
////                                                              ////
1870 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1871 
////                                                              ////
1872 
//// This source file may be used and distributed without         ////
1873 
//// restriction provided that this copyright statement is not    ////
1874 
//// removed from the file and that any derivative work contains  ////
1875 
//// the original copyright notice and the associated disclaimer. ////
1876 
////                                                              ////
1877 
//// This source file is free software; you can redistribute it   ////
1878 
//// and/or modify it under the terms of the GNU Lesser General   ////
1879 
//// Public License as published by the Free Software Foundation; ////
1880 
//// either version 2.1 of the License, or (at your option) any   ////
1881 
//// later version.                                               ////
1882 
////                                                              ////
1883 
//// This source is distributed in the hope that it will be       ////
1884 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1885 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1886 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1887 
//// details.                                                     ////
1888 
////                                                              ////
1889 
//// You should have received a copy of the GNU Lesser General    ////
1890 
//// Public License along with this source; if not, download it   ////
1891 
//// from http://www.opencores.org/lgpl.shtml                     ////
1892 
////                                                              ////
1893 
//////////////////////////////////////////////////////////////////////
1894 
 
1895 
// binary counter
1896 6 unneback 
 
1897 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1898 
module `BASE`MODULE (
1899 
`undef MODULE
1900 
 clear, set, cke, rew, q, rst, clk);
1901 
 
1902 6 unneback 
   parameter length = 4;
1903 
   input clear;
1904 
   input set;
1905 
   input cke;
1906 
   input rew;
1907 
   output [length:1] q;
1908 
   input rst;
1909 
   input clk;
1910 
 
1911 
   parameter clear_value = 0;
1912 
   parameter set_value = 1;
1913 
   parameter wrap_value = 0;
1914 
   parameter level1_value = 15;
1915 
 
1916 
   reg  [length:1] qi;
1917 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1918 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1919 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1920 
   assign q_next = rew ? q_next_rew : q_next_fw;
1921 
 
1922 
   always @ (posedge clk or posedge rst)
1923 
     if (rst)
1924 
       qi <= {length{1'b0}};
1925 
     else
1926 
     if (cke)
1927 
       qi <= q_next;
1928 
 
1929 
   assign q = qi;
1930 
 
1931 
endmodule
1932 40 unneback 
`endif
1933 
`ifdef CNT_BIN_CE_REW_L1
1934 6 unneback 
//////////////////////////////////////////////////////////////////////
1935 
////                                                              ////
1936 
////  Versatile counter                                           ////
1937 
////                                                              ////
1938 
////  Description                                                 ////
1939 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1940 
////  counter                                                     ////
1941 
////                                                              ////
1942 
////  To Do:                                                      ////
1943 
////   - add LFSR with more taps                                  ////
1944 
////                                                              ////
1945 
////  Author(s):                                                  ////
1946 
////      - Michael Unneback, unneback@opencores.org              ////
1947 
////        ORSoC AB                                              ////
1948 
////                                                              ////
1949 
//////////////////////////////////////////////////////////////////////
1950 
////                                                              ////
1951 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1952 
////                                                              ////
1953 
//// This source file may be used and distributed without         ////
1954 
//// restriction provided that this copyright statement is not    ////
1955 
//// removed from the file and that any derivative work contains  ////
1956 
//// the original copyright notice and the associated disclaimer. ////
1957 
////                                                              ////
1958 
//// This source file is free software; you can redistribute it   ////
1959 
//// and/or modify it under the terms of the GNU Lesser General   ////
1960 
//// Public License as published by the Free Software Foundation; ////
1961 
//// either version 2.1 of the License, or (at your option) any   ////
1962 
//// later version.                                               ////
1963 
////                                                              ////
1964 
//// This source is distributed in the hope that it will be       ////
1965 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1966 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1967 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1968 
//// details.                                                     ////
1969 
////                                                              ////
1970 
//// You should have received a copy of the GNU Lesser General    ////
1971 
//// Public License along with this source; if not, download it   ////
1972 
//// from http://www.opencores.org/lgpl.shtml                     ////
1973 
////                                                              ////
1974 
//////////////////////////////////////////////////////////////////////
1975 
 
1976 
// binary counter
1977 
 
1978 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
1979 
module `BASE`MODULE (
1980 
`undef MODULE
1981 
 cke, rew, level1, rst, clk);
1982 
 
1983 6 unneback 
   parameter length = 4;
1984 
   input cke;
1985 
   input rew;
1986 
   output reg level1;
1987 
   input rst;
1988 
   input clk;
1989 
 
1990 
   parameter clear_value = 0;
1991 
   parameter set_value = 1;
1992 
   parameter wrap_value = 1;
1993 
   parameter level1_value = 15;
1994 
 
1995 29 unneback 
   wire clear;
1996 30 unneback 
   assign clear = 1'b0;
1997 6 unneback 
   reg  [length:1] qi;
1998 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1999 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2000 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2001 
   assign q_next = rew ? q_next_rew : q_next_fw;
2002 
 
2003 
   always @ (posedge clk or posedge rst)
2004 
     if (rst)
2005 
       qi <= {length{1'b0}};
2006 
     else
2007 
     if (cke)
2008 
       qi <= q_next;
2009 
 
2010 
 
2011 
 
2012 
    always @ (posedge clk or posedge rst)
2013 
    if (rst)
2014 
        level1 <= 1'b0;
2015 
    else
2016 
    if (cke)
2017 29 unneback 
    if (clear)
2018 
        level1 <= 1'b0;
2019 
    else if (q_next == level1_value)
2020 6 unneback 
        level1 <= 1'b1;
2021 
    else if (qi == level1_value & rew)
2022 
        level1 <= 1'b0;
2023 
endmodule
2024 40 unneback 
`endif
2025 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2026 6 unneback 
//////////////////////////////////////////////////////////////////////
2027 
////                                                              ////
2028 
////  Versatile counter                                           ////
2029 
////                                                              ////
2030 
////  Description                                                 ////
2031 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2032 
////  counter                                                     ////
2033 
////                                                              ////
2034 
////  To Do:                                                      ////
2035 
////   - add LFSR with more taps                                  ////
2036 
////                                                              ////
2037 
////  Author(s):                                                  ////
2038 
////      - Michael Unneback, unneback@opencores.org              ////
2039 
////        ORSoC AB                                              ////
2040 
////                                                              ////
2041 
//////////////////////////////////////////////////////////////////////
2042 
////                                                              ////
2043 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2044 
////                                                              ////
2045 
//// This source file may be used and distributed without         ////
2046 
//// restriction provided that this copyright statement is not    ////
2047 
//// removed from the file and that any derivative work contains  ////
2048 
//// the original copyright notice and the associated disclaimer. ////
2049 
////                                                              ////
2050 
//// This source file is free software; you can redistribute it   ////
2051 
//// and/or modify it under the terms of the GNU Lesser General   ////
2052 
//// Public License as published by the Free Software Foundation; ////
2053 
//// either version 2.1 of the License, or (at your option) any   ////
2054 
//// later version.                                               ////
2055 
////                                                              ////
2056 
//// This source is distributed in the hope that it will be       ////
2057 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2058 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2059 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2060 
//// details.                                                     ////
2061 
////                                                              ////
2062 
//// You should have received a copy of the GNU Lesser General    ////
2063 
//// Public License along with this source; if not, download it   ////
2064 
//// from http://www.opencores.org/lgpl.shtml                     ////
2065 
////                                                              ////
2066 
//////////////////////////////////////////////////////////////////////
2067 
 
2068 25 unneback 
// binary counter
2069 
 
2070 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2071 
module `BASE`MODULE (
2072 
`undef MODULE
2073 
 cke, rew, zq, level1, rst, clk);
2074 
 
2075 25 unneback 
   parameter length = 4;
2076 
   input cke;
2077 
   input rew;
2078 
   output reg zq;
2079 
   output reg level1;
2080 
   input rst;
2081 
   input clk;
2082 
 
2083 
   parameter clear_value = 0;
2084 
   parameter set_value = 1;
2085 
   parameter wrap_value = 1;
2086 
   parameter level1_value = 15;
2087 
 
2088 29 unneback 
   wire clear;
2089 30 unneback 
   assign clear = 1'b0;
2090 25 unneback 
   reg  [length:1] qi;
2091 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2092 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2093 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2094 
   assign q_next = rew ? q_next_rew : q_next_fw;
2095 
 
2096 
   always @ (posedge clk or posedge rst)
2097 
     if (rst)
2098 
       qi <= {length{1'b0}};
2099 
     else
2100 
     if (cke)
2101 
       qi <= q_next;
2102 
 
2103 
 
2104 
 
2105 
   always @ (posedge clk or posedge rst)
2106 
     if (rst)
2107 
       zq <= 1'b1;
2108 
     else
2109 
     if (cke)
2110 
       zq <= q_next == {length{1'b0}};
2111 
 
2112 
    always @ (posedge clk or posedge rst)
2113 
    if (rst)
2114 
        level1 <= 1'b0;
2115 
    else
2116 
    if (cke)
2117 29 unneback 
    if (clear)
2118 
        level1 <= 1'b0;
2119 
    else if (q_next == level1_value)
2120 25 unneback 
        level1 <= 1'b1;
2121 
    else if (qi == level1_value & rew)
2122 
        level1 <= 1'b0;
2123 
endmodule
2124 40 unneback 
`endif
2125 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2126 25 unneback 
//////////////////////////////////////////////////////////////////////
2127 
////                                                              ////
2128 
////  Versatile counter                                           ////
2129 
////                                                              ////
2130 
////  Description                                                 ////
2131 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2132 
////  counter                                                     ////
2133 
////                                                              ////
2134 
////  To Do:                                                      ////
2135 
////   - add LFSR with more taps                                  ////
2136 
////                                                              ////
2137 
////  Author(s):                                                  ////
2138 
////      - Michael Unneback, unneback@opencores.org              ////
2139 
////        ORSoC AB                                              ////
2140 
////                                                              ////
2141 
//////////////////////////////////////////////////////////////////////
2142 
////                                                              ////
2143 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2144 
////                                                              ////
2145 
//// This source file may be used and distributed without         ////
2146 
//// restriction provided that this copyright statement is not    ////
2147 
//// removed from the file and that any derivative work contains  ////
2148 
//// the original copyright notice and the associated disclaimer. ////
2149 
////                                                              ////
2150 
//// This source file is free software; you can redistribute it   ////
2151 
//// and/or modify it under the terms of the GNU Lesser General   ////
2152 
//// Public License as published by the Free Software Foundation; ////
2153 
//// either version 2.1 of the License, or (at your option) any   ////
2154 
//// later version.                                               ////
2155 
////                                                              ////
2156 
//// This source is distributed in the hope that it will be       ////
2157 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2158 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2159 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2160 
//// details.                                                     ////
2161 
////                                                              ////
2162 
//// You should have received a copy of the GNU Lesser General    ////
2163 
//// Public License along with this source; if not, download it   ////
2164 
//// from http://www.opencores.org/lgpl.shtml                     ////
2165 
////                                                              ////
2166 
//////////////////////////////////////////////////////////////////////
2167 
 
2168 
// binary counter
2169 
 
2170 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2171 
module `BASE`MODULE (
2172 
`undef MODULE
2173 
 cke, rew, q, zq, level1, rst, clk);
2174 
 
2175 25 unneback 
   parameter length = 4;
2176 
   input cke;
2177 
   input rew;
2178 
   output [length:1] q;
2179 
   output reg zq;
2180 
   output reg level1;
2181 
   input rst;
2182 
   input clk;
2183 
 
2184 
   parameter clear_value = 0;
2185 
   parameter set_value = 1;
2186 
   parameter wrap_value = 1;
2187 
   parameter level1_value = 15;
2188 
 
2189 29 unneback 
   wire clear;
2190 30 unneback 
   assign clear = 1'b0;
2191 25 unneback 
   reg  [length:1] qi;
2192 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2193 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2194 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2195 
   assign q_next = rew ? q_next_rew : q_next_fw;
2196 
 
2197 
   always @ (posedge clk or posedge rst)
2198 
     if (rst)
2199 
       qi <= {length{1'b0}};
2200 
     else
2201 
     if (cke)
2202 
       qi <= q_next;
2203 
 
2204 
   assign q = qi;
2205 
 
2206 
 
2207 
   always @ (posedge clk or posedge rst)
2208 
     if (rst)
2209 
       zq <= 1'b1;
2210 
     else
2211 
     if (cke)
2212 
       zq <= q_next == {length{1'b0}};
2213 
 
2214 
    always @ (posedge clk or posedge rst)
2215 
    if (rst)
2216 
        level1 <= 1'b0;
2217 
    else
2218 
    if (cke)
2219 29 unneback 
    if (clear)
2220 
        level1 <= 1'b0;
2221 
    else if (q_next == level1_value)
2222 25 unneback 
        level1 <= 1'b1;
2223 
    else if (qi == level1_value & rew)
2224 
        level1 <= 1'b0;
2225 
endmodule
2226 40 unneback 
`endif
2227 
`ifdef CNT_LFSR_ZQ
2228 25 unneback 
//////////////////////////////////////////////////////////////////////
2229 
////                                                              ////
2230 
////  Versatile counter                                           ////
2231 
////                                                              ////
2232 
////  Description                                                 ////
2233 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2234 
////  counter                                                     ////
2235 
////                                                              ////
2236 
////  To Do:                                                      ////
2237 
////   - add LFSR with more taps                                  ////
2238 
////                                                              ////
2239 
////  Author(s):                                                  ////
2240 
////      - Michael Unneback, unneback@opencores.org              ////
2241 
////        ORSoC AB                                              ////
2242 
////                                                              ////
2243 
//////////////////////////////////////////////////////////////////////
2244 
////                                                              ////
2245 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2246 
////                                                              ////
2247 
//// This source file may be used and distributed without         ////
2248 
//// restriction provided that this copyright statement is not    ////
2249 
//// removed from the file and that any derivative work contains  ////
2250 
//// the original copyright notice and the associated disclaimer. ////
2251 
////                                                              ////
2252 
//// This source file is free software; you can redistribute it   ////
2253 
//// and/or modify it under the terms of the GNU Lesser General   ////
2254 
//// Public License as published by the Free Software Foundation; ////
2255 
//// either version 2.1 of the License, or (at your option) any   ////
2256 
//// later version.                                               ////
2257 
////                                                              ////
2258 
//// This source is distributed in the hope that it will be       ////
2259 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2260 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2261 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2262 
//// details.                                                     ////
2263 
////                                                              ////
2264 
//// You should have received a copy of the GNU Lesser General    ////
2265 
//// Public License along with this source; if not, download it   ////
2266 
//// from http://www.opencores.org/lgpl.shtml                     ////
2267 
////                                                              ////
2268 
//////////////////////////////////////////////////////////////////////
2269 
 
2270 6 unneback 
// LFSR counter
2271 
 
2272 40 unneback 
`define MODULE cnt_lfsr_zq
2273 
module `BASE`MODULE (
2274 
`undef MODULE
2275 
 zq, rst, clk);
2276 
 
2277 6 unneback 
   parameter length = 4;
2278 
   output reg zq;
2279 
   input rst;
2280 
   input clk;
2281 
 
2282 
   parameter clear_value = 0;
2283 
   parameter set_value = 1;
2284 
   parameter wrap_value = 8;
2285 
   parameter level1_value = 15;
2286 
 
2287 
   reg  [length:1] qi;
2288 
   reg lfsr_fb;
2289 
   wire [length:1] q_next;
2290 
   reg [32:1] polynom;
2291 
   integer i;
2292 
 
2293 
   always @ (qi)
2294 
   begin
2295 
        case (length)
2296 
         2: polynom = 32'b11;                               // 0x3
2297 
         3: polynom = 32'b110;                              // 0x6
2298 
         4: polynom = 32'b1100;                             // 0xC
2299 
         5: polynom = 32'b10100;                            // 0x14
2300 
         6: polynom = 32'b110000;                           // 0x30
2301 
         7: polynom = 32'b1100000;                          // 0x60
2302 
         8: polynom = 32'b10111000;                         // 0xb8
2303 
         9: polynom = 32'b100010000;                        // 0x110
2304 
        10: polynom = 32'b1001000000;                       // 0x240
2305 
        11: polynom = 32'b10100000000;                      // 0x500
2306 
        12: polynom = 32'b100000101001;                     // 0x829
2307 
        13: polynom = 32'b1000000001100;                    // 0x100C
2308 
        14: polynom = 32'b10000000010101;                   // 0x2015
2309 
        15: polynom = 32'b110000000000000;                  // 0x6000
2310 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2311 
        17: polynom = 32'b10010000000000000;                // 0x12000
2312 
        18: polynom = 32'b100000010000000000;               // 0x20400
2313 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2314 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2315 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2316 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2317 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2318 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2319 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2320 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2321 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2322 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2323 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2324 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2325 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2326 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2327 
        default: polynom = 32'b0;
2328 
        endcase
2329 
        lfsr_fb = qi[length];
2330 
        for (i=length-1; i>=1; i=i-1) begin
2331 
            if (polynom[i])
2332 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2333 
        end
2334 
    end
2335 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2336 
 
2337 
   always @ (posedge clk or posedge rst)
2338 
     if (rst)
2339 
       qi <= {length{1'b0}};
2340 
     else
2341 
       qi <= q_next;
2342 
 
2343 
 
2344 
 
2345 
   always @ (posedge clk or posedge rst)
2346 
     if (rst)
2347 
       zq <= 1'b1;
2348 
     else
2349 
       zq <= q_next == {length{1'b0}};
2350 
endmodule
2351 40 unneback 
`endif
2352 
`ifdef CNT_LFSR_CE_ZQ
2353 6 unneback 
//////////////////////////////////////////////////////////////////////
2354 
////                                                              ////
2355 
////  Versatile counter                                           ////
2356 
////                                                              ////
2357 
////  Description                                                 ////
2358 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2359 
////  counter                                                     ////
2360 
////                                                              ////
2361 
////  To Do:                                                      ////
2362 
////   - add LFSR with more taps                                  ////
2363 
////                                                              ////
2364 
////  Author(s):                                                  ////
2365 
////      - Michael Unneback, unneback@opencores.org              ////
2366 
////        ORSoC AB                                              ////
2367 
////                                                              ////
2368 
//////////////////////////////////////////////////////////////////////
2369 
////                                                              ////
2370 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2371 
////                                                              ////
2372 
//// This source file may be used and distributed without         ////
2373 
//// restriction provided that this copyright statement is not    ////
2374 
//// removed from the file and that any derivative work contains  ////
2375 
//// the original copyright notice and the associated disclaimer. ////
2376 
////                                                              ////
2377 
//// This source file is free software; you can redistribute it   ////
2378 
//// and/or modify it under the terms of the GNU Lesser General   ////
2379 
//// Public License as published by the Free Software Foundation; ////
2380 
//// either version 2.1 of the License, or (at your option) any   ////
2381 
//// later version.                                               ////
2382 
////                                                              ////
2383 
//// This source is distributed in the hope that it will be       ////
2384 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2385 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2386 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2387 
//// details.                                                     ////
2388 
////                                                              ////
2389 
//// You should have received a copy of the GNU Lesser General    ////
2390 
//// Public License along with this source; if not, download it   ////
2391 
//// from http://www.opencores.org/lgpl.shtml                     ////
2392 
////                                                              ////
2393 
//////////////////////////////////////////////////////////////////////
2394 
 
2395 
// LFSR counter
2396 
 
2397 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2398 
module `BASE`MODULE (
2399 
`undef MODULE
2400 
 cke, zq, rst, clk);
2401 
 
2402 6 unneback 
   parameter length = 4;
2403 
   input cke;
2404 
   output reg zq;
2405 
   input rst;
2406 
   input clk;
2407 
 
2408 
   parameter clear_value = 0;
2409 
   parameter set_value = 1;
2410 
   parameter wrap_value = 8;
2411 
   parameter level1_value = 15;
2412 
 
2413 
   reg  [length:1] qi;
2414 
   reg lfsr_fb;
2415 
   wire [length:1] q_next;
2416 
   reg [32:1] polynom;
2417 
   integer i;
2418 
 
2419 
   always @ (qi)
2420 
   begin
2421 
        case (length)
2422 
         2: polynom = 32'b11;                               // 0x3
2423 
         3: polynom = 32'b110;                              // 0x6
2424 
         4: polynom = 32'b1100;                             // 0xC
2425 
         5: polynom = 32'b10100;                            // 0x14
2426 
         6: polynom = 32'b110000;                           // 0x30
2427 
         7: polynom = 32'b1100000;                          // 0x60
2428 
         8: polynom = 32'b10111000;                         // 0xb8
2429 
         9: polynom = 32'b100010000;                        // 0x110
2430 
        10: polynom = 32'b1001000000;                       // 0x240
2431 
        11: polynom = 32'b10100000000;                      // 0x500
2432 
        12: polynom = 32'b100000101001;                     // 0x829
2433 
        13: polynom = 32'b1000000001100;                    // 0x100C
2434 
        14: polynom = 32'b10000000010101;                   // 0x2015
2435 
        15: polynom = 32'b110000000000000;                  // 0x6000
2436 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2437 
        17: polynom = 32'b10010000000000000;                // 0x12000
2438 
        18: polynom = 32'b100000010000000000;               // 0x20400
2439 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2440 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2441 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2442 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2443 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2444 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2445 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2446 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2447 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2448 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2449 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2450 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2451 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2452 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2453 
        default: polynom = 32'b0;
2454 
        endcase
2455 
        lfsr_fb = qi[length];
2456 
        for (i=length-1; i>=1; i=i-1) begin
2457 
            if (polynom[i])
2458 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2459 
        end
2460 
    end
2461 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2462 
 
2463 
   always @ (posedge clk or posedge rst)
2464 
     if (rst)
2465 
       qi <= {length{1'b0}};
2466 
     else
2467 
     if (cke)
2468 
       qi <= q_next;
2469 
 
2470 
 
2471 
 
2472 
   always @ (posedge clk or posedge rst)
2473 
     if (rst)
2474 
       zq <= 1'b1;
2475 
     else
2476 
     if (cke)
2477 
       zq <= q_next == {length{1'b0}};
2478 
endmodule
2479 40 unneback 
`endif
2480 
`ifdef CNT_LFSR_CE_Q
2481 6 unneback 
//////////////////////////////////////////////////////////////////////
2482 
////                                                              ////
2483 
////  Versatile counter                                           ////
2484 
////                                                              ////
2485 
////  Description                                                 ////
2486 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2487 
////  counter                                                     ////
2488 
////                                                              ////
2489 
////  To Do:                                                      ////
2490 
////   - add LFSR with more taps                                  ////
2491 
////                                                              ////
2492 
////  Author(s):                                                  ////
2493 
////      - Michael Unneback, unneback@opencores.org              ////
2494 
////        ORSoC AB                                              ////
2495 
////                                                              ////
2496 
//////////////////////////////////////////////////////////////////////
2497 
////                                                              ////
2498 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2499 
////                                                              ////
2500 
//// This source file may be used and distributed without         ////
2501 
//// restriction provided that this copyright statement is not    ////
2502 
//// removed from the file and that any derivative work contains  ////
2503 
//// the original copyright notice and the associated disclaimer. ////
2504 
////                                                              ////
2505 
//// This source file is free software; you can redistribute it   ////
2506 
//// and/or modify it under the terms of the GNU Lesser General   ////
2507 
//// Public License as published by the Free Software Foundation; ////
2508 
//// either version 2.1 of the License, or (at your option) any   ////
2509 
//// later version.                                               ////
2510 
////                                                              ////
2511 
//// This source is distributed in the hope that it will be       ////
2512 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2513 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2514 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2515 
//// details.                                                     ////
2516 
////                                                              ////
2517 
//// You should have received a copy of the GNU Lesser General    ////
2518 
//// Public License along with this source; if not, download it   ////
2519 
//// from http://www.opencores.org/lgpl.shtml                     ////
2520 
////                                                              ////
2521 
//////////////////////////////////////////////////////////////////////
2522 22 unneback 
 
2523 
// LFSR counter
2524 27 unneback 
 
2525 40 unneback 
`define MODULE cnt_lfsr_ce_q
2526 
module `BASE`MODULE (
2527 
`undef MODULE
2528 
 cke, q, rst, clk);
2529 
 
2530 27 unneback 
   parameter length = 4;
2531 
   input cke;
2532 
   output [length:1] q;
2533 
   input rst;
2534 
   input clk;
2535 
 
2536 
   parameter clear_value = 0;
2537 
   parameter set_value = 1;
2538 
   parameter wrap_value = 8;
2539 
   parameter level1_value = 15;
2540 
 
2541 
   reg  [length:1] qi;
2542 
   reg lfsr_fb;
2543 
   wire [length:1] q_next;
2544 
   reg [32:1] polynom;
2545 
   integer i;
2546 
 
2547 
   always @ (qi)
2548 
   begin
2549 
        case (length)
2550 
         2: polynom = 32'b11;                               // 0x3
2551 
         3: polynom = 32'b110;                              // 0x6
2552 
         4: polynom = 32'b1100;                             // 0xC
2553 
         5: polynom = 32'b10100;                            // 0x14
2554 
         6: polynom = 32'b110000;                           // 0x30
2555 
         7: polynom = 32'b1100000;                          // 0x60
2556 
         8: polynom = 32'b10111000;                         // 0xb8
2557 
         9: polynom = 32'b100010000;                        // 0x110
2558 
        10: polynom = 32'b1001000000;                       // 0x240
2559 
        11: polynom = 32'b10100000000;                      // 0x500
2560 
        12: polynom = 32'b100000101001;                     // 0x829
2561 
        13: polynom = 32'b1000000001100;                    // 0x100C
2562 
        14: polynom = 32'b10000000010101;                   // 0x2015
2563 
        15: polynom = 32'b110000000000000;                  // 0x6000
2564 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2565 
        17: polynom = 32'b10010000000000000;                // 0x12000
2566 
        18: polynom = 32'b100000010000000000;               // 0x20400
2567 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2568 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2569 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2570 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2571 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2572 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2573 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2574 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2575 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2576 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2577 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2578 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2579 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2580 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2581 
        default: polynom = 32'b0;
2582 
        endcase
2583 
        lfsr_fb = qi[length];
2584 
        for (i=length-1; i>=1; i=i-1) begin
2585 
            if (polynom[i])
2586 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2587 
        end
2588 
    end
2589 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2590 
 
2591 
   always @ (posedge clk or posedge rst)
2592 
     if (rst)
2593 
       qi <= {length{1'b0}};
2594 
     else
2595 
     if (cke)
2596 
       qi <= q_next;
2597 
 
2598 
   assign q = qi;
2599 
 
2600 
endmodule
2601 40 unneback 
`endif
2602 
`ifdef CNT_LFSR_CE_CLEAR_Q
2603 27 unneback 
//////////////////////////////////////////////////////////////////////
2604 
////                                                              ////
2605 
////  Versatile counter                                           ////
2606 
////                                                              ////
2607 
////  Description                                                 ////
2608 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2609 
////  counter                                                     ////
2610 
////                                                              ////
2611 
////  To Do:                                                      ////
2612 
////   - add LFSR with more taps                                  ////
2613 
////                                                              ////
2614 
////  Author(s):                                                  ////
2615 
////      - Michael Unneback, unneback@opencores.org              ////
2616 
////        ORSoC AB                                              ////
2617 
////                                                              ////
2618 
//////////////////////////////////////////////////////////////////////
2619 
////                                                              ////
2620 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2621 
////                                                              ////
2622 
//// This source file may be used and distributed without         ////
2623 
//// restriction provided that this copyright statement is not    ////
2624 
//// removed from the file and that any derivative work contains  ////
2625 
//// the original copyright notice and the associated disclaimer. ////
2626 
////                                                              ////
2627 
//// This source file is free software; you can redistribute it   ////
2628 
//// and/or modify it under the terms of the GNU Lesser General   ////
2629 
//// Public License as published by the Free Software Foundation; ////
2630 
//// either version 2.1 of the License, or (at your option) any   ////
2631 
//// later version.                                               ////
2632 
////                                                              ////
2633 
//// This source is distributed in the hope that it will be       ////
2634 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2635 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2636 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2637 
//// details.                                                     ////
2638 
////                                                              ////
2639 
//// You should have received a copy of the GNU Lesser General    ////
2640 
//// Public License along with this source; if not, download it   ////
2641 
//// from http://www.opencores.org/lgpl.shtml                     ////
2642 
////                                                              ////
2643 
//////////////////////////////////////////////////////////////////////
2644 
 
2645 
// LFSR counter
2646 
 
2647 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2648 
module `BASE`MODULE (
2649 
`undef MODULE
2650 
 clear, cke, q, rst, clk);
2651 
 
2652 27 unneback 
   parameter length = 4;
2653 
   input clear;
2654 
   input cke;
2655 
   output [length:1] q;
2656 
   input rst;
2657 
   input clk;
2658 
 
2659 
   parameter clear_value = 0;
2660 
   parameter set_value = 1;
2661 
   parameter wrap_value = 8;
2662 
   parameter level1_value = 15;
2663 
 
2664 
   reg  [length:1] qi;
2665 
   reg lfsr_fb;
2666 
   wire [length:1] q_next;
2667 
   reg [32:1] polynom;
2668 
   integer i;
2669 
 
2670 
   always @ (qi)
2671 
   begin
2672 
        case (length)
2673 
         2: polynom = 32'b11;                               // 0x3
2674 
         3: polynom = 32'b110;                              // 0x6
2675 
         4: polynom = 32'b1100;                             // 0xC
2676 
         5: polynom = 32'b10100;                            // 0x14
2677 
         6: polynom = 32'b110000;                           // 0x30
2678 
         7: polynom = 32'b1100000;                          // 0x60
2679 
         8: polynom = 32'b10111000;                         // 0xb8
2680 
         9: polynom = 32'b100010000;                        // 0x110
2681 
        10: polynom = 32'b1001000000;                       // 0x240
2682 
        11: polynom = 32'b10100000000;                      // 0x500
2683 
        12: polynom = 32'b100000101001;                     // 0x829
2684 
        13: polynom = 32'b1000000001100;                    // 0x100C
2685 
        14: polynom = 32'b10000000010101;                   // 0x2015
2686 
        15: polynom = 32'b110000000000000;                  // 0x6000
2687 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2688 
        17: polynom = 32'b10010000000000000;                // 0x12000
2689 
        18: polynom = 32'b100000010000000000;               // 0x20400
2690 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2691 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2692 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2693 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2694 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2695 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2696 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2697 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2698 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2699 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2700 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2701 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2702 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2703 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2704 
        default: polynom = 32'b0;
2705 
        endcase
2706 
        lfsr_fb = qi[length];
2707 
        for (i=length-1; i>=1; i=i-1) begin
2708 
            if (polynom[i])
2709 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2710 
        end
2711 
    end
2712 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2713 
 
2714 
   always @ (posedge clk or posedge rst)
2715 
     if (rst)
2716 
       qi <= {length{1'b0}};
2717 
     else
2718 
     if (cke)
2719 
       qi <= q_next;
2720 
 
2721 
   assign q = qi;
2722 
 
2723 
endmodule
2724 40 unneback 
`endif
2725 
`ifdef CNT_LFSR_CE_Q_ZQ
2726 27 unneback 
//////////////////////////////////////////////////////////////////////
2727 
////                                                              ////
2728 
////  Versatile counter                                           ////
2729 
////                                                              ////
2730 
////  Description                                                 ////
2731 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2732 
////  counter                                                     ////
2733 
////                                                              ////
2734 
////  To Do:                                                      ////
2735 
////   - add LFSR with more taps                                  ////
2736 
////                                                              ////
2737 
////  Author(s):                                                  ////
2738 
////      - Michael Unneback, unneback@opencores.org              ////
2739 
////        ORSoC AB                                              ////
2740 
////                                                              ////
2741 
//////////////////////////////////////////////////////////////////////
2742 
////                                                              ////
2743 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2744 
////                                                              ////
2745 
//// This source file may be used and distributed without         ////
2746 
//// restriction provided that this copyright statement is not    ////
2747 
//// removed from the file and that any derivative work contains  ////
2748 
//// the original copyright notice and the associated disclaimer. ////
2749 
////                                                              ////
2750 
//// This source file is free software; you can redistribute it   ////
2751 
//// and/or modify it under the terms of the GNU Lesser General   ////
2752 
//// Public License as published by the Free Software Foundation; ////
2753 
//// either version 2.1 of the License, or (at your option) any   ////
2754 
//// later version.                                               ////
2755 
////                                                              ////
2756 
//// This source is distributed in the hope that it will be       ////
2757 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2758 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2759 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2760 
//// details.                                                     ////
2761 
////                                                              ////
2762 
//// You should have received a copy of the GNU Lesser General    ////
2763 
//// Public License along with this source; if not, download it   ////
2764 
//// from http://www.opencores.org/lgpl.shtml                     ////
2765 
////                                                              ////
2766 
//////////////////////////////////////////////////////////////////////
2767 
 
2768 
// LFSR counter
2769 22 unneback 
 
2770 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2771 
module `BASE`MODULE (
2772 
`undef MODULE
2773 
 cke, q, zq, rst, clk);
2774 
 
2775 22 unneback 
   parameter length = 4;
2776 
   input cke;
2777 
   output [length:1] q;
2778 
   output reg zq;
2779 
   input rst;
2780 
   input clk;
2781 
 
2782 
   parameter clear_value = 0;
2783 
   parameter set_value = 1;
2784 
   parameter wrap_value = 8;
2785 
   parameter level1_value = 15;
2786 
 
2787 
   reg  [length:1] qi;
2788 
   reg lfsr_fb;
2789 
   wire [length:1] q_next;
2790 
   reg [32:1] polynom;
2791 
   integer i;
2792 
 
2793 
   always @ (qi)
2794 
   begin
2795 
        case (length)
2796 
         2: polynom = 32'b11;                               // 0x3
2797 
         3: polynom = 32'b110;                              // 0x6
2798 
         4: polynom = 32'b1100;                             // 0xC
2799 
         5: polynom = 32'b10100;                            // 0x14
2800 
         6: polynom = 32'b110000;                           // 0x30
2801 
         7: polynom = 32'b1100000;                          // 0x60
2802 
         8: polynom = 32'b10111000;                         // 0xb8
2803 
         9: polynom = 32'b100010000;                        // 0x110
2804 
        10: polynom = 32'b1001000000;                       // 0x240
2805 
        11: polynom = 32'b10100000000;                      // 0x500
2806 
        12: polynom = 32'b100000101001;                     // 0x829
2807 
        13: polynom = 32'b1000000001100;                    // 0x100C
2808 
        14: polynom = 32'b10000000010101;                   // 0x2015
2809 
        15: polynom = 32'b110000000000000;                  // 0x6000
2810 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2811 
        17: polynom = 32'b10010000000000000;                // 0x12000
2812 
        18: polynom = 32'b100000010000000000;               // 0x20400
2813 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2814 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2815 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2816 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2817 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2818 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2819 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2820 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2821 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2822 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2823 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2824 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2825 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2826 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2827 
        default: polynom = 32'b0;
2828 
        endcase
2829 
        lfsr_fb = qi[length];
2830 
        for (i=length-1; i>=1; i=i-1) begin
2831 
            if (polynom[i])
2832 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2833 
        end
2834 
    end
2835 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2836 
 
2837 
   always @ (posedge clk or posedge rst)
2838 
     if (rst)
2839 
       qi <= {length{1'b0}};
2840 
     else
2841 
     if (cke)
2842 
       qi <= q_next;
2843 
 
2844 
   assign q = qi;
2845 
 
2846 
 
2847 
   always @ (posedge clk or posedge rst)
2848 
     if (rst)
2849 
       zq <= 1'b1;
2850 
     else
2851 
     if (cke)
2852 
       zq <= q_next == {length{1'b0}};
2853 
endmodule
2854 40 unneback 
`endif
2855 
`ifdef CNT_LFSR_CE_REW_L1
2856 22 unneback 
//////////////////////////////////////////////////////////////////////
2857 
////                                                              ////
2858 
////  Versatile counter                                           ////
2859 
////                                                              ////
2860 
////  Description                                                 ////
2861 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2862 
////  counter                                                     ////
2863 
////                                                              ////
2864 
////  To Do:                                                      ////
2865 
////   - add LFSR with more taps                                  ////
2866 
////                                                              ////
2867 
////  Author(s):                                                  ////
2868 
////      - Michael Unneback, unneback@opencores.org              ////
2869 
////        ORSoC AB                                              ////
2870 
////                                                              ////
2871 
//////////////////////////////////////////////////////////////////////
2872 
////                                                              ////
2873 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2874 
////                                                              ////
2875 
//// This source file may be used and distributed without         ////
2876 
//// restriction provided that this copyright statement is not    ////
2877 
//// removed from the file and that any derivative work contains  ////
2878 
//// the original copyright notice and the associated disclaimer. ////
2879 
////                                                              ////
2880 
//// This source file is free software; you can redistribute it   ////
2881 
//// and/or modify it under the terms of the GNU Lesser General   ////
2882 
//// Public License as published by the Free Software Foundation; ////
2883 
//// either version 2.1 of the License, or (at your option) any   ////
2884 
//// later version.                                               ////
2885 
////                                                              ////
2886 
//// This source is distributed in the hope that it will be       ////
2887 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2888 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2889 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2890 
//// details.                                                     ////
2891 
////                                                              ////
2892 
//// You should have received a copy of the GNU Lesser General    ////
2893 
//// Public License along with this source; if not, download it   ////
2894 
//// from http://www.opencores.org/lgpl.shtml                     ////
2895 
////                                                              ////
2896 
//////////////////////////////////////////////////////////////////////
2897 6 unneback 
 
2898 
// LFSR counter
2899 
 
2900 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
2901 
module `BASE`MODULE (
2902 
`undef MODULE
2903 
 cke, rew, level1, rst, clk);
2904 
 
2905 6 unneback 
   parameter length = 4;
2906 
   input cke;
2907 
   input rew;
2908 
   output reg level1;
2909 
   input rst;
2910 
   input clk;
2911 
 
2912 
   parameter clear_value = 0;
2913 
   parameter set_value = 1;
2914 
   parameter wrap_value = 8;
2915 
   parameter level1_value = 15;
2916 
 
2917 29 unneback 
   wire clear;
2918 30 unneback 
   assign clear = 1'b0;
2919 6 unneback 
   reg  [length:1] qi;
2920 
   reg lfsr_fb, lfsr_fb_rew;
2921 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2922 
   reg [32:1] polynom_rew;
2923 
   integer j;
2924 
   reg [32:1] polynom;
2925 
   integer i;
2926 
 
2927 
   always @ (qi)
2928 
   begin
2929 
        case (length)
2930 
         2: polynom = 32'b11;                               // 0x3
2931 
         3: polynom = 32'b110;                              // 0x6
2932 
         4: polynom = 32'b1100;                             // 0xC
2933 
         5: polynom = 32'b10100;                            // 0x14
2934 
         6: polynom = 32'b110000;                           // 0x30
2935 
         7: polynom = 32'b1100000;                          // 0x60
2936 
         8: polynom = 32'b10111000;                         // 0xb8
2937 
         9: polynom = 32'b100010000;                        // 0x110
2938 
        10: polynom = 32'b1001000000;                       // 0x240
2939 
        11: polynom = 32'b10100000000;                      // 0x500
2940 
        12: polynom = 32'b100000101001;                     // 0x829
2941 
        13: polynom = 32'b1000000001100;                    // 0x100C
2942 
        14: polynom = 32'b10000000010101;                   // 0x2015
2943 
        15: polynom = 32'b110000000000000;                  // 0x6000
2944 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2945 
        17: polynom = 32'b10010000000000000;                // 0x12000
2946 
        18: polynom = 32'b100000010000000000;               // 0x20400
2947 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2948 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2949 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2950 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2951 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2952 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2953 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2954 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2955 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2956 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2957 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2958 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2959 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2960 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2961 
        default: polynom = 32'b0;
2962 
        endcase
2963 
        lfsr_fb = qi[length];
2964 
        for (i=length-1; i>=1; i=i-1) begin
2965 
            if (polynom[i])
2966 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2967 
        end
2968 
    end
2969 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2970 
   always @ (qi)
2971 
   begin
2972 
        case (length)
2973 
         2: polynom_rew = 32'b11;
2974 
         3: polynom_rew = 32'b110;
2975 
         4: polynom_rew = 32'b1100;
2976 
         5: polynom_rew = 32'b10100;
2977 
         6: polynom_rew = 32'b110000;
2978 
         7: polynom_rew = 32'b1100000;
2979 
         8: polynom_rew = 32'b10111000;
2980 
         9: polynom_rew = 32'b100010000;
2981 
        10: polynom_rew = 32'b1001000000;
2982 
        11: polynom_rew = 32'b10100000000;
2983 
        12: polynom_rew = 32'b100000101001;
2984 
        13: polynom_rew = 32'b1000000001100;
2985 
        14: polynom_rew = 32'b10000000010101;
2986 
        15: polynom_rew = 32'b110000000000000;
2987 
        16: polynom_rew = 32'b1101000000001000;
2988 
        17: polynom_rew = 32'b10010000000000000;
2989 
        18: polynom_rew = 32'b100000010000000000;
2990 
        19: polynom_rew = 32'b1000000000000100011;
2991 
        20: polynom_rew = 32'b10000010000000000000;
2992 
        21: polynom_rew = 32'b101000000000000000000;
2993 
        22: polynom_rew = 32'b1100000000000000000000;
2994 
        23: polynom_rew = 32'b10000100000000000000000;
2995 
        24: polynom_rew = 32'b111000010000000000000000;
2996 
        25: polynom_rew = 32'b1001000000000000000000000;
2997 
        26: polynom_rew = 32'b10000000000000000000100011;
2998 
        27: polynom_rew = 32'b100000000000000000000010011;
2999 
        28: polynom_rew = 32'b1100100000000000000000000000;
3000 
        29: polynom_rew = 32'b10100000000000000000000000000;
3001 
        30: polynom_rew = 32'b100000000000000000000000101001;
3002 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3003 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3004 
        default: polynom_rew = 32'b0;
3005 
        endcase
3006 
        // rotate left
3007 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3008 
        lfsr_fb_rew = qi[length];
3009 
        for (i=length-1; i>=1; i=i-1) begin
3010 
            if (polynom_rew[i])
3011 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3012 
        end
3013 
    end
3014 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3015 
   assign q_next = rew ? q_next_rew : q_next_fw;
3016 
 
3017 
   always @ (posedge clk or posedge rst)
3018 
     if (rst)
3019 
       qi <= {length{1'b0}};
3020 
     else
3021 
     if (cke)
3022 
       qi <= q_next;
3023 
 
3024 
 
3025 
 
3026 
    always @ (posedge clk or posedge rst)
3027 
    if (rst)
3028 
        level1 <= 1'b0;
3029 
    else
3030 
    if (cke)
3031 29 unneback 
    if (clear)
3032 
        level1 <= 1'b0;
3033 
    else if (q_next == level1_value)
3034 6 unneback 
        level1 <= 1'b1;
3035 
    else if (qi == level1_value & rew)
3036 
        level1 <= 1'b0;
3037 
endmodule
3038 40 unneback 
`endif
3039 
`ifdef CNT_GRAY
3040 6 unneback 
//////////////////////////////////////////////////////////////////////
3041 
////                                                              ////
3042 
////  Versatile counter                                           ////
3043 
////                                                              ////
3044 
////  Description                                                 ////
3045 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3046 
////  counter                                                     ////
3047 
////                                                              ////
3048 
////  To Do:                                                      ////
3049 
////   - add LFSR with more taps                                  ////
3050 
////                                                              ////
3051 
////  Author(s):                                                  ////
3052 
////      - Michael Unneback, unneback@opencores.org              ////
3053 
////        ORSoC AB                                              ////
3054 
////                                                              ////
3055 
//////////////////////////////////////////////////////////////////////
3056 
////                                                              ////
3057 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3058 
////                                                              ////
3059 
//// This source file may be used and distributed without         ////
3060 
//// restriction provided that this copyright statement is not    ////
3061 
//// removed from the file and that any derivative work contains  ////
3062 
//// the original copyright notice and the associated disclaimer. ////
3063 
////                                                              ////
3064 
//// This source file is free software; you can redistribute it   ////
3065 
//// and/or modify it under the terms of the GNU Lesser General   ////
3066 
//// Public License as published by the Free Software Foundation; ////
3067 
//// either version 2.1 of the License, or (at your option) any   ////
3068 
//// later version.                                               ////
3069 
////                                                              ////
3070 
//// This source is distributed in the hope that it will be       ////
3071 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3072 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3073 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3074 
//// details.                                                     ////
3075 
////                                                              ////
3076 
//// You should have received a copy of the GNU Lesser General    ////
3077 
//// Public License along with this source; if not, download it   ////
3078 
//// from http://www.opencores.org/lgpl.shtml                     ////
3079 
////                                                              ////
3080 
//////////////////////////////////////////////////////////////////////
3081 
 
3082 
// GRAY counter
3083 
 
3084 40 unneback 
`define MODULE cnt_gray
3085 
module `BASE`MODULE (
3086 
`undef MODULE
3087 
 q, rst, clk);
3088 
 
3089 6 unneback 
   parameter length = 4;
3090 
   output reg [length:1] q;
3091 
   input rst;
3092 
   input clk;
3093 
 
3094 
   parameter clear_value = 0;
3095 
   parameter set_value = 1;
3096 
   parameter wrap_value = 8;
3097 
   parameter level1_value = 15;
3098 
 
3099 
   reg  [length:1] qi;
3100 
   wire [length:1] q_next;
3101 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3102 
 
3103 
   always @ (posedge clk or posedge rst)
3104 
     if (rst)
3105 
       qi <= {length{1'b0}};
3106 
     else
3107 
       qi <= q_next;
3108 
 
3109 
   always @ (posedge clk or posedge rst)
3110 
     if (rst)
3111 
       q <= {length{1'b0}};
3112 
     else
3113 
         q <= (q_next>>1) ^ q_next;
3114 
 
3115 
endmodule
3116 40 unneback 
`endif
3117 
`ifdef CNT_GRAY_CE
3118 6 unneback 
//////////////////////////////////////////////////////////////////////
3119 
////                                                              ////
3120 
////  Versatile counter                                           ////
3121 
////                                                              ////
3122 
////  Description                                                 ////
3123 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3124 
////  counter                                                     ////
3125 
////                                                              ////
3126 
////  To Do:                                                      ////
3127 
////   - add LFSR with more taps                                  ////
3128 
////                                                              ////
3129 
////  Author(s):                                                  ////
3130 
////      - Michael Unneback, unneback@opencores.org              ////
3131 
////        ORSoC AB                                              ////
3132 
////                                                              ////
3133 
//////////////////////////////////////////////////////////////////////
3134 
////                                                              ////
3135 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3136 
////                                                              ////
3137 
//// This source file may be used and distributed without         ////
3138 
//// restriction provided that this copyright statement is not    ////
3139 
//// removed from the file and that any derivative work contains  ////
3140 
//// the original copyright notice and the associated disclaimer. ////
3141 
////                                                              ////
3142 
//// This source file is free software; you can redistribute it   ////
3143 
//// and/or modify it under the terms of the GNU Lesser General   ////
3144 
//// Public License as published by the Free Software Foundation; ////
3145 
//// either version 2.1 of the License, or (at your option) any   ////
3146 
//// later version.                                               ////
3147 
////                                                              ////
3148 
//// This source is distributed in the hope that it will be       ////
3149 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3150 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3151 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3152 
//// details.                                                     ////
3153 
////                                                              ////
3154 
//// You should have received a copy of the GNU Lesser General    ////
3155 
//// Public License along with this source; if not, download it   ////
3156 
//// from http://www.opencores.org/lgpl.shtml                     ////
3157 
////                                                              ////
3158 
//////////////////////////////////////////////////////////////////////
3159 
 
3160 
// GRAY counter
3161 
 
3162 40 unneback 
`define MODULE cnt_gray_ce
3163 
module `BASE`MODULE (
3164 
`undef MODULE
3165 
 cke, q, rst, clk);
3166 
 
3167 6 unneback 
   parameter length = 4;
3168 
   input cke;
3169 
   output reg [length:1] q;
3170 
   input rst;
3171 
   input clk;
3172 
 
3173 
   parameter clear_value = 0;
3174 
   parameter set_value = 1;
3175 
   parameter wrap_value = 8;
3176 
   parameter level1_value = 15;
3177 
 
3178 
   reg  [length:1] qi;
3179 
   wire [length:1] q_next;
3180 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3181 
 
3182 
   always @ (posedge clk or posedge rst)
3183 
     if (rst)
3184 
       qi <= {length{1'b0}};
3185 
     else
3186 
     if (cke)
3187 
       qi <= q_next;
3188 
 
3189 
   always @ (posedge clk or posedge rst)
3190 
     if (rst)
3191 
       q <= {length{1'b0}};
3192 
     else
3193 
       if (cke)
3194 
         q <= (q_next>>1) ^ q_next;
3195 
 
3196 
endmodule
3197 40 unneback 
`endif
3198 
`ifdef CNT_GRAY_CE_BIN
3199 6 unneback 
//////////////////////////////////////////////////////////////////////
3200 
////                                                              ////
3201 
////  Versatile counter                                           ////
3202 
////                                                              ////
3203 
////  Description                                                 ////
3204 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3205 
////  counter                                                     ////
3206 
////                                                              ////
3207 
////  To Do:                                                      ////
3208 
////   - add LFSR with more taps                                  ////
3209 
////                                                              ////
3210 
////  Author(s):                                                  ////
3211 
////      - Michael Unneback, unneback@opencores.org              ////
3212 
////        ORSoC AB                                              ////
3213 
////                                                              ////
3214 
//////////////////////////////////////////////////////////////////////
3215 
////                                                              ////
3216 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3217 
////                                                              ////
3218 
//// This source file may be used and distributed without         ////
3219 
//// restriction provided that this copyright statement is not    ////
3220 
//// removed from the file and that any derivative work contains  ////
3221 
//// the original copyright notice and the associated disclaimer. ////
3222 
////                                                              ////
3223 
//// This source file is free software; you can redistribute it   ////
3224 
//// and/or modify it under the terms of the GNU Lesser General   ////
3225 
//// Public License as published by the Free Software Foundation; ////
3226 
//// either version 2.1 of the License, or (at your option) any   ////
3227 
//// later version.                                               ////
3228 
////                                                              ////
3229 
//// This source is distributed in the hope that it will be       ////
3230 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3231 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3232 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3233 
//// details.                                                     ////
3234 
////                                                              ////
3235 
//// You should have received a copy of the GNU Lesser General    ////
3236 
//// Public License along with this source; if not, download it   ////
3237 
//// from http://www.opencores.org/lgpl.shtml                     ////
3238 
////                                                              ////
3239 
//////////////////////////////////////////////////////////////////////
3240 
 
3241 
// GRAY counter
3242 
 
3243 40 unneback 
`define MODULE cnt_gray_ce_bin
3244 
module `BASE`MODULE (
3245 
`undef MODULE
3246 
 cke, q, q_bin, rst, clk);
3247 
 
3248 6 unneback 
   parameter length = 4;
3249 
   input cke;
3250 
   output reg [length:1] q;
3251 
   output [length:1] q_bin;
3252 
   input rst;
3253 
   input clk;
3254 
 
3255 
   parameter clear_value = 0;
3256 
   parameter set_value = 1;
3257 
   parameter wrap_value = 8;
3258 
   parameter level1_value = 15;
3259 
 
3260 
   reg  [length:1] qi;
3261 
   wire [length:1] q_next;
3262 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3263 
 
3264 
   always @ (posedge clk or posedge rst)
3265 
     if (rst)
3266 
       qi <= {length{1'b0}};
3267 
     else
3268 
     if (cke)
3269 
       qi <= q_next;
3270 
 
3271 
   always @ (posedge clk or posedge rst)
3272 
     if (rst)
3273 
       q <= {length{1'b0}};
3274 
     else
3275 
       if (cke)
3276 
         q <= (q_next>>1) ^ q_next;
3277 
 
3278 
   assign q_bin = qi;
3279 
 
3280 
endmodule
3281 40 unneback 
`endif
3282 6 unneback 
//////////////////////////////////////////////////////////////////////
3283 
////                                                              ////
3284 
////  Versatile library, counters                                 ////
3285 
////                                                              ////
3286 
////  Description                                                 ////
3287 
////  counters                                                    ////
3288 
////                                                              ////
3289 
////                                                              ////
3290 
////  To Do:                                                      ////
3291 
////   - add more counters                                        ////
3292 
////                                                              ////
3293 
////  Author(s):                                                  ////
3294 
////      - Michael Unneback, unneback@opencores.org              ////
3295 
////        ORSoC AB                                              ////
3296 
////                                                              ////
3297 
//////////////////////////////////////////////////////////////////////
3298 
////                                                              ////
3299 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3300 
////                                                              ////
3301 
//// This source file may be used and distributed without         ////
3302 
//// restriction provided that this copyright statement is not    ////
3303 
//// removed from the file and that any derivative work contains  ////
3304 
//// the original copyright notice and the associated disclaimer. ////
3305 
////                                                              ////
3306 
//// This source file is free software; you can redistribute it   ////
3307 
//// and/or modify it under the terms of the GNU Lesser General   ////
3308 
//// Public License as published by the Free Software Foundation; ////
3309 
//// either version 2.1 of the License, or (at your option) any   ////
3310 
//// later version.                                               ////
3311 
////                                                              ////
3312 
//// This source is distributed in the hope that it will be       ////
3313 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3314 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3315 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3316 
//// details.                                                     ////
3317 
////                                                              ////
3318 
//// You should have received a copy of the GNU Lesser General    ////
3319 
//// Public License along with this source; if not, download it   ////
3320 
//// from http://www.opencores.org/lgpl.shtml                     ////
3321 
////                                                              ////
3322 
//////////////////////////////////////////////////////////////////////
3323 
 
3324 40 unneback 
`ifdef CNT_SHREG_WRAP
3325 
`define MODULE cnt_shreg_wrap
3326 
module `BASE`MODULE ( q, rst, clk);
3327 
`undef MODULE
3328 6 unneback 
 
3329 
   parameter length = 4;
3330 
   output reg [0:length-1] q;
3331 
   input rst;
3332 
   input clk;
3333 
 
3334 
    always @ (posedge clk or posedge rst)
3335 
    if (rst)
3336 
        q <= {1'b1,{length-1{1'b0}}};
3337 
    else
3338 
        q <= {q[length-1],q[0:length-2]};
3339 
 
3340 
endmodule
3341 40 unneback 
`endif
3342 6 unneback 
 
3343 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3344 
`define MODULE cnt_shreg_ce_wrap
3345 
module `BASE`MODULE ( cke, q, rst, clk);
3346 
`undef MODULE
3347 6 unneback 
 
3348 
   parameter length = 4;
3349 
   input cke;
3350 
   output reg [0:length-1] q;
3351 
   input rst;
3352 
   input clk;
3353 
 
3354 
    always @ (posedge clk or posedge rst)
3355 
    if (rst)
3356 
        q <= {1'b1,{length-1{1'b0}}};
3357 
    else
3358 
        if (cke)
3359 
            q <= {q[length-1],q[0:length-2]};
3360 
 
3361 
endmodule
3362 40 unneback 
`endif
3363 6 unneback 
 
3364 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3365 
`define MODULE cnt_shreg_ce_clear
3366 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3367 
`undef MODULE
3368 6 unneback 
 
3369 
   parameter length = 4;
3370 
   input cke, clear;
3371 
   output reg [0:length-1] q;
3372 
   input rst;
3373 
   input clk;
3374 
 
3375 
    always @ (posedge clk or posedge rst)
3376 
    if (rst)
3377 
        q <= {1'b1,{length-1{1'b0}}};
3378 
    else
3379 
        if (cke)
3380 
            if (clear)
3381 
                q <= {1'b1,{length-1{1'b0}}};
3382 
            else
3383 
                q <= q >> 1;
3384 
 
3385 
endmodule
3386 40 unneback 
`endif
3387 6 unneback 
 
3388 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3389 
`define MODULE cnt_shreg_ce_clear_wrap
3390 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3391 
`undef MODULE
3392 6 unneback 
 
3393 
   parameter length = 4;
3394 
   input cke, clear;
3395 
   output reg [0:length-1] q;
3396 
   input rst;
3397 
   input clk;
3398 
 
3399 
    always @ (posedge clk or posedge rst)
3400 
    if (rst)
3401 
        q <= {1'b1,{length-1{1'b0}}};
3402 
    else
3403 
        if (cke)
3404 
            if (clear)
3405 
                q <= {1'b1,{length-1{1'b0}}};
3406 
            else
3407 
            q <= {q[length-1],q[0:length-2]};
3408 
 
3409 
endmodule
3410 40 unneback 
`endif
3411 6 unneback 
//////////////////////////////////////////////////////////////////////
3412 
////                                                              ////
3413 
////  Versatile library, memories                                 ////
3414 
////                                                              ////
3415 
////  Description                                                 ////
3416 
////  memories                                                    ////
3417 
////                                                              ////
3418 
////                                                              ////
3419 
////  To Do:                                                      ////
3420 
////   - add more memory types                                    ////
3421 
////                                                              ////
3422 
////  Author(s):                                                  ////
3423 
////      - Michael Unneback, unneback@opencores.org              ////
3424 
////        ORSoC AB                                              ////
3425 
////                                                              ////
3426 
//////////////////////////////////////////////////////////////////////
3427 
////                                                              ////
3428 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3429 
////                                                              ////
3430 
//// This source file may be used and distributed without         ////
3431 
//// restriction provided that this copyright statement is not    ////
3432 
//// removed from the file and that any derivative work contains  ////
3433 
//// the original copyright notice and the associated disclaimer. ////
3434 
////                                                              ////
3435 
//// This source file is free software; you can redistribute it   ////
3436 
//// and/or modify it under the terms of the GNU Lesser General   ////
3437 
//// Public License as published by the Free Software Foundation; ////
3438 
//// either version 2.1 of the License, or (at your option) any   ////
3439 
//// later version.                                               ////
3440 
////                                                              ////
3441 
//// This source is distributed in the hope that it will be       ////
3442 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3443 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3444 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3445 
//// details.                                                     ////
3446 
////                                                              ////
3447 
//// You should have received a copy of the GNU Lesser General    ////
3448 
//// Public License along with this source; if not, download it   ////
3449 
//// from http://www.opencores.org/lgpl.shtml                     ////
3450 
////                                                              ////
3451 
//////////////////////////////////////////////////////////////////////
3452 
 
3453 40 unneback 
`ifdef ROM_INIT
3454 6 unneback 
/// ROM
3455 40 unneback 
`define MODULE rom_init
3456 
module `BASE`MODULE ( adr, q, clk);
3457 
`undef MODULE
3458 6 unneback 
 
3459 7 unneback 
   parameter data_width = 32;
3460 
   parameter addr_width = 8;
3461 
   input [(addr_width-1):0]       adr;
3462 
   output reg [(data_width-1):0] q;
3463 
   input                         clk;
3464 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3465 
   parameter memory_file = "vl_rom.vmem";
3466 
   initial
3467 
     begin
3468 
        $readmemh(memory_file, rom);
3469 
     end
3470 
 
3471 
   always @ (posedge clk)
3472 
     q <= rom[adr];
3473 6 unneback 
 
3474 7 unneback 
endmodule
3475 40 unneback 
`endif
3476 7 unneback 
 
3477 40 unneback 
`ifdef RAM
3478 
`define MODULE ram
3479 6 unneback 
// Single port RAM
3480 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3481 
`undef MODULE
3482 6 unneback 
 
3483 
   parameter data_width = 32;
3484 
   parameter addr_width = 8;
3485 
   input [(data_width-1):0]      d;
3486 
   input [(addr_width-1):0]       adr;
3487 
   input                         we;
3488 7 unneback 
   output reg [(data_width-1):0] q;
3489 6 unneback 
   input                         clk;
3490 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3491 7 unneback 
   parameter init = 0;
3492 
   parameter memory_file = "vl_ram.vmem";
3493 
   generate if (init) begin : init_mem
3494 
   initial
3495 
     begin
3496 
        $readmemh(memory_file, ram);
3497 
     end
3498 
   end
3499 
   endgenerate
3500 
 
3501 6 unneback 
   always @ (posedge clk)
3502 
   begin
3503 
   if (we)
3504 
     ram[adr] <= d;
3505 
   q <= ram[adr];
3506 
   end
3507 
 
3508 
endmodule
3509 40 unneback 
`endif
3510 6 unneback 
 
3511 40 unneback 
`ifdef RAM_BE
3512 
`define MODULE ram_be
3513 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3514 
`undef MODULE
3515 
 
3516 7 unneback 
   parameter data_width = 32;
3517 
   parameter addr_width = 8;
3518 
   input [(data_width-1):0]      d;
3519 
   input [(addr_width-1):0]       adr;
3520 
   input [(addr_width/4)-1:0]    be;
3521 
   input                         we;
3522 
   output reg [(data_width-1):0] q;
3523 
   input                         clk;
3524 
 
3525 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3526 
 
3527 60 unneback 
   parameter memory_init = 0;
3528 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3529 60 unneback 
   generate if (memory_init) begin : init_mem
3530 7 unneback 
   initial
3531 
     begin
3532 
        $readmemh(memory_file, ram);
3533 
     end
3534 
   end
3535 
   endgenerate
3536 
 
3537 60 unneback 
`ifdef SYSTEMVERILOG
3538 
// use a multi-dimensional packed array
3539 
//to model individual bytes within the word
3540 
 
3541 
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
3542 
always_ff@(posedge clk)
3543 
begin
3544 
    if(we) begin // note: we should have a for statement to support any bus width
3545 
        if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
3546 
        if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
3547 
        if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
3548 
        if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
3549 
    end
3550 
    q <= ram[raddr];
3551 
end
3552 
 
3553 
`else
3554 
 
3555 7 unneback 
   genvar i;
3556 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3557 
      always @ (posedge clk)
3558 
      if (we & be[i])
3559 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3560 
   end
3561 
   endgenerate
3562 
 
3563 
   always @ (posedge clk)
3564 
      q <= ram[adr];
3565 
 
3566 60 unneback 
`endif
3567 
 
3568 7 unneback 
endmodule
3569 40 unneback 
`endif
3570 7 unneback 
 
3571 6 unneback 
`ifdef ACTEL
3572 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3573 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3574 
`else
3575 
        `define SYN
3576 
`endif
3577 
 
3578 40 unneback 
`ifdef DPRAM_1R1W
3579 
`define MODULE dpram_1r1w
3580 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3581 
`undef MODULE
3582 6 unneback 
   parameter data_width = 32;
3583 
   parameter addr_width = 8;
3584 
   input [(data_width-1):0]      d_a;
3585 
   input [(addr_width-1):0]       adr_a;
3586 
   input [(addr_width-1):0]       adr_b;
3587 
   input                         we_a;
3588 
   output [(data_width-1):0]      q_b;
3589 
   input                         clk_a, clk_b;
3590 
   reg [(addr_width-1):0]         adr_b_reg;
3591 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3592 7 unneback 
 
3593 
   parameter init = 0;
3594 
   parameter memory_file = "vl_ram.vmem";
3595 
   generate if (init) begin : init_mem
3596 
   initial
3597 
     begin
3598 
        $readmemh(memory_file, ram);
3599 
     end
3600 
   end
3601 
   endgenerate
3602 
 
3603 6 unneback 
   always @ (posedge clk_a)
3604 
   if (we_a)
3605 
     ram[adr_a] <= d_a;
3606 
   always @ (posedge clk_b)
3607 
   adr_b_reg <= adr_b;
3608 
   assign q_b = ram[adr_b_reg];
3609 40 unneback 
 
3610 6 unneback 
endmodule
3611 40 unneback 
`endif
3612 6 unneback 
 
3613 40 unneback 
`ifdef DPRAM_2R1W
3614 
`define MODULE dpram_2r1w
3615 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3616 
`undef MODULE
3617 
 
3618 6 unneback 
   parameter data_width = 32;
3619 
   parameter addr_width = 8;
3620 
   input [(data_width-1):0]      d_a;
3621 
   input [(addr_width-1):0]       adr_a;
3622 
   input [(addr_width-1):0]       adr_b;
3623 
   input                         we_a;
3624 
   output [(data_width-1):0]      q_b;
3625 
   output reg [(data_width-1):0] q_a;
3626 
   input                         clk_a, clk_b;
3627 
   reg [(data_width-1):0]         q_b;
3628 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3629 7 unneback 
 
3630 
   parameter init = 0;
3631 
   parameter memory_file = "vl_ram.vmem";
3632 
   generate if (init) begin : init_mem
3633 
   initial
3634 
     begin
3635 
        $readmemh(memory_file, ram);
3636 
     end
3637 
   end
3638 
   endgenerate
3639 
 
3640 6 unneback 
   always @ (posedge clk_a)
3641 
     begin
3642 
        q_a <= ram[adr_a];
3643 
        if (we_a)
3644 
             ram[adr_a] <= d_a;
3645 
     end
3646 
   always @ (posedge clk_b)
3647 
          q_b <= ram[adr_b];
3648 
endmodule
3649 40 unneback 
`endif
3650 6 unneback 
 
3651 40 unneback 
`ifdef DPRAM_2R2W
3652 
`define MODULE dpram_2r2w
3653 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3654 
`undef MODULE
3655 
 
3656 6 unneback 
   parameter data_width = 32;
3657 
   parameter addr_width = 8;
3658 
   input [(data_width-1):0]      d_a;
3659 
   input [(addr_width-1):0]       adr_a;
3660 
   input [(addr_width-1):0]       adr_b;
3661 
   input                         we_a;
3662 
   output [(data_width-1):0]      q_b;
3663 
   input [(data_width-1):0]       d_b;
3664 
   output reg [(data_width-1):0] q_a;
3665 
   input                         we_b;
3666 
   input                         clk_a, clk_b;
3667 
   reg [(data_width-1):0]         q_b;
3668 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3669 7 unneback 
 
3670 
   parameter init = 0;
3671 
   parameter memory_file = "vl_ram.vmem";
3672 
   generate if (init) begin : init_mem
3673 
   initial
3674 
     begin
3675 
        $readmemh(memory_file, ram);
3676 
     end
3677 
   end
3678 
   endgenerate
3679 
 
3680 6 unneback 
   always @ (posedge clk_a)
3681 
     begin
3682 
        q_a <= ram[adr_a];
3683 
        if (we_a)
3684 
             ram[adr_a] <= d_a;
3685 
     end
3686 
   always @ (posedge clk_b)
3687 
     begin
3688 
        q_b <= ram[adr_b];
3689 
        if (we_b)
3690 
          ram[adr_b] <= d_b;
3691 
     end
3692 
endmodule
3693 40 unneback 
`endif
3694 6 unneback 
 
3695 
// Content addresable memory, CAM
3696 
 
3697 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3698 6 unneback 
// FIFO
3699 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
3700 
module `BASE`MODULE (
3701 
`undef MODULE
3702 25 unneback 
    d, wr, fifo_full,
3703 
    q, rd, fifo_empty,
3704 
    fill_level,
3705 
    clk, rst
3706 
    );
3707 
 
3708 
parameter data_width = 18;
3709 
parameter addr_width = 4;
3710 6 unneback 
 
3711 25 unneback 
// write side
3712 
input  [data_width-1:0] d;
3713 
input                   wr;
3714 
output                  fifo_full;
3715 
// read side
3716 
output [data_width-1:0] q;
3717 
input                   rd;
3718 
output                  fifo_empty;
3719 
// common
3720 
output [addr_width:0]   fill_level;
3721 
input rst, clk;
3722 
 
3723 
wire [addr_width:1] wadr, radr;
3724 
 
3725 40 unneback 
`define MODULE cnt_bin_ce
3726 
`BASE`MODULE
3727 25 unneback 
    # ( .length(addr_width))
3728 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3729 40 unneback 
`BASE`MODULE
3730 25 unneback 
    # (.length(addr_width))
3731 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3732 40 unneback 
`undef MODULE
3733 25 unneback 
 
3734 40 unneback 
`define MODULE dpram_1r1w
3735 
`BASE`MODULE
3736 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3737 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3738 40 unneback 
`undef MODULE
3739 25 unneback 
 
3740 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
3741 
`BASE`MODULE
3742 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3743 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3744 40 unneback 
`undef MODULE
3745 25 unneback 
endmodule
3746 40 unneback 
`endif
3747 25 unneback 
 
3748 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3749 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3750 
// RAM is supposed to be larger than the two FIFOs
3751 
// LFSR counters used adr pointers
3752 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
3753 
module `BASE`MODULE (
3754 
`undef MODULE
3755 27 unneback 
    // a side
3756 
    a_d, a_wr, a_fifo_full,
3757 
    a_q, a_rd, a_fifo_empty,
3758 
    a_fill_level,
3759 
    // b side
3760 
    b_d, b_wr, b_fifo_full,
3761 
    b_q, b_rd, b_fifo_empty,
3762 
    b_fill_level,
3763 
    // common
3764 
    clk, rst
3765 
    );
3766 
parameter data_width = 8;
3767 
parameter addr_width = 5;
3768 
parameter fifo_full_level = (1<<addr_width)-1;
3769 
 
3770 
// a side
3771 
input  [data_width-1:0] a_d;
3772 
input                   a_wr;
3773 
output                  a_fifo_full;
3774 
output [data_width-1:0] a_q;
3775 
input                   a_rd;
3776 
output                  a_fifo_empty;
3777 
output [addr_width-1:0] a_fill_level;
3778 
 
3779 
// b side
3780 
input  [data_width-1:0] b_d;
3781 
input                   b_wr;
3782 
output                  b_fifo_full;
3783 
output [data_width-1:0] b_q;
3784 
input                   b_rd;
3785 
output                  b_fifo_empty;
3786 
output [addr_width-1:0] b_fill_level;
3787 
 
3788 
input                   clk;
3789 
input                   rst;
3790 
 
3791 
// adr_gen
3792 
wire [addr_width:1] a_wadr, a_radr;
3793 
wire [addr_width:1] b_wadr, b_radr;
3794 
// dpram
3795 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3796 
 
3797 40 unneback 
`define MODULE cnt_lfsr_ce
3798 
`BASE`MODULE
3799 27 unneback 
    # ( .length(addr_width))
3800 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3801 
 
3802 40 unneback 
`BASE`MODULE
3803 27 unneback 
    # (.length(addr_width))
3804 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3805 
 
3806 40 unneback 
`BASE`MODULE
3807 27 unneback 
    # ( .length(addr_width))
3808 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3809 
 
3810 40 unneback 
`BASE`MODULE
3811 27 unneback 
    # (.length(addr_width))
3812 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3813 40 unneback 
`undef MODULE
3814 27 unneback 
 
3815 
// mux read or write adr to DPRAM
3816 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3817 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3818 
 
3819 40 unneback 
`define MODULE dpram_2r2w
3820 
`BASE`MODULE
3821 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
3822 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3823 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3824 40 unneback 
`undef MODULE
3825 
 
3826 
`define MODULE cnt_bin_ce_rew_zq_l1
3827 
`BASE`MODULE
3828 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3829 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3830 
 
3831 40 unneback 
`BASE`MODULE
3832 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3833 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3834 40 unneback 
`undef MODULE
3835 27 unneback 
 
3836 
endmodule
3837 40 unneback 
`endif
3838 27 unneback 
 
3839 40 unneback 
`ifdef FIFO_CMP_ASYNC
3840 
`define MODULE fifo_cmp_async
3841 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3842 
`undef MODULE
3843 6 unneback 
 
3844 11 unneback 
   parameter addr_width = 4;
3845 
   parameter N = addr_width-1;
3846 6 unneback 
 
3847 
   parameter Q1 = 2'b00;
3848 
   parameter Q2 = 2'b01;
3849 
   parameter Q3 = 2'b11;
3850 
   parameter Q4 = 2'b10;
3851 
 
3852 
   parameter going_empty = 1'b0;
3853 
   parameter going_full  = 1'b1;
3854 
 
3855 
   input [N:0]  wptr, rptr;
3856 14 unneback 
   output       fifo_empty;
3857 6 unneback 
   output       fifo_full;
3858 
   input        wclk, rclk, rst;
3859 
 
3860 
`ifndef GENERATE_DIRECTION_AS_LATCH
3861 
   wire direction;
3862 
`endif
3863 
`ifdef GENERATE_DIRECTION_AS_LATCH
3864 
   reg direction;
3865 
`endif
3866 
   reg  direction_set, direction_clr;
3867 
 
3868 
   wire async_empty, async_full;
3869 
   wire fifo_full2;
3870 14 unneback 
   wire fifo_empty2;
3871 6 unneback 
 
3872 
   // direction_set
3873 
   always @ (wptr[N:N-1] or rptr[N:N-1])
3874 
     case ({wptr[N:N-1],rptr[N:N-1]})
3875 
       {Q1,Q2} : direction_set <= 1'b1;
3876 
       {Q2,Q3} : direction_set <= 1'b1;
3877 
       {Q3,Q4} : direction_set <= 1'b1;
3878 
       {Q4,Q1} : direction_set <= 1'b1;
3879 
       default : direction_set <= 1'b0;
3880 
     endcase
3881 
 
3882 
   // direction_clear
3883 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3884 
     if (rst)
3885 
       direction_clr <= 1'b1;
3886 
     else
3887 
       case ({wptr[N:N-1],rptr[N:N-1]})
3888 
         {Q2,Q1} : direction_clr <= 1'b1;
3889 
         {Q3,Q2} : direction_clr <= 1'b1;
3890 
         {Q4,Q3} : direction_clr <= 1'b1;
3891 
         {Q1,Q4} : direction_clr <= 1'b1;
3892 
         default : direction_clr <= 1'b0;
3893 
       endcase
3894 
 
3895 40 unneback 
`define MODULE dff_sr
3896 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
3897 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3898 6 unneback 
`endif
3899 
 
3900 
`ifdef GENERATE_DIRECTION_AS_LATCH
3901 
   always @ (posedge direction_set or posedge direction_clr)
3902 
     if (direction_clr)
3903 
       direction <= going_empty;
3904 
     else
3905 
       direction <= going_full;
3906 
`endif
3907 
 
3908 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3909 
   assign async_full  = (wptr == rptr) && (direction==going_full);
3910 
 
3911 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3912 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3913 
`undef MODULE
3914 6 unneback 
 
3915 
/*
3916 
   always @ (posedge wclk or posedge rst or posedge async_full)
3917 
     if (rst)
3918 
       {fifo_full, fifo_full2} <= 2'b00;
3919 
     else if (async_full)
3920 
       {fifo_full, fifo_full2} <= 2'b11;
3921 
     else
3922 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3923 
*/
3924 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
3925 6 unneback 
     if (async_empty)
3926 
       {fifo_empty, fifo_empty2} <= 2'b11;
3927 
     else
3928 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3929 40 unneback 
`define MODULE dff
3930 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3931 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3932 
`undef MODULE
3933 27 unneback 
endmodule // async_compb
3934 40 unneback 
`endif
3935 6 unneback 
 
3936 40 unneback 
`ifdef FIFO_1R1W_ASYNC
3937 
`define MODULE fifo_1r1w_async
3938 
module `BASE`MODULE (
3939 
`undef MODULE
3940 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
3941 
    q, rd, fifo_empty, rd_clk, rd_rst
3942 
    );
3943 
 
3944 
parameter data_width = 18;
3945 
parameter addr_width = 4;
3946 
 
3947 
// write side
3948 
input  [data_width-1:0] d;
3949 
input                   wr;
3950 
output                  fifo_full;
3951 
input                   wr_clk;
3952 
input                   wr_rst;
3953 
// read side
3954 
output [data_width-1:0] q;
3955 
input                   rd;
3956 
output                  fifo_empty;
3957 
input                   rd_clk;
3958 
input                   rd_rst;
3959 
 
3960 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3961 23 unneback 
 
3962 40 unneback 
`define MODULE cnt_gray_ce_bin
3963 
`BASE`MODULE
3964 6 unneback 
    # ( .length(addr_width))
3965 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3966 
 
3967 40 unneback 
`BASE`MODULE
3968 6 unneback 
    # (.length(addr_width))
3969 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3970 40 unneback 
`undef MODULE
3971 6 unneback 
 
3972 40 unneback 
`define MODULE dpram_1r1w
3973 
`BASE`MODULE
3974 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3975 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3976 40 unneback 
`undef MODULE
3977 6 unneback 
 
3978 40 unneback 
`define MODULE fifo_cmp_async
3979 
`BASE`MODULE
3980 6 unneback 
    # (.addr_width(addr_width))
3981 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3982 40 unneback 
`undef MODULE
3983 6 unneback 
 
3984 
endmodule
3985 40 unneback 
`endif
3986 6 unneback 
 
3987 40 unneback 
`ifdef FIFO_2R2W_ASYNC
3988 
`define MODULE fifo_2r2w_async
3989 
module `BASE`MODULE (
3990 
`undef MODULE
3991 6 unneback 
    // a side
3992 
    a_d, a_wr, a_fifo_full,
3993 
    a_q, a_rd, a_fifo_empty,
3994 
    a_clk, a_rst,
3995 
    // b side
3996 
    b_d, b_wr, b_fifo_full,
3997 
    b_q, b_rd, b_fifo_empty,
3998 
    b_clk, b_rst
3999 
    );
4000 
 
4001 
parameter data_width = 18;
4002 
parameter addr_width = 4;
4003 
 
4004 
// a side
4005 
input  [data_width-1:0] a_d;
4006 
input                   a_wr;
4007 
output                  a_fifo_full;
4008 
output [data_width-1:0] a_q;
4009 
input                   a_rd;
4010 
output                  a_fifo_empty;
4011 
input                   a_clk;
4012 
input                   a_rst;
4013 
 
4014 
// b side
4015 
input  [data_width-1:0] b_d;
4016 
input                   b_wr;
4017 
output                  b_fifo_full;
4018 
output [data_width-1:0] b_q;
4019 
input                   b_rd;
4020 
output                  b_fifo_empty;
4021 
input                   b_clk;
4022 
input                   b_rst;
4023 
 
4024 40 unneback 
`define MODULE fifo_1r1w_async
4025 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4026 6 unneback 
vl_fifo_1r1w_async_a (
4027 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4028 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4029 
    );
4030 
 
4031 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4032 6 unneback 
vl_fifo_1r1w_async_b (
4033 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4034 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4035 
    );
4036 40 unneback 
`undef MODULE
4037 
 
4038 6 unneback 
endmodule
4039 40 unneback 
`endif
4040 6 unneback 
 
4041 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4042 
`define MODULE fifo_2r2w_async_simplex
4043 
module `BASE`MODULE (
4044 
`undef MODULE
4045 6 unneback 
    // a side
4046 
    a_d, a_wr, a_fifo_full,
4047 
    a_q, a_rd, a_fifo_empty,
4048 
    a_clk, a_rst,
4049 
    // b side
4050 
    b_d, b_wr, b_fifo_full,
4051 
    b_q, b_rd, b_fifo_empty,
4052 
    b_clk, b_rst
4053 
    );
4054 
 
4055 
parameter data_width = 18;
4056 
parameter addr_width = 4;
4057 
 
4058 
// a side
4059 
input  [data_width-1:0] a_d;
4060 
input                   a_wr;
4061 
output                  a_fifo_full;
4062 
output [data_width-1:0] a_q;
4063 
input                   a_rd;
4064 
output                  a_fifo_empty;
4065 
input                   a_clk;
4066 
input                   a_rst;
4067 
 
4068 
// b side
4069 
input  [data_width-1:0] b_d;
4070 
input                   b_wr;
4071 
output                  b_fifo_full;
4072 
output [data_width-1:0] b_q;
4073 
input                   b_rd;
4074 
output                  b_fifo_empty;
4075 
input                   b_clk;
4076 
input                   b_rst;
4077 
 
4078 
// adr_gen
4079 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4080 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4081 
// dpram
4082 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4083 
 
4084 40 unneback 
`define MODULE cnt_gray_ce_bin
4085 
`BASE`MODULE
4086 6 unneback 
    # ( .length(addr_width))
4087 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4088 
 
4089 40 unneback 
`BASE`MODULE
4090 6 unneback 
    # (.length(addr_width))
4091 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4092 
 
4093 40 unneback 
`BASE`MODULE
4094 6 unneback 
    # ( .length(addr_width))
4095 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4096 
 
4097 40 unneback 
`BASE`MODULE
4098 6 unneback 
    # (.length(addr_width))
4099 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4100 40 unneback 
`undef MODULE
4101 6 unneback 
 
4102 
// mux read or write adr to DPRAM
4103 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4104 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4105 
 
4106 40 unneback 
`define MODULE dpram_2r2w
4107 
`BASE`MODULE
4108 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4109 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4110 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4111 40 unneback 
`undef MODULE
4112 6 unneback 
 
4113 40 unneback 
`define MODULE fifo_cmp_async
4114 
`BASE`MODULE
4115 6 unneback 
    # (.addr_width(addr_width))
4116 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4117 
 
4118 40 unneback 
`BASE`MODULE
4119 6 unneback 
    # (.addr_width(addr_width))
4120 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4121 40 unneback 
`undef MODULE
4122 6 unneback 
 
4123 
endmodule
4124 40 unneback 
`endif
4125 48 unneback 
 
4126 
`ifdef REG_FILE
4127 
`define MODULE reg_file
4128 
module `BASE`MODULE (
4129 
`undef MODULE
4130 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4131 
);
4132 
parameter data_width = 32;
4133 
parameter addr_width = 5;
4134 
input [addr_width-1:0] a1, a2, a3;
4135 
input [data_width-1:0] wd3;
4136 
input we3;
4137 
output [data_width-1:0] rd1, rd2;
4138 
input clk;
4139 
 
4140 
`ifdef ACTEL
4141 
reg [data_width-1:0] wd3_reg;
4142 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4143 
reg we3_reg;
4144 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4145 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4146 
always @ (posedge clk or posedge rst)
4147 
if (rst)
4148 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4149 
else
4150 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4151 
 
4152 
    always @ (negedge clk)
4153 
    if (we3_reg)
4154 
        ram1[a3_reg] <= wd3;
4155 
    always @ (posedge clk)
4156 
        a1_reg <= a1;
4157 
    assign rd1 = ram1[a1_reg];
4158 
 
4159 
    always @ (negedge clk)
4160 
    if (we3_reg)
4161 
        ram2[a3_reg] <= wd3;
4162 
    always @ (posedge clk)
4163 
        a2_reg <= a2;
4164 
    assign rd2 = ram2[a2_reg];
4165 
 
4166 
`else
4167 
 
4168 
`define MODULE dpram_1r1w
4169 
`BASE`MODULE
4170 
    # ( .data_width(data_width), .addr_width(addr_width))
4171 
    ram1 (
4172 
        .d_a(wd3),
4173 
        .adr_a(a3),
4174 
        .we_a(we3),
4175 
        .clk_a(clk),
4176 
        .q_b(rd1),
4177 
        .adr_b(a1),
4178 
        .clk_b(clk) );
4179 
 
4180 
`BASE`MODULE
4181 
    # ( .data_width(data_width), .addr_width(addr_width))
4182 
    ram2 (
4183 
        .d_a(wd3),
4184 
        .adr_a(a3),
4185 
        .we_a(we3),
4186 
        .clk_a(clk),
4187 
        .q_b(rd2),
4188 
        .adr_b(a2),
4189 
        .clk_b(clk) );
4190 
`undef MODULE
4191 
 
4192 
`endif
4193 
 
4194 
endmodule
4195 
`endif
4196 12 unneback 
//////////////////////////////////////////////////////////////////////
4197 
////                                                              ////
4198 
////  Versatile library, wishbone stuff                           ////
4199 
////                                                              ////
4200 
////  Description                                                 ////
4201 
////  Wishbone compliant modules                                  ////
4202 
////                                                              ////
4203 
////                                                              ////
4204 
////  To Do:                                                      ////
4205 
////   -                                                          ////
4206 
////                                                              ////
4207 
////  Author(s):                                                  ////
4208 
////      - Michael Unneback, unneback@opencores.org              ////
4209 
////        ORSoC AB                                              ////
4210 
////                                                              ////
4211 
//////////////////////////////////////////////////////////////////////
4212 
////                                                              ////
4213 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4214 
////                                                              ////
4215 
//// This source file may be used and distributed without         ////
4216 
//// restriction provided that this copyright statement is not    ////
4217 
//// removed from the file and that any derivative work contains  ////
4218 
//// the original copyright notice and the associated disclaimer. ////
4219 
////                                                              ////
4220 
//// This source file is free software; you can redistribute it   ////
4221 
//// and/or modify it under the terms of the GNU Lesser General   ////
4222 
//// Public License as published by the Free Software Foundation; ////
4223 
//// either version 2.1 of the License, or (at your option) any   ////
4224 
//// later version.                                               ////
4225 
////                                                              ////
4226 
//// This source is distributed in the hope that it will be       ////
4227 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4228 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4229 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4230 
//// details.                                                     ////
4231 
////                                                              ////
4232 
//// You should have received a copy of the GNU Lesser General    ////
4233 
//// Public License along with this source; if not, download it   ////
4234 
//// from http://www.opencores.org/lgpl.shtml                     ////
4235 
////                                                              ////
4236 
//////////////////////////////////////////////////////////////////////
4237 
 
4238 40 unneback 
`ifdef WB3WB3_BRIDGE
4239 12 unneback 
// async wb3 - wb3 bridge
4240 
`timescale 1ns/1ns
4241 40 unneback 
`define MODULE wb3wb3_bridge
4242 
module `BASE`MODULE (
4243 
`undef MODULE
4244 12 unneback 
        // wishbone slave side
4245 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4246 
        // wishbone master side
4247 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4248 
 
4249 
input [31:0] wbs_dat_i;
4250 
input [31:2] wbs_adr_i;
4251 
input [3:0]  wbs_sel_i;
4252 
input [1:0]  wbs_bte_i;
4253 
input [2:0]  wbs_cti_i;
4254 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4255 
output [31:0] wbs_dat_o;
4256 14 unneback 
output wbs_ack_o;
4257 12 unneback 
input wbs_clk, wbs_rst;
4258 
 
4259 
output [31:0] wbm_dat_o;
4260 
output reg [31:2] wbm_adr_o;
4261 
output [3:0]  wbm_sel_o;
4262 
output reg [1:0]  wbm_bte_o;
4263 
output reg [2:0]  wbm_cti_o;
4264 14 unneback 
output reg wbm_we_o;
4265 
output wbm_cyc_o;
4266 12 unneback 
output wbm_stb_o;
4267 
input [31:0]  wbm_dat_i;
4268 
input wbm_ack_i;
4269 
input wbm_clk, wbm_rst;
4270 
 
4271 
parameter addr_width = 4;
4272 
 
4273 
// bte
4274 
parameter linear       = 2'b00;
4275 
parameter wrap4        = 2'b01;
4276 
parameter wrap8        = 2'b10;
4277 
parameter wrap16       = 2'b11;
4278 
// cti
4279 
parameter classic      = 3'b000;
4280 
parameter incburst     = 3'b010;
4281 
parameter endofburst   = 3'b111;
4282 
 
4283 
parameter wbs_adr  = 1'b0;
4284 
parameter wbs_data = 1'b1;
4285 
 
4286 33 unneback 
parameter wbm_adr0      = 2'b00;
4287 
parameter wbm_adr1      = 2'b01;
4288 
parameter wbm_data      = 2'b10;
4289 
parameter wbm_data_wait = 2'b11;
4290 12 unneback 
 
4291 
reg [1:0] wbs_bte_reg;
4292 
reg wbs;
4293 
wire wbs_eoc_alert, wbm_eoc_alert;
4294 
reg wbs_eoc, wbm_eoc;
4295 
reg [1:0] wbm;
4296 
 
4297 14 unneback 
wire [1:16] wbs_count, wbm_count;
4298 12 unneback 
 
4299 
wire [35:0] a_d, a_q, b_d, b_q;
4300 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4301 
reg a_rd_reg;
4302 
wire b_rd_adr, b_rd_data;
4303 14 unneback 
wire b_rd_data_reg;
4304 
wire [35:0] temp;
4305 12 unneback 
 
4306 
`define WE 5
4307 
`define BTE 4:3
4308 
`define CTI 2:0
4309 
 
4310 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4311 
always @ (posedge wbs_clk or posedge wbs_rst)
4312 
if (wbs_rst)
4313 
        wbs_eoc <= 1'b0;
4314 
else
4315 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4316 
                wbs_eoc <= wbs_bte_i==linear;
4317 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4318 
                wbs_eoc <= 1'b1;
4319 
 
4320 40 unneback 
`define MODULE cnt_shreg_ce_clear
4321 
`BASE`MODULE # ( .length(16))
4322 
`undef MODULE
4323 12 unneback 
    cnt0 (
4324 
        .cke(wbs_ack_o),
4325 
        .clear(wbs_eoc),
4326 
        .q(wbs_count),
4327 
        .rst(wbs_rst),
4328 
        .clk(wbs_clk));
4329 
 
4330 
always @ (posedge wbs_clk or posedge wbs_rst)
4331 
if (wbs_rst)
4332 
        wbs <= wbs_adr;
4333 
else
4334 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4335 
                wbs <= wbs_data;
4336 
        else if (wbs_eoc & wbs_ack_o)
4337 
                wbs <= wbs_adr;
4338 
 
4339 
// wbs FIFO
4340 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4341 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4342 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4343 
              1'b0;
4344 
assign a_rd = !a_fifo_empty;
4345 
always @ (posedge wbs_clk or posedge wbs_rst)
4346 
if (wbs_rst)
4347 
        a_rd_reg <= 1'b0;
4348 
else
4349 
        a_rd_reg <= a_rd;
4350 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4351 
 
4352 
assign wbs_dat_o = a_q[35:4];
4353 
 
4354 
always @ (posedge wbs_clk or posedge wbs_rst)
4355 
if (wbs_rst)
4356 13 unneback 
        wbs_bte_reg <= 2'b00;
4357 12 unneback 
else
4358 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4359 12 unneback 
 
4360 
// wbm FIFO
4361 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4362 
always @ (posedge wbm_clk or posedge wbm_rst)
4363 
if (wbm_rst)
4364 
        wbm_eoc <= 1'b0;
4365 
else
4366 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4367 
                wbm_eoc <= b_q[`BTE] == linear;
4368 
        else if (wbm_eoc_alert & wbm_ack_i)
4369 
                wbm_eoc <= 1'b1;
4370 
 
4371 
always @ (posedge wbm_clk or posedge wbm_rst)
4372 
if (wbm_rst)
4373 
        wbm <= wbm_adr0;
4374 
else
4375 33 unneback 
/*
4376 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4377 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4378 
        (wbm==wbm_adr1 & !wbm_we_o) |
4379 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4380 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4381 33 unneback 
*/
4382 
    case (wbm)
4383 
    wbm_adr0:
4384 
        if (!b_fifo_empty)
4385 
            wbm <= wbm_adr1;
4386 
    wbm_adr1:
4387 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4388 
            wbm <= wbm_data;
4389 
    wbm_data:
4390 
        if (wbm_ack_i & wbm_eoc)
4391 
            wbm <= wbm_adr0;
4392 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4393 
            wbm <= wbm_data_wait;
4394 
    wbm_data_wait:
4395 
        if (!b_fifo_empty)
4396 
            wbm <= wbm_data;
4397 
    endcase
4398 12 unneback 
 
4399 
assign b_d = {wbm_dat_i,4'b1111};
4400 
assign b_wr = !wbm_we_o & wbm_ack_i;
4401 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4402 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4403 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4404 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4405 12 unneback 
                   1'b0;
4406 
assign b_rd = b_rd_adr | b_rd_data;
4407 
 
4408 40 unneback 
`define MODULE dff
4409 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4410 
`undef MODULE
4411 
`define MODULE dff_ce
4412 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4413 
`undef MODULE
4414 12 unneback 
 
4415 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4416 
 
4417 40 unneback 
`define MODULE cnt_shreg_ce_clear
4418 42 unneback 
`BASE`MODULE # ( .length(16))
4419 40 unneback 
`undef MODULE
4420 12 unneback 
    cnt1 (
4421 
        .cke(wbm_ack_i),
4422 
        .clear(wbm_eoc),
4423 
        .q(wbm_count),
4424 
        .rst(wbm_rst),
4425 
        .clk(wbm_clk));
4426 
 
4427 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4428 
assign wbm_stb_o = (wbm==wbm_data);
4429 12 unneback 
 
4430 
always @ (posedge wbm_clk or posedge wbm_rst)
4431 
if (wbm_rst)
4432 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4433 
else begin
4434 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4435 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4436 
        else if (wbm_eoc_alert & wbm_ack_i)
4437 
                wbm_cti_o <= endofburst;
4438 
end
4439 
 
4440 
//async_fifo_dw_simplex_top
4441 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4442 
`BASE`MODULE
4443 
`undef MODULE
4444 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4445 
fifo (
4446 
    // a side
4447 
    .a_d(a_d),
4448 
    .a_wr(a_wr),
4449 
    .a_fifo_full(a_fifo_full),
4450 
    .a_q(a_q),
4451 
    .a_rd(a_rd),
4452 
    .a_fifo_empty(a_fifo_empty),
4453 
    .a_clk(wbs_clk),
4454 
    .a_rst(wbs_rst),
4455 
    // b side
4456 
    .b_d(b_d),
4457 
    .b_wr(b_wr),
4458 
    .b_fifo_full(b_fifo_full),
4459 
    .b_q(b_q),
4460 
    .b_rd(b_rd),
4461 
    .b_fifo_empty(b_fifo_empty),
4462 
    .b_clk(wbm_clk),
4463 
    .b_rst(wbm_rst)
4464 
    );
4465 
 
4466 
endmodule
4467 40 unneback 
`undef WE
4468 
`undef BTE
4469 
`undef CTI
4470 
`endif
4471 17 unneback 
 
4472 40 unneback 
`ifdef WB3_ARBITER_TYPE1
4473 
`define MODULE wb3_arbiter_type1
4474 42 unneback 
module `BASE`MODULE (
4475 40 unneback 
`undef MODULE
4476 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4477 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4478 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4479 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4480 
    wb_clk, wb_rst
4481 
);
4482 
 
4483 
parameter nr_of_ports = 3;
4484 
parameter adr_size = 26;
4485 
parameter adr_lo   = 2;
4486 
parameter dat_size = 32;
4487 
parameter sel_size = dat_size/8;
4488 
 
4489 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4490 
localparam dw = dat_size * nr_of_ports;
4491 
localparam sw = sel_size * nr_of_ports;
4492 
localparam cw = 3 * nr_of_ports;
4493 
localparam bw = 2 * nr_of_ports;
4494 
 
4495 
input  [dw-1:0] wbm_dat_o;
4496 
input  [aw-1:0] wbm_adr_o;
4497 
input  [sw-1:0] wbm_sel_o;
4498 
input  [cw-1:0] wbm_cti_o;
4499 
input  [bw-1:0] wbm_bte_o;
4500 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4501 
output [dw-1:0] wbm_dat_i;
4502 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4503 
 
4504 
output [dat_size-1:0] wbs_dat_i;
4505 
output [adr_size-1:adr_lo] wbs_adr_i;
4506 
output [sel_size-1:0] wbs_sel_i;
4507 
output [2:0] wbs_cti_i;
4508 
output [1:0] wbs_bte_i;
4509 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4510 
input  [dat_size-1:0] wbs_dat_o;
4511 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4512 
 
4513 
input wb_clk, wb_rst;
4514 
 
4515 44 unneback 
reg  [nr_of_ports-1:0] select;
4516 39 unneback 
wire [nr_of_ports-1:0] state;
4517 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4518 
wire [nr_of_ports-1:0] sel;
4519 
wire idle;
4520 
 
4521 
genvar i;
4522 
 
4523 
assign idle = !(|state);
4524 
 
4525 
generate
4526 
if (nr_of_ports == 2) begin
4527 
 
4528 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4529 
 
4530 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4531 
 
4532 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4533 
 
4534 
    always @ (idle or wbm_cyc_o)
4535 
    if (idle)
4536 
        casex (wbm_cyc_o)
4537 
        2'b1x : select = 2'b10;
4538 
        2'b01 : select = 2'b01;
4539 
        default : select = {nr_of_ports{1'b0}};
4540 
        endcase
4541 
    else
4542 
        select = {nr_of_ports{1'b0}};
4543 
 
4544 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4545 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4546 
 
4547 
end
4548 
endgenerate
4549 
 
4550 
generate
4551 
if (nr_of_ports == 3) begin
4552 
 
4553 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4554 
 
4555 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4556 
 
4557 44 unneback 
    always @ (idle or wbm_cyc_o)
4558 
    if (idle)
4559 
        casex (wbm_cyc_o)
4560 
        3'b1xx : select = 3'b100;
4561 
        3'b01x : select = 3'b010;
4562 
        3'b001 : select = 3'b001;
4563 
        default : select = {nr_of_ports{1'b0}};
4564 
        endcase
4565 
    else
4566 
        select = {nr_of_ports{1'b0}};
4567 
 
4568 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4569 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4570 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4571 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4572 
 
4573 
end
4574 
endgenerate
4575 
 
4576 
generate
4577 44 unneback 
if (nr_of_ports == 4) begin
4578 
 
4579 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4580 
 
4581 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4582 
 
4583 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4584 
 
4585 
    always @ (idle or wbm_cyc_o)
4586 
    if (idle)
4587 
        casex (wbm_cyc_o)
4588 
        4'b1xxx : select = 4'b1000;
4589 
        4'b01xx : select = 4'b0100;
4590 
        4'b001x : select = 4'b0010;
4591 
        4'b0001 : select = 4'b0001;
4592 
        default : select = {nr_of_ports{1'b0}};
4593 
        endcase
4594 
    else
4595 
        select = {nr_of_ports{1'b0}};
4596 
 
4597 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4598 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4599 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4600 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4601 
 
4602 
end
4603 
endgenerate
4604 
 
4605 
generate
4606 
if (nr_of_ports == 5) begin
4607 
 
4608 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4609 
 
4610 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4611 
 
4612 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4613 
 
4614 
    always @ (idle or wbm_cyc_o)
4615 
    if (idle)
4616 
        casex (wbm_cyc_o)
4617 
        5'b1xxxx : select = 5'b10000;
4618 
        5'b01xxx : select = 5'b01000;
4619 
        5'b001xx : select = 5'b00100;
4620 
        5'b0001x : select = 5'b00010;
4621 
        5'b00001 : select = 5'b00001;
4622 
        default : select = {nr_of_ports{1'b0}};
4623 
        endcase
4624 
    else
4625 
        select = {nr_of_ports{1'b0}};
4626 
 
4627 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4628 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4629 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4630 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4631 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4632 
 
4633 
end
4634 
endgenerate
4635 
 
4636 
generate
4637 39 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin
4638 42 unneback 
`define MODULE spr
4639 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4640 
`undef MODULE
4641 39 unneback 
end
4642 
endgenerate
4643 
 
4644 
    assign sel = select | state;
4645 
 
4646 40 unneback 
`define MODULE mux_andor
4647 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4648 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4649 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4650 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4651 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4652 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4653 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4654 
`undef MODULE
4655 39 unneback 
    assign wbs_cyc_i = |sel;
4656 
 
4657 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4658 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4659 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4660 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4661 
 
4662 
endmodule
4663 40 unneback 
`endif
4664 39 unneback 
 
4665 60 unneback 
`ifdef WB_B3_RAM_BE
4666 49 unneback 
// WB RAM with byte enable
4667 59 unneback 
`define MODULE wb_b3_ram_be
4668 
module `BASE`MODULE (
4669 
`undef MODULE
4670 
    wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4671 
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
4672 
 
4673 60 unneback 
parameter nr_of_ports = 3;
4674 
parameter wb_arbiter_type = 1;
4675 
parameter adr_size = 26;
4676 
parameter adr_lo   = 2;
4677 
parameter dat_size = 32;
4678 
parameter memory_init = 1;
4679 
parameter memory_file = "vl_ram.vmem";
4680 59 unneback 
 
4681 60 unneback 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4682 
localparam dw = dat_size * nr_of_ports;
4683 
localparam sw = dat_size/8 * nr_of_ports;
4684 
localparam cw = 3 * nr_of_ports;
4685 
localparam bw = 2 * nr_of_ports;
4686 
 
4687 
input [dw-1:0] wb_dat_i;
4688 
input [aw-1:0] wb_adr_i;
4689 
input [cw-1:0] wb_cti_i;
4690 
input [sw-1:0] wb_sel_i;
4691 
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
4692 
output [dw-1:0] wb_dat_o;
4693 
reg [dw-1:0] wb_dat_o;
4694 59 unneback 
output wb_ack_o;
4695 
reg wb_ack_o;
4696 
input wb_clk, wb_rst;
4697 
 
4698 60 unneback 
wire [sw-1:0] cke;
4699 59 unneback 
 
4700 60 unneback 
// local wb slave
4701 
wire [dat_size-1:0] wbs_dat_i;
4702 
wire [adr_size-1:0] wbs_adr_i;
4703 
wire [2:0] wbs_cti_i;
4704 
wire [(dat_size/8)-1:0] wbs_sel_i;
4705 
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
4706 
wire [dat_size-1:0] wbs_dat_o;
4707 
reg wbs_ack_o;
4708 
 
4709 59 unneback 
generate
4710 60 unneback 
if (nr_of_ports == 1) begin
4711 
    assign wbs_dat_i = wb_dat_i;
4712 
    assign wbs_adr_i = wb_adr_i;
4713 
    assign wbs_cti_i = wb_cti_i;
4714 
    assign wbs_sel_i = wb_sel_i;
4715 
    assign wbs_we_i  = wb_we_i;
4716 
    assign wbs_stb_i = wb_stb_i;
4717 
    assign wbs_cyc_i = wb_cyc_i;
4718 
    assign wb_dat_o  = wbs_dat_o;
4719 
    assign wb_ack_o  = wbs_ack_o;
4720 59 unneback 
end
4721 
endgenerate
4722 
 
4723 60 unneback 
generate
4724 
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
4725 
`define MODULE wb3_arbiter_type1
4726 
`BASE`MODULE wb_arbiter0(
4727 
`undef MODULE
4728 
    .wbm_dat_o(wb_dat_i),
4729 
    .wbm_adr_o(wb_adr_i),
4730 
    .wbm_sel_o(wb_sel_i),
4731 
    .wbm_cti_o(wb_cti_i),
4732 
    .wbm_bte_o(wb_bte_i),
4733 
    .wbm_we_o(wb_we_i),
4734 
    .wbm_stb_o(wb_stb_i),
4735 
    .wbm_cyc_o(wb_cyc_i),
4736 
    .wbm_dat_i(wb_dat_o),
4737 
    .wbm_ack_i(wb_ack_o),
4738 
    .wbm_err_i(),
4739 
    .wbm_rty_i(),
4740 
    .wbs_dat_i(wbs_dat_i),
4741 
    .wbs_adr_i(wbs_adr_i),
4742 
    .wbs_sel_i(wbs_sel_i),
4743 
    .wbs_cti_i(wbs_cti_i),
4744 
    .wbs_bte_i(wbs_bte_i),
4745 
    .wbs_we_i(wbs_we_i),
4746 
    .wbs_stb_i(wbs_stb_i),
4747 
    .wbs_cyc_i(wbs_cyc_i),
4748 
    .wbs_dat_o(wbs_dat_o),
4749 
    .wbs_ack_o(wbs_ack_o),
4750 
    .wbs_err_o(1'b0),
4751 
    .wbs_rty_o(1'b0),
4752 
    .wb_clk(wb_clk),
4753 
    .wb_rst(wb_rst)
4754 
);
4755 
end
4756 
endgenerate
4757 
 
4758 
`define MODULE ram_be
4759 
`BASE`MODULE # (
4760 
    .data_width(dat_size),
4761 
    .addr_width(adr_size),
4762 
    .memory_init(1),
4763 
    .memory_file("memory_file"))
4764 
ram0(
4765 
`undef MODULE
4766 
    .d(wbs_dat_i),
4767 
    .adr(wbs_adr_i[adr_size-1:2]),
4768 
    .be(wbs_sel_i),
4769 
    .we(wbs_we_i),
4770 
    .q(wbs_dat_o),
4771 
    .clk(wb_clk)
4772 
);
4773 
 
4774 59 unneback 
always @ (posedge wb_clk or posedge wb_rst)
4775 
if (wb_rst)
4776 60 unneback 
    wbs_ack_o <= 1'b0;
4777 59 unneback 
else
4778 60 unneback 
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
4779 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
4780 59 unneback 
    else
4781 60 unneback 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
4782 
 
4783 59 unneback 
endmodule
4784 
`endif
4785 
 
4786 
`ifdef WB_B4_RAM_BE
4787 
// WB RAM with byte enable
4788 49 unneback 
`define MODULE wb_b4_ram_be
4789 
module `BASE`MODULE (
4790 
`undef MODULE
4791 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4792 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
4793 49 unneback 
 
4794 
    parameter dat_width = 32;
4795 
    parameter adr_width = 8;
4796 
 
4797 
input [dat_width-1:0] wb_dat_i;
4798 
input [adr_width-1:0] wb_adr_i;
4799 
input [dat_width/8-1:0] wb_sel_i;
4800 
input wb_we_i, wb_stb_i, wb_cyc_i;
4801 
output [dat_width-1:0] wb_dat_o;
4802 51 unneback 
reg [dat_width-1:0] wb_dat_o;
4803 52 unneback 
output wb_stall_o;
4804 49 unneback 
output wb_ack_o;
4805 
reg wb_ack_o;
4806 
input wb_clk, wb_rst;
4807 
 
4808 56 unneback 
wire [dat_width/8-1:0] cke;
4809 
 
4810 49 unneback 
generate
4811 
if (dat_width==32) begin
4812 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
4813 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
4814 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
4815 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
4816 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
4817 49 unneback 
    always @ (posedge wb_clk)
4818 
    begin
4819 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
4820 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
4821 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
4822 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
4823 49 unneback 
    end
4824 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
4825 
    begin
4826 
        if (wb_rst)
4827 
            wb_dat_o <= 32'h0;
4828 
        else
4829 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
4830 
    end
4831 49 unneback 
end
4832 
endgenerate
4833 
 
4834 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
4835 55 unneback 
if (wb_rst)
4836 52 unneback 
    wb_ack_o <= 1'b0;
4837 
else
4838 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
4839 52 unneback 
 
4840 
assign wb_stall_o = 1'b0;
4841 
 
4842 49 unneback 
endmodule
4843 
`endif
4844 
 
4845 48 unneback 
`ifdef WB_B4_ROM
4846 
// WB ROM
4847 
`define MODULE wb_b4_rom
4848 
module `BASE`MODULE (
4849 
`undef MODULE
4850 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4851 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4852 
 
4853 
    parameter dat_width = 32;
4854 
    parameter dat_default = 32'h15000000;
4855 
    parameter adr_width = 32;
4856 
 
4857 
/*
4858 
`ifndef ROM
4859 
`define ROM "rom.v"
4860 
`endif
4861 
*/
4862 
    input [adr_width-1:2]   wb_adr_i;
4863 
    input                   wb_stb_i;
4864 
    input                   wb_cyc_i;
4865 
    output [dat_width-1:0]  wb_dat_o;
4866 
    reg [dat_width-1:0]     wb_dat_o;
4867 
    output                  wb_ack_o;
4868 
    reg                     wb_ack_o;
4869 
    output                  stall_o;
4870 
    input                   wb_clk;
4871 
    input                   wb_rst;
4872 
 
4873 
always @ (posedge wb_clk or posedge wb_rst)
4874 
    if (wb_rst)
4875 
        wb_dat_o <= {dat_width{1'b0}};
4876 
    else
4877 
         case (wb_adr_i[adr_width-1:2])
4878 
`ifdef ROM
4879 
`include `ROM
4880 
`endif
4881 
           default:
4882 
             wb_dat_o <= dat_default;
4883 
 
4884 
         endcase // case (wb_adr_i)
4885 
 
4886 
 
4887 
always @ (posedge wb_clk or posedge wb_rst)
4888 
    if (wb_rst)
4889 
        wb_ack_o <= 1'b0;
4890 
    else
4891 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4892 
 
4893 
assign stall_o = 1'b0;
4894 
 
4895 
endmodule
4896 
`endif
4897 
 
4898 
 
4899 40 unneback 
`ifdef WB_BOOT_ROM
4900 17 unneback 
// WB ROM
4901 40 unneback 
`define MODULE wb_boot_rom
4902 
module `BASE`MODULE (
4903 
`undef MODULE
4904 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4905 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4906 17 unneback 
 
4907 18 unneback 
    parameter adr_hi = 31;
4908 
    parameter adr_lo = 28;
4909 
    parameter adr_sel = 4'hf;
4910 
    parameter addr_width = 5;
4911 33 unneback 
/*
4912 17 unneback 
`ifndef BOOT_ROM
4913 
`define BOOT_ROM "boot_rom.v"
4914 
`endif
4915 33 unneback 
*/
4916 18 unneback 
    input [adr_hi:2]    wb_adr_i;
4917 
    input               wb_stb_i;
4918 
    input               wb_cyc_i;
4919 
    output [31:0]        wb_dat_o;
4920 
    output              wb_ack_o;
4921 
    output              hit_o;
4922 
    input               wb_clk;
4923 
    input               wb_rst;
4924 
 
4925 
    wire hit;
4926 
    reg [31:0] wb_dat;
4927 
    reg wb_ack;
4928 
 
4929 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4930 17 unneback 
 
4931 
always @ (posedge wb_clk or posedge wb_rst)
4932 
    if (wb_rst)
4933 18 unneback 
        wb_dat <= 32'h15000000;
4934 17 unneback 
    else
4935 18 unneback 
         case (wb_adr_i[addr_width-1:2])
4936 33 unneback 
`ifdef BOOT_ROM
4937 17 unneback 
`include `BOOT_ROM
4938 33 unneback 
`endif
4939 17 unneback 
           /*
4940 
            // Zero r0 and jump to 0x00000100
4941 18 unneback 
 
4942 
            1 : wb_dat <= 32'hA8200000;
4943 
            2 : wb_dat <= 32'hA8C00100;
4944 
            3 : wb_dat <= 32'h44003000;
4945 
            4 : wb_dat <= 32'h15000000;
4946 17 unneback 
            */
4947 
           default:
4948 18 unneback 
             wb_dat <= 32'h00000000;
4949 17 unneback 
 
4950 
         endcase // case (wb_adr_i)
4951 
 
4952 
 
4953 
always @ (posedge wb_clk or posedge wb_rst)
4954 
    if (wb_rst)
4955 18 unneback 
        wb_ack <= 1'b0;
4956 17 unneback 
    else
4957 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4958 17 unneback 
 
4959 18 unneback 
assign hit_o = hit;
4960 
assign wb_dat_o = wb_dat & {32{wb_ack}};
4961 
assign wb_ack_o = wb_ack;
4962 
 
4963 17 unneback 
endmodule
4964 40 unneback 
`endif
4965 32 unneback 
 
4966 40 unneback 
`ifdef WB_DPRAM
4967 
`define MODULE wb_dpram
4968 
module `BASE`MODULE (
4969 
`undef MODULE
4970 32 unneback 
        // wishbone slave side a
4971 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4972 
        wbsa_clk, wbsa_rst,
4973 
        // wishbone slave side a
4974 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4975 
        wbsb_clk, wbsb_rst);
4976 
 
4977 
parameter data_width = 32;
4978 
parameter addr_width = 8;
4979 
 
4980 
parameter dat_o_mask_a = 1;
4981 
parameter dat_o_mask_b = 1;
4982 
 
4983 
input [31:0] wbsa_dat_i;
4984 
input [addr_width-1:2] wbsa_adr_i;
4985 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4986 
output [31:0] wbsa_dat_o;
4987 
output wbsa_ack_o;
4988 
input wbsa_clk, wbsa_rst;
4989 
 
4990 
input [31:0] wbsb_dat_i;
4991 
input [addr_width-1:2] wbsb_adr_i;
4992 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4993 
output [31:0] wbsb_dat_o;
4994 
output wbsb_ack_o;
4995 
input wbsb_clk, wbsb_rst;
4996 
 
4997 
wire wbsa_dat_tmp, wbsb_dat_tmp;
4998 
 
4999 40 unneback 
`define MODULE dpram_2r2w
5000 
`BASE`MODULE # (
5001 
`undef MODULE
5002 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
5003 32 unneback 
dpram0(
5004 
    .d_a(wbsa_dat_i),
5005 
    .q_a(wbsa_dat_tmp),
5006 
    .adr_a(wbsa_adr_i),
5007 
    .we_a(wbsa_we_i),
5008 
    .clk_a(wbsa_clk),
5009 
    .d_b(wbsb_dat_i),
5010 
    .q_b(wbsb_dat_tmp),
5011 
    .adr_b(wbsb_adr_i),
5012 
    .we_b(wbsb_we_i),
5013 
    .clk_b(wbsb_clk) );
5014 
 
5015 33 unneback 
generate if (dat_o_mask_a==1)
5016 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
5017 
endgenerate
5018 33 unneback 
generate if (dat_o_mask_a==0)
5019 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
5020 
endgenerate
5021 
 
5022 33 unneback 
generate if (dat_o_mask_b==1)
5023 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
5024 
endgenerate
5025 33 unneback 
generate if (dat_o_mask_b==0)
5026 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
5027 
endgenerate
5028 
 
5029 40 unneback 
`define MODULE spr
5030 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
5031 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
5032 
`undef MODULE
5033 32 unneback 
 
5034 
endmodule
5035 40 unneback 
`endif
5036 18 unneback 
//////////////////////////////////////////////////////////////////////
5037 
////                                                              ////
5038 
////  Arithmetic functions                                        ////
5039 
////                                                              ////
5040 
////  Description                                                 ////
5041 
////  Arithmetic functions for ALU and DSP                        ////
5042 
////                                                              ////
5043 
////                                                              ////
5044 
////  To Do:                                                      ////
5045 
////   -                                                          ////
5046 
////                                                              ////
5047 
////  Author(s):                                                  ////
5048 
////      - Michael Unneback, unneback@opencores.org              ////
5049 
////        ORSoC AB                                              ////
5050 
////                                                              ////
5051 
//////////////////////////////////////////////////////////////////////
5052 
////                                                              ////
5053 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5054 
////                                                              ////
5055 
//// This source file may be used and distributed without         ////
5056 
//// restriction provided that this copyright statement is not    ////
5057 
//// removed from the file and that any derivative work contains  ////
5058 
//// the original copyright notice and the associated disclaimer. ////
5059 
////                                                              ////
5060 
//// This source file is free software; you can redistribute it   ////
5061 
//// and/or modify it under the terms of the GNU Lesser General   ////
5062 
//// Public License as published by the Free Software Foundation; ////
5063 
//// either version 2.1 of the License, or (at your option) any   ////
5064 
//// later version.                                               ////
5065 
////                                                              ////
5066 
//// This source is distributed in the hope that it will be       ////
5067 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5068 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5069 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5070 
//// details.                                                     ////
5071 
////                                                              ////
5072 
//// You should have received a copy of the GNU Lesser General    ////
5073 
//// Public License along with this source; if not, download it   ////
5074 
//// from http://www.opencores.org/lgpl.shtml                     ////
5075 
////                                                              ////
5076 
//////////////////////////////////////////////////////////////////////
5077 
 
5078 40 unneback 
`ifdef MULTS
5079 18 unneback 
// signed multiplication
5080 40 unneback 
`define MODULE mults
5081 
module `BASE`MODULE (a,b,p);
5082 
`undef MODULE
5083 18 unneback 
parameter operand_a_width = 18;
5084 
parameter operand_b_width = 18;
5085 
parameter result_hi = 35;
5086 
parameter result_lo = 0;
5087 
input [operand_a_width-1:0] a;
5088 
input [operand_b_width-1:0] b;
5089 
output [result_hi:result_lo] p;
5090 
wire signed [operand_a_width-1:0] ai;
5091 
wire signed [operand_b_width-1:0] bi;
5092 
wire signed [operand_a_width+operand_b_width-1:0] result;
5093 
 
5094 
    assign ai = a;
5095 
    assign bi = b;
5096 
    assign result = ai * bi;
5097 
    assign p = result[result_hi:result_lo];
5098 
 
5099 
endmodule
5100 40 unneback 
`endif
5101 
`ifdef MULTS18X18
5102 
`define MODULE mults18x18
5103 
module `BASE`MODULE (a,b,p);
5104 
`undef MODULE
5105 18 unneback 
input [17:0] a,b;
5106 
output [35:0] p;
5107 
vl_mult
5108 
    # (.operand_a_width(18), .operand_b_width(18))
5109 
    mult0 (.a(a), .b(b), .p(p));
5110 
endmodule
5111 40 unneback 
`endif
5112 18 unneback 
 
5113 40 unneback 
`ifdef MULT
5114 
`define MODULE mult
5115 18 unneback 
// unsigned multiplication
5116 40 unneback 
module `BASE`MODULE (a,b,p);
5117 
`undef MODULE
5118 18 unneback 
parameter operand_a_width = 18;
5119 
parameter operand_b_width = 18;
5120 
parameter result_hi = 35;
5121 
parameter result_lo = 0;
5122 
input [operand_a_width-1:0] a;
5123 
input [operand_b_width-1:0] b;
5124 
output [result_hi:result_hi] p;
5125 
 
5126 
wire [operand_a_width+operand_b_width-1:0] result;
5127 
 
5128 
    assign result = a * b;
5129 
    assign p = result[result_hi:result_lo];
5130 
 
5131 
endmodule
5132 40 unneback 
`endif
5133 18 unneback 
 
5134 40 unneback 
`ifdef SHIFT_UNIT_32
5135 
`define MODULE shift_unit_32
5136 18 unneback 
// shift unit
5137 
// supporting the following shift functions
5138 
//   SLL
5139 
//   SRL
5140 
//   SRA
5141 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5142 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
5143 
`undef MODULE
5144 18 unneback 
input [31:0] din; // data in operand
5145 
input [4:0] s; // shift operand
5146 
input [1:0] opcode;
5147 
output [31:0] dout;
5148 
 
5149 
parameter opcode_sll = 2'b00;
5150 
//parameter opcode_srl = 2'b01;
5151 
parameter opcode_sra = 2'b10;
5152 
//parameter opcode_ror = 2'b11;
5153 
 
5154 
wire sll, sra;
5155 
assign sll = opcode == opcode_sll;
5156 
assign sra = opcode == opcode_sra;
5157 
 
5158 
wire [15:1] s1;
5159 
wire [3:0] sign;
5160 
wire [7:0] tmp [0:3];
5161 
 
5162 
// first stage is multiplier based
5163 
// shift operand as fractional 8.7
5164 
assign s1[15] = sll & s[2:0]==3'd7;
5165 
assign s1[14] = sll & s[2:0]==3'd6;
5166 
assign s1[13] = sll & s[2:0]==3'd5;
5167 
assign s1[12] = sll & s[2:0]==3'd4;
5168 
assign s1[11] = sll & s[2:0]==3'd3;
5169 
assign s1[10] = sll & s[2:0]==3'd2;
5170 
assign s1[ 9] = sll & s[2:0]==3'd1;
5171 
assign s1[ 8] = s[2:0]==3'd0;
5172 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5173 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5174 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5175 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5176 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5177 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5178 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5179 
 
5180 
assign sign[3] = din[31] & sra;
5181 
assign sign[2] = sign[3] & (&din[31:24]);
5182 
assign sign[1] = sign[2] & (&din[23:16]);
5183 
assign sign[0] = sign[1] & (&din[15:8]);
5184 40 unneback 
`define MODULE mults
5185 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5186 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5187 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5188 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5189 
`undef MODULE
5190 18 unneback 
// second stage is multiplexer based
5191 
// shift on byte level
5192 
 
5193 
// mux byte 3
5194 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5195 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5196 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5197 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5198 
                     {8{sign[3]}};
5199 
 
5200 
// mux byte 2
5201 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5202 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5203 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5204 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5205 
                     (s[4:3]==2'b01) ? tmp[3] :
5206 
                     {8{sign[3]}};
5207 
 
5208 
// mux byte 1
5209 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5210 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5211 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5212 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5213 
                     (s[4:3]==2'b01) ? tmp[2] :
5214 
                     (s[4:3]==2'b10) ? tmp[3] :
5215 
                     {8{sign[3]}};
5216 
 
5217 
// mux byte 0
5218 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5219 
                     (sll) ?  {8{1'b0}}:
5220 
                     (s[4:3]==2'b01) ? tmp[1] :
5221 
                     (s[4:3]==2'b10) ? tmp[2] :
5222 
                     tmp[3];
5223 
 
5224 
endmodule
5225 40 unneback 
`endif
5226 18 unneback 
 
5227 40 unneback 
`ifdef LOGIC_UNIT
5228 18 unneback 
// logic unit
5229 
// supporting the following logic functions
5230 
//    a and b
5231 
//    a or  b
5232 
//    a xor b
5233 
//    not b
5234 40 unneback 
`define MODULE logic_unit
5235 
module `BASE`MODULE( a, b, result, opcode);
5236 
`undef MODULE
5237 18 unneback 
parameter width = 32;
5238 
parameter opcode_and = 2'b00;
5239 
parameter opcode_or  = 2'b01;
5240 
parameter opcode_xor = 2'b10;
5241 
input [width-1:0] a,b;
5242 
output [width-1:0] result;
5243 
input [1:0] opcode;
5244 
 
5245 
assign result = (opcode==opcode_and) ? a & b :
5246 
                (opcode==opcode_or)  ? a | b :
5247 
                (opcode==opcode_xor) ? a ^ b :
5248 
                b;
5249 
 
5250 
endmodule
5251 48 unneback 
`endif
5252 18 unneback 
 
5253 48 unneback 
`ifdef ARITH_UNIT
5254 
`define MODULE arith_unit
5255 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5256 
`undef MODULE
5257 18 unneback 
parameter width = 32;
5258 
parameter opcode_add = 1'b0;
5259 
parameter opcode_sub = 1'b1;
5260 
input [width-1:0] a,b;
5261 
input c_in, add_sub, sign;
5262 
output [width-1:0] result;
5263 
output c_out, z, ovfl;
5264 
 
5265 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5266 
assign z = (result=={width{1'b0}});
5267 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5268 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5269 
endmodule
5270 40 unneback 
`endif
5271 48 unneback 
 
5272 
`ifdef COUNT_UNIT
5273 
`define MODULE count_unit
5274 
module `BASE`MODULE (din, dout, opcode);
5275 
`undef MODULE
5276 
parameter width = 32;
5277 
input [width-1:0] din;
5278 
output [width-1:0] dout;
5279 
input opcode;
5280 
 
5281 
integer i;
5282 58 unneback 
wire [width/32+4:0] ff1, fl1;
5283 48 unneback 
 
5284 57 unneback 
/*
5285 48 unneback 
always @(din) begin
5286 
    ff1 = 0; i = 0;
5287 
    while (din[i] == 0 && i < width) begin // complex condition
5288 
        ff1 = ff1 + 1;
5289 
        i = i + 1;
5290 
    end
5291 
end
5292 
 
5293 
always @(din) begin
5294 
    fl1 = width; i = width-1;
5295 
    while (din[i] == 0 && i >= width) begin // complex condition
5296 
        fl1 = fl1 - 1;
5297 
        i = i - 1;
5298 
    end
5299 
end
5300 57 unneback 
*/
5301 48 unneback 
 
5302 
generate
5303 
if (width==32) begin
5304 57 unneback 
 
5305 
    assign ff1 = din[0] ? 6'd1 :
5306 
                 din[1] ? 6'd2 :
5307 
                 din[2] ? 6'd3 :
5308 
                 din[3] ? 6'd4 :
5309 
                 din[4] ? 6'd5 :
5310 
                 din[5] ? 6'd6 :
5311 
                 din[6] ? 6'd7 :
5312 
                 din[7] ? 6'd8 :
5313 
                 din[8] ? 6'd9 :
5314 
                 din[9] ? 6'd10 :
5315 
                 din[10] ? 6'd11 :
5316 
                 din[11] ? 6'd12 :
5317 
                 din[12] ? 6'd13 :
5318 
                 din[13] ? 6'd14 :
5319 
                 din[14] ? 6'd15 :
5320 
                 din[15] ? 6'd16 :
5321 
                 din[16] ? 6'd17 :
5322 
                 din[17] ? 6'd18 :
5323 
                 din[18] ? 6'd19 :
5324 
                 din[19] ? 6'd20 :
5325 
                 din[20] ? 6'd21 :
5326 
                 din[21] ? 6'd22 :
5327 
                 din[22] ? 6'd23 :
5328 
                 din[23] ? 6'd24 :
5329 
                 din[24] ? 6'd25 :
5330 
                 din[25] ? 6'd26 :
5331 
                 din[26] ? 6'd27 :
5332 
                 din[27] ? 6'd28 :
5333 
                 din[28] ? 6'd29 :
5334 
                 din[29] ? 6'd30 :
5335 
                 din[30] ? 6'd31 :
5336 
                 din[31] ? 6'd32 :
5337 
                 6'd0;
5338 
 
5339 
    assign fl1 = din[31] ? 6'd32 :
5340 
                 din[30] ? 6'd31 :
5341 
                 din[29] ? 6'd30 :
5342 
                 din[28] ? 6'd29 :
5343 
                 din[27] ? 6'd28 :
5344 
                 din[26] ? 6'd27 :
5345 
                 din[25] ? 6'd26 :
5346 
                 din[24] ? 6'd25 :
5347 
                 din[23] ? 6'd24 :
5348 
                 din[22] ? 6'd23 :
5349 
                 din[21] ? 6'd22 :
5350 
                 din[20] ? 6'd21 :
5351 
                 din[19] ? 6'd20 :
5352 
                 din[18] ? 6'd19 :
5353 
                 din[17] ? 6'd18 :
5354 
                 din[16] ? 6'd17 :
5355 
                 din[15] ? 6'd16 :
5356 
                 din[14] ? 6'd15 :
5357 
                 din[13] ? 6'd14 :
5358 
                 din[12] ? 6'd13 :
5359 
                 din[11] ? 6'd12 :
5360 
                 din[10] ? 6'd11 :
5361 
                 din[9] ? 6'd10 :
5362 
                 din[8] ? 6'd9 :
5363 
                 din[7] ? 6'd8 :
5364 
                 din[6] ? 6'd7 :
5365 
                 din[5] ? 6'd6 :
5366 
                 din[4] ? 6'd5 :
5367 
                 din[3] ? 6'd4 :
5368 
                 din[2] ? 6'd3 :
5369 
                 din[1] ? 6'd2 :
5370 
                 din[0] ? 6'd1 :
5371 
                 6'd0;
5372 
 
5373 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5374 48 unneback 
end
5375 
endgenerate
5376 57 unneback 
 
5377 48 unneback 
generate
5378 
if (width==64) begin
5379 57 unneback 
    assign ff1 = 7'd0;
5380 
    assign fl1 = 7'd0;
5381 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5382 48 unneback 
end
5383 
endgenerate
5384 
 
5385 
endmodule
5386 
`endif
5387 
 
5388 
`ifdef EXT_UNIT
5389 
`define MODULE ext_unit
5390 
module `BASE`MODULE ( a, b, F, result, opcode);
5391 
`undef MODULE
5392 
parameter width = 32;
5393 
input [width-1:0] a, b;
5394 
input F;
5395 
output reg [width-1:0] result;
5396 
input [2:0] opcode;
5397 
 
5398 
generate
5399 
if (width==32) begin
5400 
always @ (a or b or F or opcode)
5401 
begin
5402 
    case (opcode)
5403 
    3'b000: result = {{24{1'b0}},a[7:0]};
5404 
    3'b001: result = {{24{a[7]}},a[7:0]};
5405 
    3'b010: result = {{16{1'b0}},a[7:0]};
5406 
    3'b011: result = {{16{a[15]}},a[15:0]};
5407 
    3'b110: result = (F) ? a : b;
5408 
    default: result = {b[15:0],16'h0000};
5409 
    endcase
5410 
end
5411 
end
5412 
endgenerate
5413 
 
5414 
generate
5415 
if (width==64) begin
5416 
always @ (a or b or F or opcode)
5417 
begin
5418 
    case (opcode)
5419 
    3'b000: result = {{56{1'b0}},a[7:0]};
5420 
    3'b001: result = {{56{a[7]}},a[7:0]};
5421 
    3'b010: result = {{48{1'b0}},a[7:0]};
5422 
    3'b011: result = {{48{a[15]}},a[15:0]};
5423 57 unneback 
    3'b110: result = (F) ? a : b;
5424 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
5425 
    endcase
5426 
end
5427 
end
5428 
endgenerate
5429 
endmodule
5430 
`endif

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