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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 91

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 75 unneback 
`define DPRAM_BE_2R2W
45 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
46 
`define FIFO_2R2W_SYNC_SIMPLEX
47 
`define FIFO_CMP_ASYNC
48 
`define FIFO_1R1W_ASYNC
49 
`define FIFO_2R2W_ASYNC
50 
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback 
`define REG_FILE
52 40 unneback 
 
53 
`define DFF
54 
`define DFF_ARRAY
55 
`define DFF_CE
56 
`define DFF_CE_CLEAR
57 
`define DF_CE_SET
58 
`define SPR
59 
`define SRP
60 
`define DFF_SR
61 
`define LATCH
62 
`define SHREG
63 
`define SHREG_CE
64 
`define DELAY
65 
`define DELAY_EMPTYFLAG
66 
 
67 75 unneback 
`define WB3AVALON_BRIDGE
68 40 unneback 
`define WB3WB3_BRIDGE
69 
`define WB3_ARBITER_TYPE1
70 83 unneback 
`define WB_ADR_INC
71 59 unneback 
`define WB_B3_RAM_BE
72 49 unneback 
`define WB_B4_RAM_BE
73 48 unneback 
`define WB_B4_ROM
74 40 unneback 
`define WB_BOOT_ROM
75 
`define WB_DPRAM
76 
 
77 44 unneback 
`define IO_DFF_OE
78 
`define O_DFF
79 
 
80 40 unneback 
`endif
81 
 
82 
`ifdef PLL
83 
`ifndef SYNC_RST
84 
`define SYNC_RST
85 
`endif
86 
`endif
87 
 
88 
`ifdef SYNC_RST
89 
`ifndef GBUF
90 
`define GBUF
91 
`endif
92 
`endif
93 
 
94 
`ifdef WB_DPRAM
95 
`ifndef DPRAM_2R2W
96 
`define DPRAM_2R2W
97 
`endif
98 
`ifndef SPR
99 
`define SPR
100 
`endif
101 
`endif
102 
 
103 62 unneback 
`ifdef WB_B3_RAM_BE
104 83 unneback 
`ifndef WB_ADR_INC
105 
`define WB_ADR_INC
106 62 unneback 
`endif
107 
`ifndef RAM_BE
108 
`define RAM_BE
109 
`endif
110 
`endif
111 
 
112 40 unneback 
`ifdef WB3_ARBITER_TYPE1
113 42 unneback 
`ifndef SPR
114 
`define SPR
115 
`endif
116 40 unneback 
`ifndef MUX_ANDOR
117 
`define MUX_ANDOR
118 
`endif
119 
`endif
120 
 
121 76 unneback 
`ifdef WB3AVALON_BRIDGE
122 
`ifndef WB3WB3_BRIDGE
123 
`define WB3WB3_BRIDGE
124 
`endif
125 
`endif
126 
 
127 40 unneback 
`ifdef WB3WB3_BRIDGE
128 
`ifndef CNT_SHREG_CE_CLEAR
129 
`define CNT_SHREG_CE_CLEAR
130 
`endif
131 
`ifndef DFF
132 
`define DFF
133 
`endif
134 
`ifndef DFF_CE
135 
`define DFF_CE
136 
`endif
137 
`ifndef CNT_SHREG_CE_CLEAR
138 
`define CNT_SHREG_CE_CLEAR
139 
`endif
140 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
141 
`define FIFO_2R2W_ASYNC_SIMPLEX
142 
`endif
143 
`endif
144 
 
145 
`ifdef MULTS18X18
146 
`ifndef MULTS
147 
`define MULTS
148 
`endif
149 
`endif
150 
 
151 
`ifdef SHIFT_UNIT_32
152 
`ifndef MULTS
153 
`define MULTS
154 
`endif
155 
`endif
156 
 
157 
`ifdef MUX2_ANDOR
158 
`ifndef MUX_ANDOR
159 
`define MUX_ANDOR
160 
`endif
161 
`endif
162 
 
163 
`ifdef MUX3_ANDOR
164 
`ifndef MUX_ANDOR
165 
`define MUX_ANDOR
166 
`endif
167 
`endif
168 
 
169 
`ifdef MUX4_ANDOR
170 
`ifndef MUX_ANDOR
171 
`define MUX_ANDOR
172 
`endif
173 
`endif
174 
 
175 
`ifdef MUX5_ANDOR
176 
`ifndef MUX_ANDOR
177 
`define MUX_ANDOR
178 
`endif
179 
`endif
180 
 
181 
`ifdef MUX6_ANDOR
182 
`ifndef MUX_ANDOR
183 
`define MUX_ANDOR
184 
`endif
185 
`endif
186 
 
187 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
188 
`ifndef CNT_BIN_CE
189 
`define CNT_BIN_CE
190 
`endif
191 
`ifndef DPRAM_1R1W
192 
`define DPRAM_1R1W
193 
`endif
194 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
195 
`define CNT_BIN_CE_REW_Q_ZQ_L1
196 
`endif
197 
`endif
198 
 
199 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
200 
`ifndef CNT_LFSR_CE
201 
`define CNT_LFSR_CE
202 
`endif
203 
`ifndef DPRAM_2R2W
204 
`define DPRAM_2R2W
205 
`endif
206 
`ifndef CNT_BIN_CE_REW_ZQ_L1
207 
`define CNT_BIN_CE_REW_ZQ_L1
208 
`endif
209 
`endif
210 
 
211 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
212 
`ifndef CNT_GRAY_CE_BIN
213 
`define CNT_GRAY_CE_BIN
214 
`endif
215 
`ifndef DPRAM_2R2W
216 
`define DPRAM_2R2W
217 
`endif
218 
`ifndef FIFO_CMP_ASYNC
219 
`define FIFO_CMP_ASYNC
220 
`endif
221 
`endif
222 
 
223 
`ifdef FIFO_2R2W_ASYNC
224 
`ifndef FIFO_1R1W_ASYNC
225 
`define FIFO_1R1W_ASYNC
226 
`endif
227 
`endif
228 
 
229 
`ifdef FIFO_1R1W_ASYNC
230 
`ifndef CNT_GRAY_CE_BIN
231 
`define CNT_GRAY_CE_BIN
232 
`endif
233 
`ifndef DPRAM_1R1W
234 
`define DPRAM_1R1W
235 
`endif
236 
`ifndef FIFO_CMP_ASYNC
237 
`define FIFO_CMP_ASYNC
238 
`endif
239 
`endif
240 
 
241 
`ifdef FIFO_CMP_ASYNC
242 
`ifndef DFF_SR
243 
`define DFF_SR
244 
`endif
245 
`ifndef DFF
246 
`define DFF
247 
`endif
248 
`endif
249 48 unneback 
 
250 
`ifdef REG_FILE
251 
`ifndef DPRAM_1R1W
252 
`define DPRAM_1R1W
253 
`endif
254 
`endif
255 62 unneback 
//////////////////////////////////////////////////////////////////////
256 6 unneback 
////                                                              ////
257 
////  Versatile library, clock and reset                          ////
258 
////                                                              ////
259 
////  Description                                                 ////
260 
////  Logic related to clock and reset                            ////
261 
////                                                              ////
262 
////                                                              ////
263 
////  To Do:                                                      ////
264 
////   - add more different registers                             ////
265 
////                                                              ////
266 
////  Author(s):                                                  ////
267 
////      - Michael Unneback, unneback@opencores.org              ////
268 
////        ORSoC AB                                              ////
269 
////                                                              ////
270 
//////////////////////////////////////////////////////////////////////
271 
////                                                              ////
272 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
273 
////                                                              ////
274 
//// This source file may be used and distributed without         ////
275 
//// restriction provided that this copyright statement is not    ////
276 
//// removed from the file and that any derivative work contains  ////
277 
//// the original copyright notice and the associated disclaimer. ////
278 
////                                                              ////
279 
//// This source file is free software; you can redistribute it   ////
280 
//// and/or modify it under the terms of the GNU Lesser General   ////
281 
//// Public License as published by the Free Software Foundation; ////
282 
//// either version 2.1 of the License, or (at your option) any   ////
283 
//// later version.                                               ////
284 
////                                                              ////
285 
//// This source is distributed in the hope that it will be       ////
286 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
287 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
288 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
289 
//// details.                                                     ////
290 
////                                                              ////
291 
//// You should have received a copy of the GNU Lesser General    ////
292 
//// Public License along with this source; if not, download it   ////
293 
//// from http://www.opencores.org/lgpl.shtml                     ////
294 
////                                                              ////
295 
//////////////////////////////////////////////////////////////////////
296 
 
297 48 unneback 
`ifdef ACTEL
298 
`ifdef GBUF
299 
`timescale 1 ns/100 ps
300 6 unneback 
// Global buffer
301 
// usage:
302 
// use to enable global buffers for high fan out signals such as clock and reset
303 
// Version: 8.4 8.4.0.33
304 
module gbuf(GL,CLK);
305 
output GL;
306 
input  CLK;
307 
 
308 
    wire GND;
309 
 
310 
    GND GND_1_net(.Y(GND));
311 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
312 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
313 
 
314 
endmodule
315 
`timescale 1 ns/1 ns
316 40 unneback 
`define MODULE gbuf
317 
module `BASE`MODULE ( i, o);
318 
`undef MODULE
319 6 unneback 
input i;
320 
output o;
321 
`ifdef SIM_GBUF
322 
assign o=i;
323 
`else
324 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
325 
`endif
326 
endmodule
327 40 unneback 
`endif
328 33 unneback 
 
329 6 unneback 
`else
330 33 unneback 
 
331 40 unneback 
`ifdef ALTERA
332 
`ifdef GBUF
333 21 unneback 
//altera
334 40 unneback 
`define MODULE gbuf
335 
module `BASE`MODULE ( i, o);
336 
`undef MODULE
337 33 unneback 
input i;
338 
output o;
339 
assign o = i;
340 
endmodule
341 40 unneback 
`endif
342 33 unneback 
 
343 6 unneback 
`else
344 
 
345 40 unneback 
`ifdef GBUF
346 6 unneback 
`timescale 1 ns/100 ps
347 40 unneback 
`define MODULE
348 
module `BASE`MODULE ( i, o);
349 
`undef MODULE
350 6 unneback 
input i;
351 
output o;
352 
assign o = i;
353 
endmodule
354 40 unneback 
`endif
355 6 unneback 
`endif // ALTERA
356 
`endif //ACTEL
357 
 
358 40 unneback 
`ifdef SYNC_RST
359 6 unneback 
// sync reset
360 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
361 6 unneback 
// output active high global reset sync with two DFFs
362 
`timescale 1 ns/100 ps
363 40 unneback 
`define MODULE sync_rst
364 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
365 
`undef MODULE
366 6 unneback 
input rst_n_i, clk;
367 
output rst_o;
368 18 unneback 
reg [1:0] tmp;
369 6 unneback 
always @ (posedge clk or negedge rst_n_i)
370 
if (!rst_n_i)
371 17 unneback 
        tmp <= 2'b11;
372 6 unneback 
else
373 33 unneback 
        tmp <= {1'b0,tmp[1]};
374 40 unneback 
`define MODULE gbuf
375 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
376 
`undef MODULE
377 6 unneback 
endmodule
378 40 unneback 
`endif
379 6 unneback 
 
380 40 unneback 
`ifdef PLL
381 6 unneback 
// vl_pll
382 
`ifdef ACTEL
383 32 unneback 
///////////////////////////////////////////////////////////////////////////////
384 17 unneback 
`timescale 1 ps/1 ps
385 40 unneback 
`define MODULE pll
386 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
387 
`undef MODULE
388 6 unneback 
parameter index = 0;
389 
parameter number_of_clk = 1;
390 17 unneback 
parameter period_time_0 = 20000;
391 
parameter period_time_1 = 20000;
392 
parameter period_time_2 = 20000;
393 
parameter lock_delay = 2000000;
394 6 unneback 
input clk_i, rst_n_i;
395 
output lock;
396 
output reg [0:number_of_clk-1] clk_o;
397 
output [0:number_of_clk-1] rst_o;
398 
 
399 
`ifdef SIM_PLL
400 
 
401 
always
402 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
403 
 
404 
generate if (number_of_clk > 1)
405 
always
406 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
407 
endgenerate
408 
 
409 
generate if (number_of_clk > 2)
410 
always
411 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
412 
endgenerate
413 
 
414 
genvar i;
415 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
416 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
417 
end
418 
endgenerate
419 
 
420 
assign #lock_delay lock = rst_n_i;
421 
 
422 
endmodule
423 
`else
424 
generate if (number_of_clk==1 & index==0) begin
425 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
426 
end
427 
endgenerate // index==0
428 
generate if (number_of_clk==1 & index==1) begin
429 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
430 
end
431 
endgenerate // index==1
432 
generate if (number_of_clk==1 & index==2) begin
433 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
434 
end
435 
endgenerate // index==2
436 
generate if (number_of_clk==1 & index==3) begin
437 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
438 
end
439 
endgenerate // index==0
440 
 
441 
generate if (number_of_clk==2 & index==0) begin
442 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
443 
end
444 
endgenerate // index==0
445 
generate if (number_of_clk==2 & index==1) begin
446 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
447 
end
448 
endgenerate // index==1
449 
generate if (number_of_clk==2 & index==2) begin
450 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
451 
end
452 
endgenerate // index==2
453 
generate if (number_of_clk==2 & index==3) begin
454 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
455 
end
456 
endgenerate // index==0
457 
 
458 
generate if (number_of_clk==3 & index==0) begin
459 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
460 
end
461 
endgenerate // index==0
462 
generate if (number_of_clk==3 & index==1) begin
463 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
464 
end
465 
endgenerate // index==1
466 
generate if (number_of_clk==3 & index==2) begin
467 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
468 
end
469 
endgenerate // index==2
470 
generate if (number_of_clk==3 & index==3) begin
471 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
472 
end
473 
endgenerate // index==0
474 
 
475 
genvar i;
476 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
477 40 unneback 
`define MODULE sync_rst
478 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
479 
`undef MODULE
480 6 unneback 
end
481 
endgenerate
482 
endmodule
483 
`endif
484 32 unneback 
///////////////////////////////////////////////////////////////////////////////
485 6 unneback 
 
486 
`else
487 
 
488 32 unneback 
///////////////////////////////////////////////////////////////////////////////
489 6 unneback 
`ifdef ALTERA
490 
 
491 32 unneback 
`timescale 1 ps/1 ps
492 40 unneback 
`define MODULE pll
493 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
494 
`undef MODULE
495 32 unneback 
parameter index = 0;
496 
parameter number_of_clk = 1;
497 
parameter period_time_0 = 20000;
498 
parameter period_time_1 = 20000;
499 
parameter period_time_2 = 20000;
500 
parameter period_time_3 = 20000;
501 
parameter period_time_4 = 20000;
502 
parameter lock_delay = 2000000;
503 
input clk_i, rst_n_i;
504 
output lock;
505 
output reg [0:number_of_clk-1] clk_o;
506 
output [0:number_of_clk-1] rst_o;
507 
 
508 
`ifdef SIM_PLL
509 
 
510 
always
511 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
512 
 
513 
generate if (number_of_clk > 1)
514 
always
515 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
516 
endgenerate
517 
 
518 
generate if (number_of_clk > 2)
519 
always
520 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
521 
endgenerate
522 
 
523 33 unneback 
generate if (number_of_clk > 3)
524 32 unneback 
always
525 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
526 
endgenerate
527 
 
528 33 unneback 
generate if (number_of_clk > 4)
529 32 unneback 
always
530 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
531 
endgenerate
532 
 
533 
genvar i;
534 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
535 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
536 
end
537 
endgenerate
538 
 
539 33 unneback 
//assign #lock_delay lock = rst_n_i;
540 
assign lock = rst_n_i;
541 32 unneback 
 
542 
endmodule
543 6 unneback 
`else
544 
 
545 33 unneback 
`ifdef VL_PLL0
546 
`ifdef VL_PLL0_CLK1
547 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
548 
`endif
549 
`ifdef VL_PLL0_CLK2
550 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
551 
`endif
552 
`ifdef VL_PLL0_CLK3
553 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
554 
`endif
555 
`ifdef VL_PLL0_CLK4
556 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
557 
`endif
558 
`ifdef VL_PLL0_CLK5
559 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
560 
`endif
561 
`endif
562 32 unneback 
 
563 33 unneback 
`ifdef VL_PLL1
564 
`ifdef VL_PLL1_CLK1
565 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
566 
`endif
567 
`ifdef VL_PLL1_CLK2
568 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
569 
`endif
570 
`ifdef VL_PLL1_CLK3
571 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
572 
`endif
573 
`ifdef VL_PLL1_CLK4
574 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
575 
`endif
576 
`ifdef VL_PLL1_CLK5
577 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
578 
`endif
579 
`endif
580 32 unneback 
 
581 33 unneback 
`ifdef VL_PLL2
582 
`ifdef VL_PLL2_CLK1
583 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
584 
`endif
585 
`ifdef VL_PLL2_CLK2
586 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
587 
`endif
588 
`ifdef VL_PLL2_CLK3
589 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
590 
`endif
591 
`ifdef VL_PLL2_CLK4
592 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
593 
`endif
594 
`ifdef VL_PLL2_CLK5
595 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
596 
`endif
597 
`endif
598 32 unneback 
 
599 33 unneback 
`ifdef VL_PLL3
600 
`ifdef VL_PLL3_CLK1
601 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
602 
`endif
603 
`ifdef VL_PLL3_CLK2
604 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
605 
`endif
606 
`ifdef VL_PLL3_CLK3
607 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
608 
`endif
609 
`ifdef VL_PLL3_CLK4
610 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
611 
`endif
612 
`ifdef VL_PLL3_CLK5
613 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
614 
`endif
615 
`endif
616 32 unneback 
 
617 
genvar i;
618 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
619 40 unneback 
`define MODULE sync_rst
620 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
621 
`undef MODULE
622 32 unneback 
end
623 
endgenerate
624 
endmodule
625 
`endif
626 
///////////////////////////////////////////////////////////////////////////////
627 
 
628 
`else
629 
 
630 6 unneback 
// generic PLL
631 17 unneback 
`timescale 1 ps/1 ps
632 40 unneback 
`define MODULE pll
633 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
634 
`undef MODULE
635 6 unneback 
parameter index = 0;
636 
parameter number_of_clk = 1;
637 17 unneback 
parameter period_time_0 = 20000;
638 
parameter period_time_1 = 20000;
639 
parameter period_time_2 = 20000;
640 6 unneback 
parameter lock_delay = 2000;
641 
input clk_i, rst_n_i;
642 
output lock;
643 
output reg [0:number_of_clk-1] clk_o;
644 
output [0:number_of_clk-1] rst_o;
645 
 
646 
always
647 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
648 
 
649 
generate if (number_of_clk > 1)
650 
always
651 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
652 
endgenerate
653 
 
654 
generate if (number_of_clk > 2)
655 
always
656 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
657 
endgenerate
658 
 
659 
genvar i;
660 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
661 40 unneback 
`define MODULE sync_rst
662 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
663 
`undef MODULE
664 6 unneback 
end
665 
endgenerate
666 
 
667 
assign #lock_delay lock = rst_n_i;
668 
 
669 
endmodule
670 
 
671 
`endif //altera
672 17 unneback 
`endif //actel
673 40 unneback 
`undef MODULE
674 
`endif//////////////////////////////////////////////////////////////////////
675 6 unneback 
////                                                              ////
676 
////  Versatile library, registers                                ////
677 
////                                                              ////
678 
////  Description                                                 ////
679 
////  Different type of registers                                 ////
680 
////                                                              ////
681 
////                                                              ////
682 
////  To Do:                                                      ////
683 
////   - add more different registers                             ////
684 
////                                                              ////
685 
////  Author(s):                                                  ////
686 
////      - Michael Unneback, unneback@opencores.org              ////
687 
////        ORSoC AB                                              ////
688 
////                                                              ////
689 
//////////////////////////////////////////////////////////////////////
690 
////                                                              ////
691 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
692 
////                                                              ////
693 
//// This source file may be used and distributed without         ////
694 
//// restriction provided that this copyright statement is not    ////
695 
//// removed from the file and that any derivative work contains  ////
696 
//// the original copyright notice and the associated disclaimer. ////
697 
////                                                              ////
698 
//// This source file is free software; you can redistribute it   ////
699 
//// and/or modify it under the terms of the GNU Lesser General   ////
700 
//// Public License as published by the Free Software Foundation; ////
701 
//// either version 2.1 of the License, or (at your option) any   ////
702 
//// later version.                                               ////
703 
////                                                              ////
704 
//// This source is distributed in the hope that it will be       ////
705 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
706 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
707 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
708 
//// details.                                                     ////
709 
////                                                              ////
710 
//// You should have received a copy of the GNU Lesser General    ////
711 
//// Public License along with this source; if not, download it   ////
712 
//// from http://www.opencores.org/lgpl.shtml                     ////
713 
////                                                              ////
714 
//////////////////////////////////////////////////////////////////////
715 
 
716 40 unneback 
`ifdef DFF
717 
`define MODULE dff
718 
module `BASE`MODULE ( d, q, clk, rst);
719 
`undef MODULE
720 6 unneback 
        parameter width = 1;
721 
        parameter reset_value = 0;
722 
 
723 
        input [width-1:0] d;
724 
        input clk, rst;
725 
        output reg [width-1:0] q;
726 
 
727 
        always @ (posedge clk or posedge rst)
728 
        if (rst)
729 
                q <= reset_value;
730 
        else
731 
                q <= d;
732 
 
733 
endmodule
734 40 unneback 
`endif
735 6 unneback 
 
736 40 unneback 
`ifdef DFF_ARRAY
737 
`define MODULE dff_array
738 
module `BASE`MODULE ( d, q, clk, rst);
739 
`undef MODULE
740 6 unneback 
 
741 
        parameter width = 1;
742 
        parameter depth = 2;
743 
        parameter reset_value = 1'b0;
744 
 
745 
        input [width-1:0] d;
746 
        input clk, rst;
747 
        output [width-1:0] q;
748 
        reg  [0:depth-1] q_tmp [width-1:0];
749 
        integer i;
750 
        always @ (posedge clk or posedge rst)
751 
        if (rst) begin
752 
            for (i=0;i<depth;i=i+1)
753 
                q_tmp[i] <= {width{reset_value}};
754 
        end else begin
755 
            q_tmp[0] <= d;
756 
            for (i=1;i<depth;i=i+1)
757 
                q_tmp[i] <= q_tmp[i-1];
758 
        end
759 
 
760 
    assign q = q_tmp[depth-1];
761 
 
762 
endmodule
763 40 unneback 
`endif
764 6 unneback 
 
765 40 unneback 
`ifdef DFF_CE
766 
`define MODULE dff_ce
767 
module `BASE`MODULE ( d, ce, q, clk, rst);
768 
`undef MODULE
769 6 unneback 
 
770 
        parameter width = 1;
771 
        parameter reset_value = 0;
772 
 
773 
        input [width-1:0] d;
774 
        input ce, clk, rst;
775 
        output reg [width-1:0] q;
776 
 
777 
        always @ (posedge clk or posedge rst)
778 
        if (rst)
779 
                q <= reset_value;
780 
        else
781 
                if (ce)
782 
                        q <= d;
783 
 
784 
endmodule
785 40 unneback 
`endif
786 6 unneback 
 
787 40 unneback 
`ifdef DFF_CE_CLEAR
788 
`define MODULE dff_ce_clear
789 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
790 
`undef MODULE
791 8 unneback 
 
792 
        parameter width = 1;
793 
        parameter reset_value = 0;
794 
 
795 
        input [width-1:0] d;
796 10 unneback 
        input ce, clear, clk, rst;
797 8 unneback 
        output reg [width-1:0] q;
798 
 
799 
        always @ (posedge clk or posedge rst)
800 
        if (rst)
801 
            q <= reset_value;
802 
        else
803 
            if (ce)
804 
                if (clear)
805 
                    q <= {width{1'b0}};
806 
                else
807 
                    q <= d;
808 
 
809 
endmodule
810 40 unneback 
`endif
811 8 unneback 
 
812 40 unneback 
`ifdef DF_CE_SET
813 
`define MODULE dff_ce_set
814 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
815 
`undef MODULE
816 24 unneback 
 
817 
        parameter width = 1;
818 
        parameter reset_value = 0;
819 
 
820 
        input [width-1:0] d;
821 
        input ce, set, clk, rst;
822 
        output reg [width-1:0] q;
823 
 
824 
        always @ (posedge clk or posedge rst)
825 
        if (rst)
826 
            q <= reset_value;
827 
        else
828 
            if (ce)
829 
                if (set)
830 
                    q <= {width{1'b1}};
831 
                else
832 
                    q <= d;
833 
 
834 
endmodule
835 40 unneback 
`endif
836 24 unneback 
 
837 40 unneback 
`ifdef SPR
838 
`define MODULE spr
839 
module `BASE`MODULE ( sp, r, q, clk, rst);
840 
`undef MODULE
841 
 
842 64 unneback 
        //parameter width = 1;
843 
        parameter reset_value = 1'b0;
844 29 unneback 
 
845 
        input sp, r;
846 
        output reg q;
847 
        input clk, rst;
848 
 
849 
        always @ (posedge clk or posedge rst)
850 
        if (rst)
851 
            q <= reset_value;
852 
        else
853 
            if (sp)
854 
                q <= 1'b1;
855 
            else if (r)
856 
                q <= 1'b0;
857 
 
858 
endmodule
859 40 unneback 
`endif
860 29 unneback 
 
861 40 unneback 
`ifdef SRP
862 
`define MODULE srp
863 
module `BASE`MODULE ( s, rp, q, clk, rst);
864 
`undef MODULE
865 
 
866 29 unneback 
        parameter width = 1;
867 
        parameter reset_value = 0;
868 
 
869 
        input s, rp;
870 
        output reg q;
871 
        input clk, rst;
872 
 
873 
        always @ (posedge clk or posedge rst)
874 
        if (rst)
875 
            q <= reset_value;
876 
        else
877 
            if (rp)
878 
                q <= 1'b0;
879 
            else if (s)
880 
                q <= 1'b1;
881 
 
882 
endmodule
883 40 unneback 
`endif
884 29 unneback 
 
885 40 unneback 
`ifdef ALTERA
886 29 unneback 
 
887 40 unneback 
`ifdef DFF_SR
888 6 unneback 
// megafunction wizard: %LPM_FF%
889 
// GENERATION: STANDARD
890 
// VERSION: WM1.0
891 
// MODULE: lpm_ff
892 
 
893 
// ============================================================
894 
// File Name: dff_sr.v
895 
// Megafunction Name(s):
896 
//                      lpm_ff
897 
//
898 
// Simulation Library Files(s):
899 
//                      lpm
900 
// ============================================================
901 
// ************************************************************
902 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
903 
//
904 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
905 
// ************************************************************
906 
 
907 
 
908 
//Copyright (C) 1991-2010 Altera Corporation
909 
//Your use of Altera Corporation's design tools, logic functions
910 
//and other software and tools, and its AMPP partner logic
911 
//functions, and any output files from any of the foregoing
912 
//(including device programming or simulation files), and any
913 
//associated documentation or information are expressly subject
914 
//to the terms and conditions of the Altera Program License
915 
//Subscription Agreement, Altera MegaCore Function License
916 
//Agreement, or other applicable license agreement, including,
917 
//without limitation, that your use is for the sole purpose of
918 
//programming logic devices manufactured by Altera and sold by
919 
//Altera or its authorized distributors.  Please refer to the
920 
//applicable agreement for further details.
921 
 
922 
 
923 
// synopsys translate_off
924 
`timescale 1 ps / 1 ps
925 
// synopsys translate_on
926 40 unneback 
`define MODULE dff_sr
927 
module `BASE`MODULE (
928 
`undef MODULE
929 
 
930 6 unneback 
        aclr,
931 
        aset,
932 
        clock,
933 
        data,
934 
        q);
935 
 
936 
        input     aclr;
937 
        input     aset;
938 
        input     clock;
939 
        input     data;
940 
        output    q;
941 
 
942 
        wire [0:0] sub_wire0;
943 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
944 
        wire  q = sub_wire1;
945 
        wire  sub_wire2 = data;
946 
        wire  sub_wire3 = sub_wire2;
947 
 
948 
        lpm_ff  lpm_ff_component (
949 
                                .aclr (aclr),
950 
                                .clock (clock),
951 
                                .data (sub_wire3),
952 
                                .aset (aset),
953 
                                .q (sub_wire0)
954 
                                // synopsys translate_off
955 
                                ,
956 
                                .aload (),
957 
                                .enable (),
958 
                                .sclr (),
959 
                                .sload (),
960 
                                .sset ()
961 
                                // synopsys translate_on
962 
                                );
963 
        defparam
964 
                lpm_ff_component.lpm_fftype = "DFF",
965 
                lpm_ff_component.lpm_type = "LPM_FF",
966 
                lpm_ff_component.lpm_width = 1;
967 
 
968 
 
969 
endmodule
970 
 
971 
// ============================================================
972 
// CNX file retrieval info
973 
// ============================================================
974 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
975 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
976 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
977 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
978 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
979 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
980 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
981 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
982 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
983 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
984 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
985 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
986 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
987 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
988 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
989 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
990 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
991 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
992 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
993 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
994 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
995 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
996 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
997 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
998 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
999 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1000 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1001 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1002 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1003 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1004 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1005 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1006 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1007 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1008 
// Retrieval info: LIB_FILE: lpm
1009 40 unneback 
`endif
1010 6 unneback 
 
1011 
`else
1012 
 
1013 40 unneback 
`ifdef DFF_SR
1014 
`define MODULE dff_sr
1015 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1016 
`undef MODULE
1017 6 unneback 
 
1018 
    input         aclr;
1019 
    input         aset;
1020 
    input         clock;
1021 
    input         data;
1022 
    output reg    q;
1023 
 
1024 
   always @ (posedge clock or posedge aclr or posedge aset)
1025 
     if (aclr)
1026 
       q <= 1'b0;
1027 
     else if (aset)
1028 
       q <= 1'b1;
1029 
     else
1030 
       q <= data;
1031 
 
1032 
endmodule
1033 40 unneback 
`endif
1034 6 unneback 
 
1035 
`endif
1036 
 
1037 
// LATCH
1038 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1039 
`ifdef ALTERA
1040 40 unneback 
 
1041 
`ifdef LATCH
1042 
`define MODULE latch
1043 
module `BASE`MODULE ( d, le, q, clk);
1044 
`undef MODULE
1045 6 unneback 
input d, le;
1046 
output q;
1047 
input clk;
1048 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1049 
endmodule
1050 40 unneback 
`endif
1051 
 
1052 6 unneback 
`else
1053 40 unneback 
 
1054 
`ifdef LATCH
1055 
`define MODULE latch
1056 
module `BASE`MODULE ( d, le, q, clk);
1057 
`undef MODULE
1058 6 unneback 
input d, le;
1059 48 unneback 
input clk;
1060 
always @ (le or d)
1061 60 unneback 
if (le)
1062 48 unneback 
    d <= q;
1063 6 unneback 
endmodule
1064 15 unneback 
`endif
1065 
 
1066 40 unneback 
`endif
1067 
 
1068 
`ifdef SHREG
1069 
`define MODULE shreg
1070 
module `BASE`MODULE ( d, q, clk, rst);
1071 
`undef MODULE
1072 
 
1073 17 unneback 
parameter depth = 10;
1074 
input d;
1075 
output q;
1076 
input clk, rst;
1077 
 
1078 
reg [1:depth] dffs;
1079 
 
1080 
always @ (posedge clk or posedge rst)
1081 
if (rst)
1082 
    dffs <= {depth{1'b0}};
1083 
else
1084 
    dffs <= {d,dffs[1:depth-1]};
1085 
assign q = dffs[depth];
1086 
endmodule
1087 40 unneback 
`endif
1088 17 unneback 
 
1089 40 unneback 
`ifdef SHREG_CE
1090 
`define MODULE shreg_ce
1091 
module `BASE`MODULE ( d, ce, q, clk, rst);
1092 
`undef MODULE
1093 17 unneback 
parameter depth = 10;
1094 
input d, ce;
1095 
output q;
1096 
input clk, rst;
1097 
 
1098 
reg [1:depth] dffs;
1099 
 
1100 
always @ (posedge clk or posedge rst)
1101 
if (rst)
1102 
    dffs <= {depth{1'b0}};
1103 
else
1104 
    if (ce)
1105 
        dffs <= {d,dffs[1:depth-1]};
1106 
assign q = dffs[depth];
1107 
endmodule
1108 40 unneback 
`endif
1109 17 unneback 
 
1110 40 unneback 
`ifdef DELAY
1111 
`define MODULE delay
1112 
module `BASE`MODULE ( d, q, clk, rst);
1113 
`undef MODULE
1114 15 unneback 
parameter depth = 10;
1115 
input d;
1116 
output q;
1117 
input clk, rst;
1118 
 
1119 
reg [1:depth] dffs;
1120 
 
1121 
always @ (posedge clk or posedge rst)
1122 
if (rst)
1123 
    dffs <= {depth{1'b0}};
1124 
else
1125 
    dffs <= {d,dffs[1:depth-1]};
1126 
assign q = dffs[depth];
1127 17 unneback 
endmodule
1128 40 unneback 
`endif
1129 17 unneback 
 
1130 40 unneback 
`ifdef DELAY_EMPTYFLAG
1131 
`define MODULE delay_emptyflag
1132 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1133 40 unneback 
`undef MODULE
1134 17 unneback 
parameter depth = 10;
1135 
input d;
1136 
output q, emptyflag;
1137 
input clk, rst;
1138 
 
1139 
reg [1:depth] dffs;
1140 
 
1141 
always @ (posedge clk or posedge rst)
1142 
if (rst)
1143 
    dffs <= {depth{1'b0}};
1144 
else
1145 
    dffs <= {d,dffs[1:depth-1]};
1146 
assign q = dffs[depth];
1147 
assign emptyflag = !(|dffs);
1148 
endmodule
1149 40 unneback 
`endif
1150 75 unneback 
 
1151 
`ifdef ASYNC_REG_REQ_ACK
1152 
`define MODULE async_reg_req_ack
1153 
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
1154 
`undef MODULE
1155 
parameter data_width = 8;
1156 
input [data_width-1:0] d;
1157 
output [data_width-1:0] q;
1158 
input req_i;
1159 
output req_o;
1160 
input ack_i;
1161 
output ack_o;
1162 
input clk_a, rst_a, clk_b, rst_b;
1163 
 
1164 
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
1165 
wire rst;
1166 
 
1167 
always @ (posedge clk_a or rst_a)
1168 
if (rst_a)
1169 
    q <= {data_width{1'b0}};
1170 
else
1171 
    if (req_i)
1172 
        q <= d;
1173 
 
1174 
assign rst = ack_i | rst_a;
1175 
always @ (posedge clk_a or posedge rst)
1176 
if (rst)
1177 
    req[2] <= 1'b0;
1178 
else
1179 
    req[2] <= req_i & !ack_o;
1180 
 
1181 
always @ (posedge clk_a or posedge rst_a)
1182 
if (rst_a)
1183 
    req[3] <= 1'b0;
1184 
else
1185 
    req[3] <= req[2];
1186 
 
1187 
always @ (posedge clk_b or posedge rst_b)
1188 
if (rst_b)
1189 
    req[1:0] <= 2'b00;
1190 
else
1191 
    if (ack_i)
1192 
        req[1:0] <= 2'b00;
1193 
    else
1194 
        req[1:0] <= req[2:1];
1195 
assign req_o = req[0];
1196 
 
1197 
always @ (posedge clk_a or posedge rst_a)
1198 
if (rst_a)
1199 
    ack_o <= 1'b0;
1200 
else
1201 
    ack_o <= req[3] & req[2];
1202 
 
1203 
endmodule
1204 
`endif
1205 17 unneback 
//////////////////////////////////////////////////////////////////////
1206 6 unneback 
////                                                              ////
1207 18 unneback 
////  Logic functions                                             ////
1208 
////                                                              ////
1209 
////  Description                                                 ////
1210 
////  Logic functions such as multiplexers                        ////
1211 
////                                                              ////
1212 
////                                                              ////
1213 
////  To Do:                                                      ////
1214 
////   -                                                          ////
1215 
////                                                              ////
1216 
////  Author(s):                                                  ////
1217 
////      - Michael Unneback, unneback@opencores.org              ////
1218 
////        ORSoC AB                                              ////
1219 
////                                                              ////
1220 
//////////////////////////////////////////////////////////////////////
1221 
////                                                              ////
1222 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1223 
////                                                              ////
1224 
//// This source file may be used and distributed without         ////
1225 
//// restriction provided that this copyright statement is not    ////
1226 
//// removed from the file and that any derivative work contains  ////
1227 
//// the original copyright notice and the associated disclaimer. ////
1228 
////                                                              ////
1229 
//// This source file is free software; you can redistribute it   ////
1230 
//// and/or modify it under the terms of the GNU Lesser General   ////
1231 
//// Public License as published by the Free Software Foundation; ////
1232 
//// either version 2.1 of the License, or (at your option) any   ////
1233 
//// later version.                                               ////
1234 
////                                                              ////
1235 
//// This source is distributed in the hope that it will be       ////
1236 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1237 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1238 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1239 
//// details.                                                     ////
1240 
////                                                              ////
1241 
//// You should have received a copy of the GNU Lesser General    ////
1242 
//// Public License along with this source; if not, download it   ////
1243 
//// from http://www.opencores.org/lgpl.shtml                     ////
1244 
////                                                              ////
1245 
//////////////////////////////////////////////////////////////////////
1246 40 unneback 
`ifdef MUX_ANDOR
1247 
`define MODULE mux_andor
1248 
module `BASE`MODULE ( a, sel, dout);
1249 
`undef MODULE
1250 36 unneback 
 
1251 
parameter width = 32;
1252 
parameter nr_of_ports = 4;
1253 
 
1254 
input [nr_of_ports*width-1:0] a;
1255 
input [nr_of_ports-1:0] sel;
1256 
output reg [width-1:0] dout;
1257 
 
1258 38 unneback 
integer i,j;
1259 
 
1260 36 unneback 
always @ (a, sel)
1261 
begin
1262 
    dout = a[width-1:0] & {width{sel[0]}};
1263 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1264 
        for (j=0;j<width;j=j+1)
1265 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1266 36 unneback 
end
1267 
 
1268 
endmodule
1269 40 unneback 
`endif
1270 36 unneback 
 
1271 40 unneback 
`ifdef MUX2_ANDOR
1272 
`define MODULE mux2_andor
1273 
module `BASE`MODULE ( a1, a0, sel, dout);
1274 
`undef MODULE
1275 18 unneback 
 
1276 34 unneback 
parameter width = 32;
1277 35 unneback 
localparam nr_of_ports = 2;
1278 34 unneback 
input [width-1:0] a1, a0;
1279 
input [nr_of_ports-1:0] sel;
1280 
output [width-1:0] dout;
1281 
 
1282 40 unneback 
`define MODULE mux_andor
1283 
`BASE`MODULE
1284 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1285 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1286 40 unneback 
`undef MODULE
1287 
 
1288 34 unneback 
endmodule
1289 40 unneback 
`endif
1290 34 unneback 
 
1291 40 unneback 
`ifdef MUX3_ANDOR
1292 
`define MODULE mux3_andor
1293 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1294 
`undef MODULE
1295 34 unneback 
 
1296 
parameter width = 32;
1297 35 unneback 
localparam nr_of_ports = 3;
1298 34 unneback 
input [width-1:0] a2, a1, a0;
1299 
input [nr_of_ports-1:0] sel;
1300 
output [width-1:0] dout;
1301 
 
1302 40 unneback 
`define MODULE mux_andor
1303 
`BASE`MODULE
1304 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1305 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1306 40 unneback 
`undef MODULE
1307 34 unneback 
endmodule
1308 40 unneback 
`endif
1309 34 unneback 
 
1310 40 unneback 
`ifdef MUX4_ANDOR
1311 
`define MODULE mux4_andor
1312 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1313 
`undef MODULE
1314 18 unneback 
 
1315 
parameter width = 32;
1316 35 unneback 
localparam nr_of_ports = 4;
1317 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1318 
input [nr_of_ports-1:0] sel;
1319 22 unneback 
output [width-1:0] dout;
1320 18 unneback 
 
1321 40 unneback 
`define MODULE mux_andor
1322 
`BASE`MODULE
1323 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1324 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1325 40 unneback 
`undef MODULE
1326 18 unneback 
 
1327 
endmodule
1328 40 unneback 
`endif
1329 18 unneback 
 
1330 40 unneback 
`ifdef MUX5_ANDOR
1331 
`define MODULE mux5_andor
1332 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1333 
`undef MODULE
1334 18 unneback 
 
1335 
parameter width = 32;
1336 35 unneback 
localparam nr_of_ports = 5;
1337 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1338 
input [nr_of_ports-1:0] sel;
1339 22 unneback 
output [width-1:0] dout;
1340 18 unneback 
 
1341 40 unneback 
`define MODULE mux_andor
1342 
`BASE`MODULE
1343 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1344 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1345 40 unneback 
`undef MODULE
1346 18 unneback 
 
1347 
endmodule
1348 40 unneback 
`endif
1349 18 unneback 
 
1350 40 unneback 
`ifdef MUX6_ANDOR
1351 
`define MODULE mux6_andor
1352 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1353 
`undef MODULE
1354 18 unneback 
 
1355 
parameter width = 32;
1356 35 unneback 
localparam nr_of_ports = 6;
1357 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1358 
input [nr_of_ports-1:0] sel;
1359 22 unneback 
output [width-1:0] dout;
1360 18 unneback 
 
1361 40 unneback 
`define MODULE mux_andor
1362 
`BASE`MODULE
1363 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1364 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1365 40 unneback 
`undef MODULE
1366 18 unneback 
 
1367 
endmodule
1368 40 unneback 
`endif
1369 43 unneback 
 
1370 
`ifdef PARITY
1371 
 
1372 
`define MODULE parity_generate
1373 
module `BASE`MODULE (data, parity);
1374 
`undef MODULE
1375 
parameter word_size = 32;
1376 
parameter chunk_size = 8;
1377 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1378 
input [word_size-1:0] data;
1379 
output reg [word_size/chunk_size-1:0] parity;
1380 
integer i,j;
1381 
always @ (data)
1382 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1383 
    parity[i] = parity_type;
1384 
    for (j=0;j<chunk_size;j=j+1) begin
1385 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1386 43 unneback 
    end
1387 
end
1388 
endmodule
1389 
 
1390 
`define MODULE parity_check
1391 
module `BASE`MODULE( data, parity, parity_error);
1392 
`undef MODULE
1393 
parameter word_size = 32;
1394 
parameter chunk_size = 8;
1395 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1396 
input [word_size-1:0] data;
1397 
input [word_size/chunk_size-1:0] parity;
1398 
output parity_error;
1399 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1400 43 unneback 
integer i,j;
1401 
always @ (data or parity)
1402 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1403 
    error_flag[i] = parity[i] ^ parity_type;
1404 
    for (j=0;j<chunk_size;j=j+1) begin
1405 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1406 43 unneback 
    end
1407 
end
1408 
assign parity_error = |error_flag;
1409 
endmodule
1410 
 
1411 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1412 
////                                                              ////
1413 
////  IO functions                                                ////
1414 
////                                                              ////
1415 
////  Description                                                 ////
1416 
////  IO functions such as IOB flip-flops                         ////
1417 
////                                                              ////
1418 
////                                                              ////
1419 
////  To Do:                                                      ////
1420 
////   -                                                          ////
1421 
////                                                              ////
1422 
////  Author(s):                                                  ////
1423 
////      - Michael Unneback, unneback@opencores.org              ////
1424 
////        ORSoC AB                                              ////
1425 
////                                                              ////
1426 18 unneback 
//////////////////////////////////////////////////////////////////////
1427 
////                                                              ////
1428 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1429 
////                                                              ////
1430 
//// This source file may be used and distributed without         ////
1431 
//// restriction provided that this copyright statement is not    ////
1432 
//// removed from the file and that any derivative work contains  ////
1433 
//// the original copyright notice and the associated disclaimer. ////
1434 
////                                                              ////
1435 
//// This source file is free software; you can redistribute it   ////
1436 
//// and/or modify it under the terms of the GNU Lesser General   ////
1437 
//// Public License as published by the Free Software Foundation; ////
1438 
//// either version 2.1 of the License, or (at your option) any   ////
1439 
//// later version.                                               ////
1440 
////                                                              ////
1441 
//// This source is distributed in the hope that it will be       ////
1442 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1443 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1444 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1445 
//// details.                                                     ////
1446 
////                                                              ////
1447 
//// You should have received a copy of the GNU Lesser General    ////
1448 
//// Public License along with this source; if not, download it   ////
1449 
//// from http://www.opencores.org/lgpl.shtml                     ////
1450 
////                                                              ////
1451 
//////////////////////////////////////////////////////////////////////
1452 45 unneback 
`timescale 1ns/1ns
1453 44 unneback 
`ifdef O_DFF
1454 
`define MODULE o_dff
1455 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1456 
`undef MODULE
1457 
parameter width = 1;
1458 45 unneback 
parameter reset_value = {width{1'b0}};
1459 
input  [width-1:0]  d_i;
1460 44 unneback 
output [width-1:0] o_pad;
1461 
input clk, rst;
1462 
wire [width-1:0] d_i_int `SYN_KEEP;
1463 45 unneback 
reg  [width-1:0] o_pad_int;
1464 44 unneback 
assign d_i_int = d_i;
1465 
genvar i;
1466 45 unneback 
generate
1467 44 unneback 
for (i=0;i<width;i=i+1) begin
1468 
    always @ (posedge clk or posedge rst)
1469 
    if (rst)
1470 45 unneback 
        o_pad_int[i] <= reset_value[i];
1471 44 unneback 
    else
1472 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1473 
    assign #1 o_pad[i] = o_pad_int[i];
1474 44 unneback 
end
1475 
endgenerate
1476 
endmodule
1477 
`endif
1478 
 
1479 45 unneback 
`timescale 1ns/1ns
1480 44 unneback 
`ifdef IO_DFF_OE
1481 
`define MODULE io_dff_oe
1482 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1483 
`undef MODULE
1484 
parameter width = 1;
1485 
input  [width-1:0] d_o;
1486 
output reg [width-1:0] d_i;
1487 
input oe;
1488 
inout [width-1:0] io_pad;
1489 
input clk, rst;
1490 
wire [width-1:0] oe_d `SYN_KEEP;
1491 
reg [width-1:0] oe_q;
1492 
reg [width-1:0] d_o_q;
1493 
assign oe_d = {width{oe}};
1494 
genvar i;
1495 
generate
1496 
for (i=0;i<width;i=i+1) begin
1497 
    always @ (posedge clk or posedge rst)
1498 
    if (rst)
1499 
        oe_q[i] <= 1'b0;
1500 
    else
1501 
        oe_q[i] <= oe_d[i];
1502 
    always @ (posedge clk or posedge rst)
1503 
    if (rst)
1504 
        d_o_q[i] <= 1'b0;
1505 
    else
1506 
        d_o_q[i] <= d_o[i];
1507 
    always @ (posedge clk or posedge rst)
1508 
    if (rst)
1509 
        d_i[i] <= 1'b0;
1510 
    else
1511 
        d_i[i] <= io_pad[i];
1512 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1513 44 unneback 
end
1514 
endgenerate
1515 
endmodule
1516 
`endif
1517 
`ifdef CNT_BIN
1518 
//////////////////////////////////////////////////////////////////////
1519 
////                                                              ////
1520 6 unneback 
////  Versatile counter                                           ////
1521 
////                                                              ////
1522 
////  Description                                                 ////
1523 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1524 
////  counter                                                     ////
1525 
////                                                              ////
1526 
////  To Do:                                                      ////
1527 
////   - add LFSR with more taps                                  ////
1528 
////                                                              ////
1529 
////  Author(s):                                                  ////
1530 
////      - Michael Unneback, unneback@opencores.org              ////
1531 
////        ORSoC AB                                              ////
1532 
////                                                              ////
1533 
//////////////////////////////////////////////////////////////////////
1534 
////                                                              ////
1535 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1536 
////                                                              ////
1537 
//// This source file may be used and distributed without         ////
1538 
//// restriction provided that this copyright statement is not    ////
1539 
//// removed from the file and that any derivative work contains  ////
1540 
//// the original copyright notice and the associated disclaimer. ////
1541 
////                                                              ////
1542 
//// This source file is free software; you can redistribute it   ////
1543 
//// and/or modify it under the terms of the GNU Lesser General   ////
1544 
//// Public License as published by the Free Software Foundation; ////
1545 
//// either version 2.1 of the License, or (at your option) any   ////
1546 
//// later version.                                               ////
1547 
////                                                              ////
1548 
//// This source is distributed in the hope that it will be       ////
1549 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1550 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1551 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1552 
//// details.                                                     ////
1553 
////                                                              ////
1554 
//// You should have received a copy of the GNU Lesser General    ////
1555 
//// Public License along with this source; if not, download it   ////
1556 
//// from http://www.opencores.org/lgpl.shtml                     ////
1557 
////                                                              ////
1558 
//////////////////////////////////////////////////////////////////////
1559 
 
1560 
// binary counter
1561 22 unneback 
 
1562 40 unneback 
`define MODULE cnt_bin
1563 
module `BASE`MODULE (
1564 
`undef MODULE
1565 
 q, rst, clk);
1566 
 
1567 22 unneback 
   parameter length = 4;
1568 
   output [length:1] q;
1569 
   input rst;
1570 
   input clk;
1571 
 
1572 
   parameter clear_value = 0;
1573 
   parameter set_value = 1;
1574 
   parameter wrap_value = 0;
1575 
   parameter level1_value = 15;
1576 
 
1577 
   reg  [length:1] qi;
1578 
   wire [length:1] q_next;
1579 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1580 
 
1581 
   always @ (posedge clk or posedge rst)
1582 
     if (rst)
1583 
       qi <= {length{1'b0}};
1584 
     else
1585 
       qi <= q_next;
1586 
 
1587 
   assign q = qi;
1588 
 
1589 
endmodule
1590 40 unneback 
`endif
1591 
`ifdef CNT_BIN_CLEAR
1592 22 unneback 
//////////////////////////////////////////////////////////////////////
1593 
////                                                              ////
1594 
////  Versatile counter                                           ////
1595 
////                                                              ////
1596 
////  Description                                                 ////
1597 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1598 
////  counter                                                     ////
1599 
////                                                              ////
1600 
////  To Do:                                                      ////
1601 
////   - add LFSR with more taps                                  ////
1602 
////                                                              ////
1603 
////  Author(s):                                                  ////
1604 
////      - Michael Unneback, unneback@opencores.org              ////
1605 
////        ORSoC AB                                              ////
1606 
////                                                              ////
1607 
//////////////////////////////////////////////////////////////////////
1608 
////                                                              ////
1609 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1610 
////                                                              ////
1611 
//// This source file may be used and distributed without         ////
1612 
//// restriction provided that this copyright statement is not    ////
1613 
//// removed from the file and that any derivative work contains  ////
1614 
//// the original copyright notice and the associated disclaimer. ////
1615 
////                                                              ////
1616 
//// This source file is free software; you can redistribute it   ////
1617 
//// and/or modify it under the terms of the GNU Lesser General   ////
1618 
//// Public License as published by the Free Software Foundation; ////
1619 
//// either version 2.1 of the License, or (at your option) any   ////
1620 
//// later version.                                               ////
1621 
////                                                              ////
1622 
//// This source is distributed in the hope that it will be       ////
1623 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1624 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1625 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1626 
//// details.                                                     ////
1627 
////                                                              ////
1628 
//// You should have received a copy of the GNU Lesser General    ////
1629 
//// Public License along with this source; if not, download it   ////
1630 
//// from http://www.opencores.org/lgpl.shtml                     ////
1631 
////                                                              ////
1632 
//////////////////////////////////////////////////////////////////////
1633 
 
1634 
// binary counter
1635 
 
1636 40 unneback 
`define MODULE cnt_bin_clear
1637 
module `BASE`MODULE (
1638 
`undef MODULE
1639 
 clear, q, rst, clk);
1640 
 
1641 22 unneback 
   parameter length = 4;
1642 
   input clear;
1643 
   output [length:1] q;
1644 
   input rst;
1645 
   input clk;
1646 
 
1647 
   parameter clear_value = 0;
1648 
   parameter set_value = 1;
1649 
   parameter wrap_value = 0;
1650 
   parameter level1_value = 15;
1651 
 
1652 
   reg  [length:1] qi;
1653 
   wire [length:1] q_next;
1654 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1655 
 
1656 
   always @ (posedge clk or posedge rst)
1657 
     if (rst)
1658 
       qi <= {length{1'b0}};
1659 
     else
1660 
       qi <= q_next;
1661 
 
1662 
   assign q = qi;
1663 
 
1664 
endmodule
1665 40 unneback 
`endif
1666 
`ifdef CNT_BIN_CE
1667 22 unneback 
//////////////////////////////////////////////////////////////////////
1668 
////                                                              ////
1669 
////  Versatile counter                                           ////
1670 
////                                                              ////
1671 
////  Description                                                 ////
1672 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1673 
////  counter                                                     ////
1674 
////                                                              ////
1675 
////  To Do:                                                      ////
1676 
////   - add LFSR with more taps                                  ////
1677 
////                                                              ////
1678 
////  Author(s):                                                  ////
1679 
////      - Michael Unneback, unneback@opencores.org              ////
1680 
////        ORSoC AB                                              ////
1681 
////                                                              ////
1682 
//////////////////////////////////////////////////////////////////////
1683 
////                                                              ////
1684 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1685 
////                                                              ////
1686 
//// This source file may be used and distributed without         ////
1687 
//// restriction provided that this copyright statement is not    ////
1688 
//// removed from the file and that any derivative work contains  ////
1689 
//// the original copyright notice and the associated disclaimer. ////
1690 
////                                                              ////
1691 
//// This source file is free software; you can redistribute it   ////
1692 
//// and/or modify it under the terms of the GNU Lesser General   ////
1693 
//// Public License as published by the Free Software Foundation; ////
1694 
//// either version 2.1 of the License, or (at your option) any   ////
1695 
//// later version.                                               ////
1696 
////                                                              ////
1697 
//// This source is distributed in the hope that it will be       ////
1698 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1699 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1700 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1701 
//// details.                                                     ////
1702 
////                                                              ////
1703 
//// You should have received a copy of the GNU Lesser General    ////
1704 
//// Public License along with this source; if not, download it   ////
1705 
//// from http://www.opencores.org/lgpl.shtml                     ////
1706 
////                                                              ////
1707 
//////////////////////////////////////////////////////////////////////
1708 
 
1709 
// binary counter
1710 6 unneback 
 
1711 40 unneback 
`define MODULE cnt_bin_ce
1712 
module `BASE`MODULE (
1713 
`undef MODULE
1714 
 cke, q, rst, clk);
1715 
 
1716 6 unneback 
   parameter length = 4;
1717 
   input cke;
1718 
   output [length:1] q;
1719 
   input rst;
1720 
   input clk;
1721 
 
1722 
   parameter clear_value = 0;
1723 
   parameter set_value = 1;
1724 
   parameter wrap_value = 0;
1725 
   parameter level1_value = 15;
1726 
 
1727 
   reg  [length:1] qi;
1728 
   wire [length:1] q_next;
1729 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1730 
 
1731 
   always @ (posedge clk or posedge rst)
1732 
     if (rst)
1733 
       qi <= {length{1'b0}};
1734 
     else
1735 
     if (cke)
1736 
       qi <= q_next;
1737 
 
1738 
   assign q = qi;
1739 
 
1740 
endmodule
1741 40 unneback 
`endif
1742 
`ifdef CNT_BIN_CE_CLEAR
1743 6 unneback 
//////////////////////////////////////////////////////////////////////
1744 
////                                                              ////
1745 
////  Versatile counter                                           ////
1746 
////                                                              ////
1747 
////  Description                                                 ////
1748 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1749 
////  counter                                                     ////
1750 
////                                                              ////
1751 
////  To Do:                                                      ////
1752 
////   - add LFSR with more taps                                  ////
1753 
////                                                              ////
1754 
////  Author(s):                                                  ////
1755 
////      - Michael Unneback, unneback@opencores.org              ////
1756 
////        ORSoC AB                                              ////
1757 
////                                                              ////
1758 
//////////////////////////////////////////////////////////////////////
1759 
////                                                              ////
1760 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1761 
////                                                              ////
1762 
//// This source file may be used and distributed without         ////
1763 
//// restriction provided that this copyright statement is not    ////
1764 
//// removed from the file and that any derivative work contains  ////
1765 
//// the original copyright notice and the associated disclaimer. ////
1766 
////                                                              ////
1767 
//// This source file is free software; you can redistribute it   ////
1768 
//// and/or modify it under the terms of the GNU Lesser General   ////
1769 
//// Public License as published by the Free Software Foundation; ////
1770 
//// either version 2.1 of the License, or (at your option) any   ////
1771 
//// later version.                                               ////
1772 
////                                                              ////
1773 
//// This source is distributed in the hope that it will be       ////
1774 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1775 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1776 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1777 
//// details.                                                     ////
1778 
////                                                              ////
1779 
//// You should have received a copy of the GNU Lesser General    ////
1780 
//// Public License along with this source; if not, download it   ////
1781 
//// from http://www.opencores.org/lgpl.shtml                     ////
1782 
////                                                              ////
1783 
//////////////////////////////////////////////////////////////////////
1784 
 
1785 
// binary counter
1786 
 
1787 40 unneback 
`define MODULE cnt_bin_ce_clear
1788 
module `BASE`MODULE (
1789 
`undef MODULE
1790 
 clear, cke, q, rst, clk);
1791 
 
1792 6 unneback 
   parameter length = 4;
1793 
   input clear;
1794 
   input cke;
1795 
   output [length:1] q;
1796 
   input rst;
1797 
   input clk;
1798 
 
1799 
   parameter clear_value = 0;
1800 
   parameter set_value = 1;
1801 
   parameter wrap_value = 0;
1802 
   parameter level1_value = 15;
1803 
 
1804 
   reg  [length:1] qi;
1805 
   wire [length:1] q_next;
1806 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1807 
 
1808 
   always @ (posedge clk or posedge rst)
1809 
     if (rst)
1810 
       qi <= {length{1'b0}};
1811 
     else
1812 
     if (cke)
1813 
       qi <= q_next;
1814 
 
1815 
   assign q = qi;
1816 
 
1817 
endmodule
1818 40 unneback 
`endif
1819 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1820 6 unneback 
//////////////////////////////////////////////////////////////////////
1821 
////                                                              ////
1822 
////  Versatile counter                                           ////
1823 
////                                                              ////
1824 
////  Description                                                 ////
1825 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1826 
////  counter                                                     ////
1827 
////                                                              ////
1828 
////  To Do:                                                      ////
1829 
////   - add LFSR with more taps                                  ////
1830 
////                                                              ////
1831 
////  Author(s):                                                  ////
1832 
////      - Michael Unneback, unneback@opencores.org              ////
1833 
////        ORSoC AB                                              ////
1834 
////                                                              ////
1835 
//////////////////////////////////////////////////////////////////////
1836 
////                                                              ////
1837 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1838 
////                                                              ////
1839 
//// This source file may be used and distributed without         ////
1840 
//// restriction provided that this copyright statement is not    ////
1841 
//// removed from the file and that any derivative work contains  ////
1842 
//// the original copyright notice and the associated disclaimer. ////
1843 
////                                                              ////
1844 
//// This source file is free software; you can redistribute it   ////
1845 
//// and/or modify it under the terms of the GNU Lesser General   ////
1846 
//// Public License as published by the Free Software Foundation; ////
1847 
//// either version 2.1 of the License, or (at your option) any   ////
1848 
//// later version.                                               ////
1849 
////                                                              ////
1850 
//// This source is distributed in the hope that it will be       ////
1851 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1852 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1853 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1854 
//// details.                                                     ////
1855 
////                                                              ////
1856 
//// You should have received a copy of the GNU Lesser General    ////
1857 
//// Public License along with this source; if not, download it   ////
1858 
//// from http://www.opencores.org/lgpl.shtml                     ////
1859 
////                                                              ////
1860 
//////////////////////////////////////////////////////////////////////
1861 
 
1862 
// binary counter
1863 29 unneback 
 
1864 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1865 
module `BASE`MODULE (
1866 
`undef MODULE
1867 
 clear, cke, q, level1, level2, rst, clk);
1868 
 
1869 29 unneback 
   parameter length = 4;
1870 
   input clear;
1871 
   input cke;
1872 
   output [length:1] q;
1873 
   output reg level1;
1874 
   output reg level2;
1875 
   input rst;
1876 
   input clk;
1877 
 
1878 
   parameter clear_value = 0;
1879 
   parameter set_value = 1;
1880 30 unneback 
   parameter wrap_value = 15;
1881 
   parameter level1_value = 8;
1882 
   parameter level2_value = 15;
1883 29 unneback 
 
1884 
   wire rew;
1885 30 unneback 
   assign rew = 1'b0;
1886 29 unneback 
   reg  [length:1] qi;
1887 
   wire [length:1] q_next;
1888 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1889 
 
1890 
   always @ (posedge clk or posedge rst)
1891 
     if (rst)
1892 
       qi <= {length{1'b0}};
1893 
     else
1894 
     if (cke)
1895 
       qi <= q_next;
1896 
 
1897 
   assign q = qi;
1898 
 
1899 
 
1900 
    always @ (posedge clk or posedge rst)
1901 
    if (rst)
1902 
        level1 <= 1'b0;
1903 
    else
1904 
    if (cke)
1905 
    if (clear)
1906 
        level1 <= 1'b0;
1907 
    else if (q_next == level1_value)
1908 
        level1 <= 1'b1;
1909 
    else if (qi == level1_value & rew)
1910 
        level1 <= 1'b0;
1911 
 
1912 
    always @ (posedge clk or posedge rst)
1913 
    if (rst)
1914 
        level2 <= 1'b0;
1915 
    else
1916 
    if (cke)
1917 
    if (clear)
1918 
        level2 <= 1'b0;
1919 
    else if (q_next == level2_value)
1920 
        level2 <= 1'b1;
1921 
    else if (qi == level2_value & rew)
1922 
        level2 <= 1'b0;
1923 
endmodule
1924 40 unneback 
`endif
1925 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1926 29 unneback 
//////////////////////////////////////////////////////////////////////
1927 
////                                                              ////
1928 
////  Versatile counter                                           ////
1929 
////                                                              ////
1930 
////  Description                                                 ////
1931 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1932 
////  counter                                                     ////
1933 
////                                                              ////
1934 
////  To Do:                                                      ////
1935 
////   - add LFSR with more taps                                  ////
1936 
////                                                              ////
1937 
////  Author(s):                                                  ////
1938 
////      - Michael Unneback, unneback@opencores.org              ////
1939 
////        ORSoC AB                                              ////
1940 
////                                                              ////
1941 
//////////////////////////////////////////////////////////////////////
1942 
////                                                              ////
1943 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1944 
////                                                              ////
1945 
//// This source file may be used and distributed without         ////
1946 
//// restriction provided that this copyright statement is not    ////
1947 
//// removed from the file and that any derivative work contains  ////
1948 
//// the original copyright notice and the associated disclaimer. ////
1949 
////                                                              ////
1950 
//// This source file is free software; you can redistribute it   ////
1951 
//// and/or modify it under the terms of the GNU Lesser General   ////
1952 
//// Public License as published by the Free Software Foundation; ////
1953 
//// either version 2.1 of the License, or (at your option) any   ////
1954 
//// later version.                                               ////
1955 
////                                                              ////
1956 
//// This source is distributed in the hope that it will be       ////
1957 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1958 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1959 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1960 
//// details.                                                     ////
1961 
////                                                              ////
1962 
//// You should have received a copy of the GNU Lesser General    ////
1963 
//// Public License along with this source; if not, download it   ////
1964 
//// from http://www.opencores.org/lgpl.shtml                     ////
1965 
////                                                              ////
1966 
//////////////////////////////////////////////////////////////////////
1967 
 
1968 
// binary counter
1969 6 unneback 
 
1970 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1971 
module `BASE`MODULE (
1972 
`undef MODULE
1973 
 clear, set, cke, rew, q, rst, clk);
1974 
 
1975 6 unneback 
   parameter length = 4;
1976 
   input clear;
1977 
   input set;
1978 
   input cke;
1979 
   input rew;
1980 
   output [length:1] q;
1981 
   input rst;
1982 
   input clk;
1983 
 
1984 
   parameter clear_value = 0;
1985 
   parameter set_value = 1;
1986 
   parameter wrap_value = 0;
1987 
   parameter level1_value = 15;
1988 
 
1989 
   reg  [length:1] qi;
1990 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1991 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1992 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1993 
   assign q_next = rew ? q_next_rew : q_next_fw;
1994 
 
1995 
   always @ (posedge clk or posedge rst)
1996 
     if (rst)
1997 
       qi <= {length{1'b0}};
1998 
     else
1999 
     if (cke)
2000 
       qi <= q_next;
2001 
 
2002 
   assign q = qi;
2003 
 
2004 
endmodule
2005 40 unneback 
`endif
2006 
`ifdef CNT_BIN_CE_REW_L1
2007 6 unneback 
//////////////////////////////////////////////////////////////////////
2008 
////                                                              ////
2009 
////  Versatile counter                                           ////
2010 
////                                                              ////
2011 
////  Description                                                 ////
2012 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2013 
////  counter                                                     ////
2014 
////                                                              ////
2015 
////  To Do:                                                      ////
2016 
////   - add LFSR with more taps                                  ////
2017 
////                                                              ////
2018 
////  Author(s):                                                  ////
2019 
////      - Michael Unneback, unneback@opencores.org              ////
2020 
////        ORSoC AB                                              ////
2021 
////                                                              ////
2022 
//////////////////////////////////////////////////////////////////////
2023 
////                                                              ////
2024 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2025 
////                                                              ////
2026 
//// This source file may be used and distributed without         ////
2027 
//// restriction provided that this copyright statement is not    ////
2028 
//// removed from the file and that any derivative work contains  ////
2029 
//// the original copyright notice and the associated disclaimer. ////
2030 
////                                                              ////
2031 
//// This source file is free software; you can redistribute it   ////
2032 
//// and/or modify it under the terms of the GNU Lesser General   ////
2033 
//// Public License as published by the Free Software Foundation; ////
2034 
//// either version 2.1 of the License, or (at your option) any   ////
2035 
//// later version.                                               ////
2036 
////                                                              ////
2037 
//// This source is distributed in the hope that it will be       ////
2038 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2039 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2040 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2041 
//// details.                                                     ////
2042 
////                                                              ////
2043 
//// You should have received a copy of the GNU Lesser General    ////
2044 
//// Public License along with this source; if not, download it   ////
2045 
//// from http://www.opencores.org/lgpl.shtml                     ////
2046 
////                                                              ////
2047 
//////////////////////////////////////////////////////////////////////
2048 
 
2049 
// binary counter
2050 
 
2051 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2052 
module `BASE`MODULE (
2053 
`undef MODULE
2054 
 cke, rew, level1, rst, clk);
2055 
 
2056 6 unneback 
   parameter length = 4;
2057 
   input cke;
2058 
   input rew;
2059 
   output reg level1;
2060 
   input rst;
2061 
   input clk;
2062 
 
2063 
   parameter clear_value = 0;
2064 
   parameter set_value = 1;
2065 
   parameter wrap_value = 1;
2066 
   parameter level1_value = 15;
2067 
 
2068 29 unneback 
   wire clear;
2069 30 unneback 
   assign clear = 1'b0;
2070 6 unneback 
   reg  [length:1] qi;
2071 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2072 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2073 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2074 
   assign q_next = rew ? q_next_rew : q_next_fw;
2075 
 
2076 
   always @ (posedge clk or posedge rst)
2077 
     if (rst)
2078 
       qi <= {length{1'b0}};
2079 
     else
2080 
     if (cke)
2081 
       qi <= q_next;
2082 
 
2083 
 
2084 
 
2085 
    always @ (posedge clk or posedge rst)
2086 
    if (rst)
2087 
        level1 <= 1'b0;
2088 
    else
2089 
    if (cke)
2090 29 unneback 
    if (clear)
2091 
        level1 <= 1'b0;
2092 
    else if (q_next == level1_value)
2093 6 unneback 
        level1 <= 1'b1;
2094 
    else if (qi == level1_value & rew)
2095 
        level1 <= 1'b0;
2096 
endmodule
2097 40 unneback 
`endif
2098 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2099 6 unneback 
//////////////////////////////////////////////////////////////////////
2100 
////                                                              ////
2101 
////  Versatile counter                                           ////
2102 
////                                                              ////
2103 
////  Description                                                 ////
2104 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2105 
////  counter                                                     ////
2106 
////                                                              ////
2107 
////  To Do:                                                      ////
2108 
////   - add LFSR with more taps                                  ////
2109 
////                                                              ////
2110 
////  Author(s):                                                  ////
2111 
////      - Michael Unneback, unneback@opencores.org              ////
2112 
////        ORSoC AB                                              ////
2113 
////                                                              ////
2114 
//////////////////////////////////////////////////////////////////////
2115 
////                                                              ////
2116 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2117 
////                                                              ////
2118 
//// This source file may be used and distributed without         ////
2119 
//// restriction provided that this copyright statement is not    ////
2120 
//// removed from the file and that any derivative work contains  ////
2121 
//// the original copyright notice and the associated disclaimer. ////
2122 
////                                                              ////
2123 
//// This source file is free software; you can redistribute it   ////
2124 
//// and/or modify it under the terms of the GNU Lesser General   ////
2125 
//// Public License as published by the Free Software Foundation; ////
2126 
//// either version 2.1 of the License, or (at your option) any   ////
2127 
//// later version.                                               ////
2128 
////                                                              ////
2129 
//// This source is distributed in the hope that it will be       ////
2130 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2131 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2132 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2133 
//// details.                                                     ////
2134 
////                                                              ////
2135 
//// You should have received a copy of the GNU Lesser General    ////
2136 
//// Public License along with this source; if not, download it   ////
2137 
//// from http://www.opencores.org/lgpl.shtml                     ////
2138 
////                                                              ////
2139 
//////////////////////////////////////////////////////////////////////
2140 
 
2141 25 unneback 
// binary counter
2142 
 
2143 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2144 
module `BASE`MODULE (
2145 
`undef MODULE
2146 
 cke, rew, zq, level1, rst, clk);
2147 
 
2148 25 unneback 
   parameter length = 4;
2149 
   input cke;
2150 
   input rew;
2151 
   output reg zq;
2152 
   output reg level1;
2153 
   input rst;
2154 
   input clk;
2155 
 
2156 
   parameter clear_value = 0;
2157 
   parameter set_value = 1;
2158 
   parameter wrap_value = 1;
2159 
   parameter level1_value = 15;
2160 
 
2161 29 unneback 
   wire clear;
2162 30 unneback 
   assign clear = 1'b0;
2163 25 unneback 
   reg  [length:1] qi;
2164 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2165 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2166 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2167 
   assign q_next = rew ? q_next_rew : q_next_fw;
2168 
 
2169 
   always @ (posedge clk or posedge rst)
2170 
     if (rst)
2171 
       qi <= {length{1'b0}};
2172 
     else
2173 
     if (cke)
2174 
       qi <= q_next;
2175 
 
2176 
 
2177 
 
2178 
   always @ (posedge clk or posedge rst)
2179 
     if (rst)
2180 
       zq <= 1'b1;
2181 
     else
2182 
     if (cke)
2183 
       zq <= q_next == {length{1'b0}};
2184 
 
2185 
    always @ (posedge clk or posedge rst)
2186 
    if (rst)
2187 
        level1 <= 1'b0;
2188 
    else
2189 
    if (cke)
2190 29 unneback 
    if (clear)
2191 
        level1 <= 1'b0;
2192 
    else if (q_next == level1_value)
2193 25 unneback 
        level1 <= 1'b1;
2194 
    else if (qi == level1_value & rew)
2195 
        level1 <= 1'b0;
2196 
endmodule
2197 40 unneback 
`endif
2198 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2199 25 unneback 
//////////////////////////////////////////////////////////////////////
2200 
////                                                              ////
2201 
////  Versatile counter                                           ////
2202 
////                                                              ////
2203 
////  Description                                                 ////
2204 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2205 
////  counter                                                     ////
2206 
////                                                              ////
2207 
////  To Do:                                                      ////
2208 
////   - add LFSR with more taps                                  ////
2209 
////                                                              ////
2210 
////  Author(s):                                                  ////
2211 
////      - Michael Unneback, unneback@opencores.org              ////
2212 
////        ORSoC AB                                              ////
2213 
////                                                              ////
2214 
//////////////////////////////////////////////////////////////////////
2215 
////                                                              ////
2216 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2217 
////                                                              ////
2218 
//// This source file may be used and distributed without         ////
2219 
//// restriction provided that this copyright statement is not    ////
2220 
//// removed from the file and that any derivative work contains  ////
2221 
//// the original copyright notice and the associated disclaimer. ////
2222 
////                                                              ////
2223 
//// This source file is free software; you can redistribute it   ////
2224 
//// and/or modify it under the terms of the GNU Lesser General   ////
2225 
//// Public License as published by the Free Software Foundation; ////
2226 
//// either version 2.1 of the License, or (at your option) any   ////
2227 
//// later version.                                               ////
2228 
////                                                              ////
2229 
//// This source is distributed in the hope that it will be       ////
2230 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2231 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2232 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2233 
//// details.                                                     ////
2234 
////                                                              ////
2235 
//// You should have received a copy of the GNU Lesser General    ////
2236 
//// Public License along with this source; if not, download it   ////
2237 
//// from http://www.opencores.org/lgpl.shtml                     ////
2238 
////                                                              ////
2239 
//////////////////////////////////////////////////////////////////////
2240 
 
2241 
// binary counter
2242 
 
2243 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2244 
module `BASE`MODULE (
2245 
`undef MODULE
2246 
 cke, rew, q, zq, level1, rst, clk);
2247 
 
2248 25 unneback 
   parameter length = 4;
2249 
   input cke;
2250 
   input rew;
2251 
   output [length:1] q;
2252 
   output reg zq;
2253 
   output reg level1;
2254 
   input rst;
2255 
   input clk;
2256 
 
2257 
   parameter clear_value = 0;
2258 
   parameter set_value = 1;
2259 
   parameter wrap_value = 1;
2260 
   parameter level1_value = 15;
2261 
 
2262 29 unneback 
   wire clear;
2263 30 unneback 
   assign clear = 1'b0;
2264 25 unneback 
   reg  [length:1] qi;
2265 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2266 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2267 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2268 
   assign q_next = rew ? q_next_rew : q_next_fw;
2269 
 
2270 
   always @ (posedge clk or posedge rst)
2271 
     if (rst)
2272 
       qi <= {length{1'b0}};
2273 
     else
2274 
     if (cke)
2275 
       qi <= q_next;
2276 
 
2277 
   assign q = qi;
2278 
 
2279 
 
2280 
   always @ (posedge clk or posedge rst)
2281 
     if (rst)
2282 
       zq <= 1'b1;
2283 
     else
2284 
     if (cke)
2285 
       zq <= q_next == {length{1'b0}};
2286 
 
2287 
    always @ (posedge clk or posedge rst)
2288 
    if (rst)
2289 
        level1 <= 1'b0;
2290 
    else
2291 
    if (cke)
2292 29 unneback 
    if (clear)
2293 
        level1 <= 1'b0;
2294 
    else if (q_next == level1_value)
2295 25 unneback 
        level1 <= 1'b1;
2296 
    else if (qi == level1_value & rew)
2297 
        level1 <= 1'b0;
2298 
endmodule
2299 40 unneback 
`endif
2300 
`ifdef CNT_LFSR_ZQ
2301 25 unneback 
//////////////////////////////////////////////////////////////////////
2302 
////                                                              ////
2303 
////  Versatile counter                                           ////
2304 
////                                                              ////
2305 
////  Description                                                 ////
2306 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2307 
////  counter                                                     ////
2308 
////                                                              ////
2309 
////  To Do:                                                      ////
2310 
////   - add LFSR with more taps                                  ////
2311 
////                                                              ////
2312 
////  Author(s):                                                  ////
2313 
////      - Michael Unneback, unneback@opencores.org              ////
2314 
////        ORSoC AB                                              ////
2315 
////                                                              ////
2316 
//////////////////////////////////////////////////////////////////////
2317 
////                                                              ////
2318 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2319 
////                                                              ////
2320 
//// This source file may be used and distributed without         ////
2321 
//// restriction provided that this copyright statement is not    ////
2322 
//// removed from the file and that any derivative work contains  ////
2323 
//// the original copyright notice and the associated disclaimer. ////
2324 
////                                                              ////
2325 
//// This source file is free software; you can redistribute it   ////
2326 
//// and/or modify it under the terms of the GNU Lesser General   ////
2327 
//// Public License as published by the Free Software Foundation; ////
2328 
//// either version 2.1 of the License, or (at your option) any   ////
2329 
//// later version.                                               ////
2330 
////                                                              ////
2331 
//// This source is distributed in the hope that it will be       ////
2332 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2333 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2334 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2335 
//// details.                                                     ////
2336 
////                                                              ////
2337 
//// You should have received a copy of the GNU Lesser General    ////
2338 
//// Public License along with this source; if not, download it   ////
2339 
//// from http://www.opencores.org/lgpl.shtml                     ////
2340 
////                                                              ////
2341 
//////////////////////////////////////////////////////////////////////
2342 
 
2343 6 unneback 
// LFSR counter
2344 
 
2345 40 unneback 
`define MODULE cnt_lfsr_zq
2346 
module `BASE`MODULE (
2347 
`undef MODULE
2348 
 zq, rst, clk);
2349 
 
2350 6 unneback 
   parameter length = 4;
2351 
   output reg zq;
2352 
   input rst;
2353 
   input clk;
2354 
 
2355 
   parameter clear_value = 0;
2356 
   parameter set_value = 1;
2357 
   parameter wrap_value = 8;
2358 
   parameter level1_value = 15;
2359 
 
2360 
   reg  [length:1] qi;
2361 
   reg lfsr_fb;
2362 
   wire [length:1] q_next;
2363 
   reg [32:1] polynom;
2364 
   integer i;
2365 
 
2366 
   always @ (qi)
2367 
   begin
2368 
        case (length)
2369 
         2: polynom = 32'b11;                               // 0x3
2370 
         3: polynom = 32'b110;                              // 0x6
2371 
         4: polynom = 32'b1100;                             // 0xC
2372 
         5: polynom = 32'b10100;                            // 0x14
2373 
         6: polynom = 32'b110000;                           // 0x30
2374 
         7: polynom = 32'b1100000;                          // 0x60
2375 
         8: polynom = 32'b10111000;                         // 0xb8
2376 
         9: polynom = 32'b100010000;                        // 0x110
2377 
        10: polynom = 32'b1001000000;                       // 0x240
2378 
        11: polynom = 32'b10100000000;                      // 0x500
2379 
        12: polynom = 32'b100000101001;                     // 0x829
2380 
        13: polynom = 32'b1000000001100;                    // 0x100C
2381 
        14: polynom = 32'b10000000010101;                   // 0x2015
2382 
        15: polynom = 32'b110000000000000;                  // 0x6000
2383 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2384 
        17: polynom = 32'b10010000000000000;                // 0x12000
2385 
        18: polynom = 32'b100000010000000000;               // 0x20400
2386 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2387 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2388 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2389 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2390 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2391 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2392 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2393 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2394 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2395 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2396 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2397 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2398 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2399 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2400 
        default: polynom = 32'b0;
2401 
        endcase
2402 
        lfsr_fb = qi[length];
2403 
        for (i=length-1; i>=1; i=i-1) begin
2404 
            if (polynom[i])
2405 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2406 
        end
2407 
    end
2408 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2409 
 
2410 
   always @ (posedge clk or posedge rst)
2411 
     if (rst)
2412 
       qi <= {length{1'b0}};
2413 
     else
2414 
       qi <= q_next;
2415 
 
2416 
 
2417 
 
2418 
   always @ (posedge clk or posedge rst)
2419 
     if (rst)
2420 
       zq <= 1'b1;
2421 
     else
2422 
       zq <= q_next == {length{1'b0}};
2423 
endmodule
2424 40 unneback 
`endif
2425 75 unneback 
`ifdef CNT_LFSR_CE
2426 
//////////////////////////////////////////////////////////////////////
2427 
////                                                              ////
2428 
////  Versatile counter                                           ////
2429 
////                                                              ////
2430 
////  Description                                                 ////
2431 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2432 
////  counter                                                     ////
2433 
////                                                              ////
2434 
////  To Do:                                                      ////
2435 
////   - add LFSR with more taps                                  ////
2436 
////                                                              ////
2437 
////  Author(s):                                                  ////
2438 
////      - Michael Unneback, unneback@opencores.org              ////
2439 
////        ORSoC AB                                              ////
2440 
////                                                              ////
2441 
//////////////////////////////////////////////////////////////////////
2442 
////                                                              ////
2443 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2444 
////                                                              ////
2445 
//// This source file may be used and distributed without         ////
2446 
//// restriction provided that this copyright statement is not    ////
2447 
//// removed from the file and that any derivative work contains  ////
2448 
//// the original copyright notice and the associated disclaimer. ////
2449 
////                                                              ////
2450 
//// This source file is free software; you can redistribute it   ////
2451 
//// and/or modify it under the terms of the GNU Lesser General   ////
2452 
//// Public License as published by the Free Software Foundation; ////
2453 
//// either version 2.1 of the License, or (at your option) any   ////
2454 
//// later version.                                               ////
2455 
////                                                              ////
2456 
//// This source is distributed in the hope that it will be       ////
2457 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2458 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2459 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2460 
//// details.                                                     ////
2461 
////                                                              ////
2462 
//// You should have received a copy of the GNU Lesser General    ////
2463 
//// Public License along with this source; if not, download it   ////
2464 
//// from http://www.opencores.org/lgpl.shtml                     ////
2465 
////                                                              ////
2466 
//////////////////////////////////////////////////////////////////////
2467 
 
2468 
// LFSR counter
2469 
 
2470 
`define MODULE cnt_lfsr_ce
2471 
module `BASE`MODULE (
2472 
`undef MODULE
2473 
 cke, zq, rst, clk);
2474 
 
2475 
   parameter length = 4;
2476 
   input cke;
2477 
   output reg zq;
2478 
   input rst;
2479 
   input clk;
2480 
 
2481 
   parameter clear_value = 0;
2482 
   parameter set_value = 1;
2483 
   parameter wrap_value = 0;
2484 
   parameter level1_value = 15;
2485 
 
2486 
   reg  [length:1] qi;
2487 
   reg lfsr_fb;
2488 
   wire [length:1] q_next;
2489 
   reg [32:1] polynom;
2490 
   integer i;
2491 
 
2492 
   always @ (qi)
2493 
   begin
2494 
        case (length)
2495 
         2: polynom = 32'b11;                               // 0x3
2496 
         3: polynom = 32'b110;                              // 0x6
2497 
         4: polynom = 32'b1100;                             // 0xC
2498 
         5: polynom = 32'b10100;                            // 0x14
2499 
         6: polynom = 32'b110000;                           // 0x30
2500 
         7: polynom = 32'b1100000;                          // 0x60
2501 
         8: polynom = 32'b10111000;                         // 0xb8
2502 
         9: polynom = 32'b100010000;                        // 0x110
2503 
        10: polynom = 32'b1001000000;                       // 0x240
2504 
        11: polynom = 32'b10100000000;                      // 0x500
2505 
        12: polynom = 32'b100000101001;                     // 0x829
2506 
        13: polynom = 32'b1000000001100;                    // 0x100C
2507 
        14: polynom = 32'b10000000010101;                   // 0x2015
2508 
        15: polynom = 32'b110000000000000;                  // 0x6000
2509 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2510 
        17: polynom = 32'b10010000000000000;                // 0x12000
2511 
        18: polynom = 32'b100000010000000000;               // 0x20400
2512 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2513 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2514 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2515 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2516 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2517 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2518 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2519 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2520 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2521 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2522 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2523 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2524 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2525 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2526 
        default: polynom = 32'b0;
2527 
        endcase
2528 
        lfsr_fb = qi[length];
2529 
        for (i=length-1; i>=1; i=i-1) begin
2530 
            if (polynom[i])
2531 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2532 
        end
2533 
    end
2534 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2535 
 
2536 
   always @ (posedge clk or posedge rst)
2537 
     if (rst)
2538 
       qi <= {length{1'b0}};
2539 
     else
2540 
     if (cke)
2541 
       qi <= q_next;
2542 
 
2543 
 
2544 
 
2545 
   always @ (posedge clk or posedge rst)
2546 
     if (rst)
2547 
       zq <= 1'b1;
2548 
     else
2549 
     if (cke)
2550 
       zq <= q_next == {length{1'b0}};
2551 
endmodule
2552 
`endif
2553 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2554 6 unneback 
//////////////////////////////////////////////////////////////////////
2555 
////                                                              ////
2556 
////  Versatile counter                                           ////
2557 
////                                                              ////
2558 
////  Description                                                 ////
2559 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2560 
////  counter                                                     ////
2561 
////                                                              ////
2562 
////  To Do:                                                      ////
2563 
////   - add LFSR with more taps                                  ////
2564 
////                                                              ////
2565 
////  Author(s):                                                  ////
2566 
////      - Michael Unneback, unneback@opencores.org              ////
2567 
////        ORSoC AB                                              ////
2568 
////                                                              ////
2569 
//////////////////////////////////////////////////////////////////////
2570 
////                                                              ////
2571 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2572 
////                                                              ////
2573 
//// This source file may be used and distributed without         ////
2574 
//// restriction provided that this copyright statement is not    ////
2575 
//// removed from the file and that any derivative work contains  ////
2576 
//// the original copyright notice and the associated disclaimer. ////
2577 
////                                                              ////
2578 
//// This source file is free software; you can redistribute it   ////
2579 
//// and/or modify it under the terms of the GNU Lesser General   ////
2580 
//// Public License as published by the Free Software Foundation; ////
2581 
//// either version 2.1 of the License, or (at your option) any   ////
2582 
//// later version.                                               ////
2583 
////                                                              ////
2584 
//// This source is distributed in the hope that it will be       ////
2585 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2586 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2587 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2588 
//// details.                                                     ////
2589 
////                                                              ////
2590 
//// You should have received a copy of the GNU Lesser General    ////
2591 
//// Public License along with this source; if not, download it   ////
2592 
//// from http://www.opencores.org/lgpl.shtml                     ////
2593 
////                                                              ////
2594 
//////////////////////////////////////////////////////////////////////
2595 
 
2596 
// LFSR counter
2597 
 
2598 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2599 
module `BASE`MODULE (
2600 
`undef MODULE
2601 
 cke, zq, rst, clk);
2602 
 
2603 6 unneback 
   parameter length = 4;
2604 
   input cke;
2605 
   output reg zq;
2606 
   input rst;
2607 
   input clk;
2608 
 
2609 
   parameter clear_value = 0;
2610 
   parameter set_value = 1;
2611 
   parameter wrap_value = 8;
2612 
   parameter level1_value = 15;
2613 
 
2614 
   reg  [length:1] qi;
2615 
   reg lfsr_fb;
2616 
   wire [length:1] q_next;
2617 
   reg [32:1] polynom;
2618 
   integer i;
2619 
 
2620 
   always @ (qi)
2621 
   begin
2622 
        case (length)
2623 
         2: polynom = 32'b11;                               // 0x3
2624 
         3: polynom = 32'b110;                              // 0x6
2625 
         4: polynom = 32'b1100;                             // 0xC
2626 
         5: polynom = 32'b10100;                            // 0x14
2627 
         6: polynom = 32'b110000;                           // 0x30
2628 
         7: polynom = 32'b1100000;                          // 0x60
2629 
         8: polynom = 32'b10111000;                         // 0xb8
2630 
         9: polynom = 32'b100010000;                        // 0x110
2631 
        10: polynom = 32'b1001000000;                       // 0x240
2632 
        11: polynom = 32'b10100000000;                      // 0x500
2633 
        12: polynom = 32'b100000101001;                     // 0x829
2634 
        13: polynom = 32'b1000000001100;                    // 0x100C
2635 
        14: polynom = 32'b10000000010101;                   // 0x2015
2636 
        15: polynom = 32'b110000000000000;                  // 0x6000
2637 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2638 
        17: polynom = 32'b10010000000000000;                // 0x12000
2639 
        18: polynom = 32'b100000010000000000;               // 0x20400
2640 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2641 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2642 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2643 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2644 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2645 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2646 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2647 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2648 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2649 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2650 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2651 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2652 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2653 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2654 
        default: polynom = 32'b0;
2655 
        endcase
2656 
        lfsr_fb = qi[length];
2657 
        for (i=length-1; i>=1; i=i-1) begin
2658 
            if (polynom[i])
2659 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2660 
        end
2661 
    end
2662 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2663 
 
2664 
   always @ (posedge clk or posedge rst)
2665 
     if (rst)
2666 
       qi <= {length{1'b0}};
2667 
     else
2668 
     if (cke)
2669 
       qi <= q_next;
2670 
 
2671 
 
2672 
 
2673 
   always @ (posedge clk or posedge rst)
2674 
     if (rst)
2675 
       zq <= 1'b1;
2676 
     else
2677 
     if (cke)
2678 
       zq <= q_next == {length{1'b0}};
2679 
endmodule
2680 40 unneback 
`endif
2681 
`ifdef CNT_LFSR_CE_Q
2682 6 unneback 
//////////////////////////////////////////////////////////////////////
2683 
////                                                              ////
2684 
////  Versatile counter                                           ////
2685 
////                                                              ////
2686 
////  Description                                                 ////
2687 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2688 
////  counter                                                     ////
2689 
////                                                              ////
2690 
////  To Do:                                                      ////
2691 
////   - add LFSR with more taps                                  ////
2692 
////                                                              ////
2693 
////  Author(s):                                                  ////
2694 
////      - Michael Unneback, unneback@opencores.org              ////
2695 
////        ORSoC AB                                              ////
2696 
////                                                              ////
2697 
//////////////////////////////////////////////////////////////////////
2698 
////                                                              ////
2699 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2700 
////                                                              ////
2701 
//// This source file may be used and distributed without         ////
2702 
//// restriction provided that this copyright statement is not    ////
2703 
//// removed from the file and that any derivative work contains  ////
2704 
//// the original copyright notice and the associated disclaimer. ////
2705 
////                                                              ////
2706 
//// This source file is free software; you can redistribute it   ////
2707 
//// and/or modify it under the terms of the GNU Lesser General   ////
2708 
//// Public License as published by the Free Software Foundation; ////
2709 
//// either version 2.1 of the License, or (at your option) any   ////
2710 
//// later version.                                               ////
2711 
////                                                              ////
2712 
//// This source is distributed in the hope that it will be       ////
2713 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2714 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2715 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2716 
//// details.                                                     ////
2717 
////                                                              ////
2718 
//// You should have received a copy of the GNU Lesser General    ////
2719 
//// Public License along with this source; if not, download it   ////
2720 
//// from http://www.opencores.org/lgpl.shtml                     ////
2721 
////                                                              ////
2722 
//////////////////////////////////////////////////////////////////////
2723 22 unneback 
 
2724 
// LFSR counter
2725 27 unneback 
 
2726 40 unneback 
`define MODULE cnt_lfsr_ce_q
2727 
module `BASE`MODULE (
2728 
`undef MODULE
2729 
 cke, q, rst, clk);
2730 
 
2731 27 unneback 
   parameter length = 4;
2732 
   input cke;
2733 
   output [length:1] q;
2734 
   input rst;
2735 
   input clk;
2736 
 
2737 
   parameter clear_value = 0;
2738 
   parameter set_value = 1;
2739 
   parameter wrap_value = 8;
2740 
   parameter level1_value = 15;
2741 
 
2742 
   reg  [length:1] qi;
2743 
   reg lfsr_fb;
2744 
   wire [length:1] q_next;
2745 
   reg [32:1] polynom;
2746 
   integer i;
2747 
 
2748 
   always @ (qi)
2749 
   begin
2750 
        case (length)
2751 
         2: polynom = 32'b11;                               // 0x3
2752 
         3: polynom = 32'b110;                              // 0x6
2753 
         4: polynom = 32'b1100;                             // 0xC
2754 
         5: polynom = 32'b10100;                            // 0x14
2755 
         6: polynom = 32'b110000;                           // 0x30
2756 
         7: polynom = 32'b1100000;                          // 0x60
2757 
         8: polynom = 32'b10111000;                         // 0xb8
2758 
         9: polynom = 32'b100010000;                        // 0x110
2759 
        10: polynom = 32'b1001000000;                       // 0x240
2760 
        11: polynom = 32'b10100000000;                      // 0x500
2761 
        12: polynom = 32'b100000101001;                     // 0x829
2762 
        13: polynom = 32'b1000000001100;                    // 0x100C
2763 
        14: polynom = 32'b10000000010101;                   // 0x2015
2764 
        15: polynom = 32'b110000000000000;                  // 0x6000
2765 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2766 
        17: polynom = 32'b10010000000000000;                // 0x12000
2767 
        18: polynom = 32'b100000010000000000;               // 0x20400
2768 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2769 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2770 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2771 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2772 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2773 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2774 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2775 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2776 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2777 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2778 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2779 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2780 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2781 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2782 
        default: polynom = 32'b0;
2783 
        endcase
2784 
        lfsr_fb = qi[length];
2785 
        for (i=length-1; i>=1; i=i-1) begin
2786 
            if (polynom[i])
2787 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2788 
        end
2789 
    end
2790 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2791 
 
2792 
   always @ (posedge clk or posedge rst)
2793 
     if (rst)
2794 
       qi <= {length{1'b0}};
2795 
     else
2796 
     if (cke)
2797 
       qi <= q_next;
2798 
 
2799 
   assign q = qi;
2800 
 
2801 
endmodule
2802 40 unneback 
`endif
2803 
`ifdef CNT_LFSR_CE_CLEAR_Q
2804 27 unneback 
//////////////////////////////////////////////////////////////////////
2805 
////                                                              ////
2806 
////  Versatile counter                                           ////
2807 
////                                                              ////
2808 
////  Description                                                 ////
2809 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2810 
////  counter                                                     ////
2811 
////                                                              ////
2812 
////  To Do:                                                      ////
2813 
////   - add LFSR with more taps                                  ////
2814 
////                                                              ////
2815 
////  Author(s):                                                  ////
2816 
////      - Michael Unneback, unneback@opencores.org              ////
2817 
////        ORSoC AB                                              ////
2818 
////                                                              ////
2819 
//////////////////////////////////////////////////////////////////////
2820 
////                                                              ////
2821 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2822 
////                                                              ////
2823 
//// This source file may be used and distributed without         ////
2824 
//// restriction provided that this copyright statement is not    ////
2825 
//// removed from the file and that any derivative work contains  ////
2826 
//// the original copyright notice and the associated disclaimer. ////
2827 
////                                                              ////
2828 
//// This source file is free software; you can redistribute it   ////
2829 
//// and/or modify it under the terms of the GNU Lesser General   ////
2830 
//// Public License as published by the Free Software Foundation; ////
2831 
//// either version 2.1 of the License, or (at your option) any   ////
2832 
//// later version.                                               ////
2833 
////                                                              ////
2834 
//// This source is distributed in the hope that it will be       ////
2835 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2836 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2837 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2838 
//// details.                                                     ////
2839 
////                                                              ////
2840 
//// You should have received a copy of the GNU Lesser General    ////
2841 
//// Public License along with this source; if not, download it   ////
2842 
//// from http://www.opencores.org/lgpl.shtml                     ////
2843 
////                                                              ////
2844 
//////////////////////////////////////////////////////////////////////
2845 
 
2846 
// LFSR counter
2847 
 
2848 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2849 
module `BASE`MODULE (
2850 
`undef MODULE
2851 
 clear, cke, q, rst, clk);
2852 
 
2853 27 unneback 
   parameter length = 4;
2854 
   input clear;
2855 
   input cke;
2856 
   output [length:1] q;
2857 
   input rst;
2858 
   input clk;
2859 
 
2860 
   parameter clear_value = 0;
2861 
   parameter set_value = 1;
2862 
   parameter wrap_value = 8;
2863 
   parameter level1_value = 15;
2864 
 
2865 
   reg  [length:1] qi;
2866 
   reg lfsr_fb;
2867 
   wire [length:1] q_next;
2868 
   reg [32:1] polynom;
2869 
   integer i;
2870 
 
2871 
   always @ (qi)
2872 
   begin
2873 
        case (length)
2874 
         2: polynom = 32'b11;                               // 0x3
2875 
         3: polynom = 32'b110;                              // 0x6
2876 
         4: polynom = 32'b1100;                             // 0xC
2877 
         5: polynom = 32'b10100;                            // 0x14
2878 
         6: polynom = 32'b110000;                           // 0x30
2879 
         7: polynom = 32'b1100000;                          // 0x60
2880 
         8: polynom = 32'b10111000;                         // 0xb8
2881 
         9: polynom = 32'b100010000;                        // 0x110
2882 
        10: polynom = 32'b1001000000;                       // 0x240
2883 
        11: polynom = 32'b10100000000;                      // 0x500
2884 
        12: polynom = 32'b100000101001;                     // 0x829
2885 
        13: polynom = 32'b1000000001100;                    // 0x100C
2886 
        14: polynom = 32'b10000000010101;                   // 0x2015
2887 
        15: polynom = 32'b110000000000000;                  // 0x6000
2888 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2889 
        17: polynom = 32'b10010000000000000;                // 0x12000
2890 
        18: polynom = 32'b100000010000000000;               // 0x20400
2891 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2892 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2893 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2894 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2895 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2896 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2897 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2898 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2899 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2900 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2901 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2902 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2903 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2904 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2905 
        default: polynom = 32'b0;
2906 
        endcase
2907 
        lfsr_fb = qi[length];
2908 
        for (i=length-1; i>=1; i=i-1) begin
2909 
            if (polynom[i])
2910 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2911 
        end
2912 
    end
2913 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2914 
 
2915 
   always @ (posedge clk or posedge rst)
2916 
     if (rst)
2917 
       qi <= {length{1'b0}};
2918 
     else
2919 
     if (cke)
2920 
       qi <= q_next;
2921 
 
2922 
   assign q = qi;
2923 
 
2924 
endmodule
2925 40 unneback 
`endif
2926 
`ifdef CNT_LFSR_CE_Q_ZQ
2927 27 unneback 
//////////////////////////////////////////////////////////////////////
2928 
////                                                              ////
2929 
////  Versatile counter                                           ////
2930 
////                                                              ////
2931 
////  Description                                                 ////
2932 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2933 
////  counter                                                     ////
2934 
////                                                              ////
2935 
////  To Do:                                                      ////
2936 
////   - add LFSR with more taps                                  ////
2937 
////                                                              ////
2938 
////  Author(s):                                                  ////
2939 
////      - Michael Unneback, unneback@opencores.org              ////
2940 
////        ORSoC AB                                              ////
2941 
////                                                              ////
2942 
//////////////////////////////////////////////////////////////////////
2943 
////                                                              ////
2944 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2945 
////                                                              ////
2946 
//// This source file may be used and distributed without         ////
2947 
//// restriction provided that this copyright statement is not    ////
2948 
//// removed from the file and that any derivative work contains  ////
2949 
//// the original copyright notice and the associated disclaimer. ////
2950 
////                                                              ////
2951 
//// This source file is free software; you can redistribute it   ////
2952 
//// and/or modify it under the terms of the GNU Lesser General   ////
2953 
//// Public License as published by the Free Software Foundation; ////
2954 
//// either version 2.1 of the License, or (at your option) any   ////
2955 
//// later version.                                               ////
2956 
////                                                              ////
2957 
//// This source is distributed in the hope that it will be       ////
2958 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2959 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2960 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2961 
//// details.                                                     ////
2962 
////                                                              ////
2963 
//// You should have received a copy of the GNU Lesser General    ////
2964 
//// Public License along with this source; if not, download it   ////
2965 
//// from http://www.opencores.org/lgpl.shtml                     ////
2966 
////                                                              ////
2967 
//////////////////////////////////////////////////////////////////////
2968 
 
2969 
// LFSR counter
2970 22 unneback 
 
2971 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2972 
module `BASE`MODULE (
2973 
`undef MODULE
2974 
 cke, q, zq, rst, clk);
2975 
 
2976 22 unneback 
   parameter length = 4;
2977 
   input cke;
2978 
   output [length:1] q;
2979 
   output reg zq;
2980 
   input rst;
2981 
   input clk;
2982 
 
2983 
   parameter clear_value = 0;
2984 
   parameter set_value = 1;
2985 
   parameter wrap_value = 8;
2986 
   parameter level1_value = 15;
2987 
 
2988 
   reg  [length:1] qi;
2989 
   reg lfsr_fb;
2990 
   wire [length:1] q_next;
2991 
   reg [32:1] polynom;
2992 
   integer i;
2993 
 
2994 
   always @ (qi)
2995 
   begin
2996 
        case (length)
2997 
         2: polynom = 32'b11;                               // 0x3
2998 
         3: polynom = 32'b110;                              // 0x6
2999 
         4: polynom = 32'b1100;                             // 0xC
3000 
         5: polynom = 32'b10100;                            // 0x14
3001 
         6: polynom = 32'b110000;                           // 0x30
3002 
         7: polynom = 32'b1100000;                          // 0x60
3003 
         8: polynom = 32'b10111000;                         // 0xb8
3004 
         9: polynom = 32'b100010000;                        // 0x110
3005 
        10: polynom = 32'b1001000000;                       // 0x240
3006 
        11: polynom = 32'b10100000000;                      // 0x500
3007 
        12: polynom = 32'b100000101001;                     // 0x829
3008 
        13: polynom = 32'b1000000001100;                    // 0x100C
3009 
        14: polynom = 32'b10000000010101;                   // 0x2015
3010 
        15: polynom = 32'b110000000000000;                  // 0x6000
3011 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3012 
        17: polynom = 32'b10010000000000000;                // 0x12000
3013 
        18: polynom = 32'b100000010000000000;               // 0x20400
3014 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3015 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3016 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3017 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3018 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3019 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3020 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3021 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3022 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3023 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3024 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3025 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3026 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3027 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3028 
        default: polynom = 32'b0;
3029 
        endcase
3030 
        lfsr_fb = qi[length];
3031 
        for (i=length-1; i>=1; i=i-1) begin
3032 
            if (polynom[i])
3033 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3034 
        end
3035 
    end
3036 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3037 
 
3038 
   always @ (posedge clk or posedge rst)
3039 
     if (rst)
3040 
       qi <= {length{1'b0}};
3041 
     else
3042 
     if (cke)
3043 
       qi <= q_next;
3044 
 
3045 
   assign q = qi;
3046 
 
3047 
 
3048 
   always @ (posedge clk or posedge rst)
3049 
     if (rst)
3050 
       zq <= 1'b1;
3051 
     else
3052 
     if (cke)
3053 
       zq <= q_next == {length{1'b0}};
3054 
endmodule
3055 40 unneback 
`endif
3056 
`ifdef CNT_LFSR_CE_REW_L1
3057 22 unneback 
//////////////////////////////////////////////////////////////////////
3058 
////                                                              ////
3059 
////  Versatile counter                                           ////
3060 
////                                                              ////
3061 
////  Description                                                 ////
3062 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3063 
////  counter                                                     ////
3064 
////                                                              ////
3065 
////  To Do:                                                      ////
3066 
////   - add LFSR with more taps                                  ////
3067 
////                                                              ////
3068 
////  Author(s):                                                  ////
3069 
////      - Michael Unneback, unneback@opencores.org              ////
3070 
////        ORSoC AB                                              ////
3071 
////                                                              ////
3072 
//////////////////////////////////////////////////////////////////////
3073 
////                                                              ////
3074 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3075 
////                                                              ////
3076 
//// This source file may be used and distributed without         ////
3077 
//// restriction provided that this copyright statement is not    ////
3078 
//// removed from the file and that any derivative work contains  ////
3079 
//// the original copyright notice and the associated disclaimer. ////
3080 
////                                                              ////
3081 
//// This source file is free software; you can redistribute it   ////
3082 
//// and/or modify it under the terms of the GNU Lesser General   ////
3083 
//// Public License as published by the Free Software Foundation; ////
3084 
//// either version 2.1 of the License, or (at your option) any   ////
3085 
//// later version.                                               ////
3086 
////                                                              ////
3087 
//// This source is distributed in the hope that it will be       ////
3088 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3089 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3090 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3091 
//// details.                                                     ////
3092 
////                                                              ////
3093 
//// You should have received a copy of the GNU Lesser General    ////
3094 
//// Public License along with this source; if not, download it   ////
3095 
//// from http://www.opencores.org/lgpl.shtml                     ////
3096 
////                                                              ////
3097 
//////////////////////////////////////////////////////////////////////
3098 6 unneback 
 
3099 
// LFSR counter
3100 
 
3101 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3102 
module `BASE`MODULE (
3103 
`undef MODULE
3104 
 cke, rew, level1, rst, clk);
3105 
 
3106 6 unneback 
   parameter length = 4;
3107 
   input cke;
3108 
   input rew;
3109 
   output reg level1;
3110 
   input rst;
3111 
   input clk;
3112 
 
3113 
   parameter clear_value = 0;
3114 
   parameter set_value = 1;
3115 
   parameter wrap_value = 8;
3116 
   parameter level1_value = 15;
3117 
 
3118 29 unneback 
   wire clear;
3119 30 unneback 
   assign clear = 1'b0;
3120 6 unneback 
   reg  [length:1] qi;
3121 
   reg lfsr_fb, lfsr_fb_rew;
3122 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3123 
   reg [32:1] polynom_rew;
3124 
   integer j;
3125 
   reg [32:1] polynom;
3126 
   integer i;
3127 
 
3128 
   always @ (qi)
3129 
   begin
3130 
        case (length)
3131 
         2: polynom = 32'b11;                               // 0x3
3132 
         3: polynom = 32'b110;                              // 0x6
3133 
         4: polynom = 32'b1100;                             // 0xC
3134 
         5: polynom = 32'b10100;                            // 0x14
3135 
         6: polynom = 32'b110000;                           // 0x30
3136 
         7: polynom = 32'b1100000;                          // 0x60
3137 
         8: polynom = 32'b10111000;                         // 0xb8
3138 
         9: polynom = 32'b100010000;                        // 0x110
3139 
        10: polynom = 32'b1001000000;                       // 0x240
3140 
        11: polynom = 32'b10100000000;                      // 0x500
3141 
        12: polynom = 32'b100000101001;                     // 0x829
3142 
        13: polynom = 32'b1000000001100;                    // 0x100C
3143 
        14: polynom = 32'b10000000010101;                   // 0x2015
3144 
        15: polynom = 32'b110000000000000;                  // 0x6000
3145 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3146 
        17: polynom = 32'b10010000000000000;                // 0x12000
3147 
        18: polynom = 32'b100000010000000000;               // 0x20400
3148 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3149 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3150 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3151 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3152 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3153 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3154 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3155 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3156 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3157 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3158 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3159 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3160 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3161 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3162 
        default: polynom = 32'b0;
3163 
        endcase
3164 
        lfsr_fb = qi[length];
3165 
        for (i=length-1; i>=1; i=i-1) begin
3166 
            if (polynom[i])
3167 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3168 
        end
3169 
    end
3170 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3171 
   always @ (qi)
3172 
   begin
3173 
        case (length)
3174 
         2: polynom_rew = 32'b11;
3175 
         3: polynom_rew = 32'b110;
3176 
         4: polynom_rew = 32'b1100;
3177 
         5: polynom_rew = 32'b10100;
3178 
         6: polynom_rew = 32'b110000;
3179 
         7: polynom_rew = 32'b1100000;
3180 
         8: polynom_rew = 32'b10111000;
3181 
         9: polynom_rew = 32'b100010000;
3182 
        10: polynom_rew = 32'b1001000000;
3183 
        11: polynom_rew = 32'b10100000000;
3184 
        12: polynom_rew = 32'b100000101001;
3185 
        13: polynom_rew = 32'b1000000001100;
3186 
        14: polynom_rew = 32'b10000000010101;
3187 
        15: polynom_rew = 32'b110000000000000;
3188 
        16: polynom_rew = 32'b1101000000001000;
3189 
        17: polynom_rew = 32'b10010000000000000;
3190 
        18: polynom_rew = 32'b100000010000000000;
3191 
        19: polynom_rew = 32'b1000000000000100011;
3192 
        20: polynom_rew = 32'b10000010000000000000;
3193 
        21: polynom_rew = 32'b101000000000000000000;
3194 
        22: polynom_rew = 32'b1100000000000000000000;
3195 
        23: polynom_rew = 32'b10000100000000000000000;
3196 
        24: polynom_rew = 32'b111000010000000000000000;
3197 
        25: polynom_rew = 32'b1001000000000000000000000;
3198 
        26: polynom_rew = 32'b10000000000000000000100011;
3199 
        27: polynom_rew = 32'b100000000000000000000010011;
3200 
        28: polynom_rew = 32'b1100100000000000000000000000;
3201 
        29: polynom_rew = 32'b10100000000000000000000000000;
3202 
        30: polynom_rew = 32'b100000000000000000000000101001;
3203 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3204 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3205 
        default: polynom_rew = 32'b0;
3206 
        endcase
3207 
        // rotate left
3208 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3209 
        lfsr_fb_rew = qi[length];
3210 
        for (i=length-1; i>=1; i=i-1) begin
3211 
            if (polynom_rew[i])
3212 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3213 
        end
3214 
    end
3215 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3216 
   assign q_next = rew ? q_next_rew : q_next_fw;
3217 
 
3218 
   always @ (posedge clk or posedge rst)
3219 
     if (rst)
3220 
       qi <= {length{1'b0}};
3221 
     else
3222 
     if (cke)
3223 
       qi <= q_next;
3224 
 
3225 
 
3226 
 
3227 
    always @ (posedge clk or posedge rst)
3228 
    if (rst)
3229 
        level1 <= 1'b0;
3230 
    else
3231 
    if (cke)
3232 29 unneback 
    if (clear)
3233 
        level1 <= 1'b0;
3234 
    else if (q_next == level1_value)
3235 6 unneback 
        level1 <= 1'b1;
3236 
    else if (qi == level1_value & rew)
3237 
        level1 <= 1'b0;
3238 
endmodule
3239 40 unneback 
`endif
3240 
`ifdef CNT_GRAY
3241 6 unneback 
//////////////////////////////////////////////////////////////////////
3242 
////                                                              ////
3243 
////  Versatile counter                                           ////
3244 
////                                                              ////
3245 
////  Description                                                 ////
3246 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3247 
////  counter                                                     ////
3248 
////                                                              ////
3249 
////  To Do:                                                      ////
3250 
////   - add LFSR with more taps                                  ////
3251 
////                                                              ////
3252 
////  Author(s):                                                  ////
3253 
////      - Michael Unneback, unneback@opencores.org              ////
3254 
////        ORSoC AB                                              ////
3255 
////                                                              ////
3256 
//////////////////////////////////////////////////////////////////////
3257 
////                                                              ////
3258 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3259 
////                                                              ////
3260 
//// This source file may be used and distributed without         ////
3261 
//// restriction provided that this copyright statement is not    ////
3262 
//// removed from the file and that any derivative work contains  ////
3263 
//// the original copyright notice and the associated disclaimer. ////
3264 
////                                                              ////
3265 
//// This source file is free software; you can redistribute it   ////
3266 
//// and/or modify it under the terms of the GNU Lesser General   ////
3267 
//// Public License as published by the Free Software Foundation; ////
3268 
//// either version 2.1 of the License, or (at your option) any   ////
3269 
//// later version.                                               ////
3270 
////                                                              ////
3271 
//// This source is distributed in the hope that it will be       ////
3272 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3273 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3274 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3275 
//// details.                                                     ////
3276 
////                                                              ////
3277 
//// You should have received a copy of the GNU Lesser General    ////
3278 
//// Public License along with this source; if not, download it   ////
3279 
//// from http://www.opencores.org/lgpl.shtml                     ////
3280 
////                                                              ////
3281 
//////////////////////////////////////////////////////////////////////
3282 
 
3283 
// GRAY counter
3284 
 
3285 40 unneback 
`define MODULE cnt_gray
3286 
module `BASE`MODULE (
3287 
`undef MODULE
3288 
 q, rst, clk);
3289 
 
3290 6 unneback 
   parameter length = 4;
3291 
   output reg [length:1] q;
3292 
   input rst;
3293 
   input clk;
3294 
 
3295 
   parameter clear_value = 0;
3296 
   parameter set_value = 1;
3297 
   parameter wrap_value = 8;
3298 
   parameter level1_value = 15;
3299 
 
3300 
   reg  [length:1] qi;
3301 
   wire [length:1] q_next;
3302 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3303 
 
3304 
   always @ (posedge clk or posedge rst)
3305 
     if (rst)
3306 
       qi <= {length{1'b0}};
3307 
     else
3308 
       qi <= q_next;
3309 
 
3310 
   always @ (posedge clk or posedge rst)
3311 
     if (rst)
3312 
       q <= {length{1'b0}};
3313 
     else
3314 
         q <= (q_next>>1) ^ q_next;
3315 
 
3316 
endmodule
3317 40 unneback 
`endif
3318 
`ifdef CNT_GRAY_CE
3319 6 unneback 
//////////////////////////////////////////////////////////////////////
3320 
////                                                              ////
3321 
////  Versatile counter                                           ////
3322 
////                                                              ////
3323 
////  Description                                                 ////
3324 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3325 
////  counter                                                     ////
3326 
////                                                              ////
3327 
////  To Do:                                                      ////
3328 
////   - add LFSR with more taps                                  ////
3329 
////                                                              ////
3330 
////  Author(s):                                                  ////
3331 
////      - Michael Unneback, unneback@opencores.org              ////
3332 
////        ORSoC AB                                              ////
3333 
////                                                              ////
3334 
//////////////////////////////////////////////////////////////////////
3335 
////                                                              ////
3336 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3337 
////                                                              ////
3338 
//// This source file may be used and distributed without         ////
3339 
//// restriction provided that this copyright statement is not    ////
3340 
//// removed from the file and that any derivative work contains  ////
3341 
//// the original copyright notice and the associated disclaimer. ////
3342 
////                                                              ////
3343 
//// This source file is free software; you can redistribute it   ////
3344 
//// and/or modify it under the terms of the GNU Lesser General   ////
3345 
//// Public License as published by the Free Software Foundation; ////
3346 
//// either version 2.1 of the License, or (at your option) any   ////
3347 
//// later version.                                               ////
3348 
////                                                              ////
3349 
//// This source is distributed in the hope that it will be       ////
3350 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3351 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3352 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3353 
//// details.                                                     ////
3354 
////                                                              ////
3355 
//// You should have received a copy of the GNU Lesser General    ////
3356 
//// Public License along with this source; if not, download it   ////
3357 
//// from http://www.opencores.org/lgpl.shtml                     ////
3358 
////                                                              ////
3359 
//////////////////////////////////////////////////////////////////////
3360 
 
3361 
// GRAY counter
3362 
 
3363 40 unneback 
`define MODULE cnt_gray_ce
3364 
module `BASE`MODULE (
3365 
`undef MODULE
3366 
 cke, q, rst, clk);
3367 
 
3368 6 unneback 
   parameter length = 4;
3369 
   input cke;
3370 
   output reg [length:1] q;
3371 
   input rst;
3372 
   input clk;
3373 
 
3374 
   parameter clear_value = 0;
3375 
   parameter set_value = 1;
3376 
   parameter wrap_value = 8;
3377 
   parameter level1_value = 15;
3378 
 
3379 
   reg  [length:1] qi;
3380 
   wire [length:1] q_next;
3381 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3382 
 
3383 
   always @ (posedge clk or posedge rst)
3384 
     if (rst)
3385 
       qi <= {length{1'b0}};
3386 
     else
3387 
     if (cke)
3388 
       qi <= q_next;
3389 
 
3390 
   always @ (posedge clk or posedge rst)
3391 
     if (rst)
3392 
       q <= {length{1'b0}};
3393 
     else
3394 
       if (cke)
3395 
         q <= (q_next>>1) ^ q_next;
3396 
 
3397 
endmodule
3398 40 unneback 
`endif
3399 
`ifdef CNT_GRAY_CE_BIN
3400 6 unneback 
//////////////////////////////////////////////////////////////////////
3401 
////                                                              ////
3402 
////  Versatile counter                                           ////
3403 
////                                                              ////
3404 
////  Description                                                 ////
3405 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3406 
////  counter                                                     ////
3407 
////                                                              ////
3408 
////  To Do:                                                      ////
3409 
////   - add LFSR with more taps                                  ////
3410 
////                                                              ////
3411 
////  Author(s):                                                  ////
3412 
////      - Michael Unneback, unneback@opencores.org              ////
3413 
////        ORSoC AB                                              ////
3414 
////                                                              ////
3415 
//////////////////////////////////////////////////////////////////////
3416 
////                                                              ////
3417 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3418 
////                                                              ////
3419 
//// This source file may be used and distributed without         ////
3420 
//// restriction provided that this copyright statement is not    ////
3421 
//// removed from the file and that any derivative work contains  ////
3422 
//// the original copyright notice and the associated disclaimer. ////
3423 
////                                                              ////
3424 
//// This source file is free software; you can redistribute it   ////
3425 
//// and/or modify it under the terms of the GNU Lesser General   ////
3426 
//// Public License as published by the Free Software Foundation; ////
3427 
//// either version 2.1 of the License, or (at your option) any   ////
3428 
//// later version.                                               ////
3429 
////                                                              ////
3430 
//// This source is distributed in the hope that it will be       ////
3431 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3432 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3433 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3434 
//// details.                                                     ////
3435 
////                                                              ////
3436 
//// You should have received a copy of the GNU Lesser General    ////
3437 
//// Public License along with this source; if not, download it   ////
3438 
//// from http://www.opencores.org/lgpl.shtml                     ////
3439 
////                                                              ////
3440 
//////////////////////////////////////////////////////////////////////
3441 
 
3442 
// GRAY counter
3443 
 
3444 40 unneback 
`define MODULE cnt_gray_ce_bin
3445 
module `BASE`MODULE (
3446 
`undef MODULE
3447 
 cke, q, q_bin, rst, clk);
3448 
 
3449 6 unneback 
   parameter length = 4;
3450 
   input cke;
3451 
   output reg [length:1] q;
3452 
   output [length:1] q_bin;
3453 
   input rst;
3454 
   input clk;
3455 
 
3456 
   parameter clear_value = 0;
3457 
   parameter set_value = 1;
3458 
   parameter wrap_value = 8;
3459 
   parameter level1_value = 15;
3460 
 
3461 
   reg  [length:1] qi;
3462 
   wire [length:1] q_next;
3463 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3464 
 
3465 
   always @ (posedge clk or posedge rst)
3466 
     if (rst)
3467 
       qi <= {length{1'b0}};
3468 
     else
3469 
     if (cke)
3470 
       qi <= q_next;
3471 
 
3472 
   always @ (posedge clk or posedge rst)
3473 
     if (rst)
3474 
       q <= {length{1'b0}};
3475 
     else
3476 
       if (cke)
3477 
         q <= (q_next>>1) ^ q_next;
3478 
 
3479 
   assign q_bin = qi;
3480 
 
3481 
endmodule
3482 40 unneback 
`endif
3483 6 unneback 
//////////////////////////////////////////////////////////////////////
3484 
////                                                              ////
3485 
////  Versatile library, counters                                 ////
3486 
////                                                              ////
3487 
////  Description                                                 ////
3488 
////  counters                                                    ////
3489 
////                                                              ////
3490 
////                                                              ////
3491 
////  To Do:                                                      ////
3492 
////   - add more counters                                        ////
3493 
////                                                              ////
3494 
////  Author(s):                                                  ////
3495 
////      - Michael Unneback, unneback@opencores.org              ////
3496 
////        ORSoC AB                                              ////
3497 
////                                                              ////
3498 
//////////////////////////////////////////////////////////////////////
3499 
////                                                              ////
3500 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3501 
////                                                              ////
3502 
//// This source file may be used and distributed without         ////
3503 
//// restriction provided that this copyright statement is not    ////
3504 
//// removed from the file and that any derivative work contains  ////
3505 
//// the original copyright notice and the associated disclaimer. ////
3506 
////                                                              ////
3507 
//// This source file is free software; you can redistribute it   ////
3508 
//// and/or modify it under the terms of the GNU Lesser General   ////
3509 
//// Public License as published by the Free Software Foundation; ////
3510 
//// either version 2.1 of the License, or (at your option) any   ////
3511 
//// later version.                                               ////
3512 
////                                                              ////
3513 
//// This source is distributed in the hope that it will be       ////
3514 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3515 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3516 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3517 
//// details.                                                     ////
3518 
////                                                              ////
3519 
//// You should have received a copy of the GNU Lesser General    ////
3520 
//// Public License along with this source; if not, download it   ////
3521 
//// from http://www.opencores.org/lgpl.shtml                     ////
3522 
////                                                              ////
3523 
//////////////////////////////////////////////////////////////////////
3524 
 
3525 40 unneback 
`ifdef CNT_SHREG_WRAP
3526 
`define MODULE cnt_shreg_wrap
3527 
module `BASE`MODULE ( q, rst, clk);
3528 
`undef MODULE
3529 6 unneback 
 
3530 
   parameter length = 4;
3531 
   output reg [0:length-1] q;
3532 
   input rst;
3533 
   input clk;
3534 
 
3535 
    always @ (posedge clk or posedge rst)
3536 
    if (rst)
3537 
        q <= {1'b1,{length-1{1'b0}}};
3538 
    else
3539 
        q <= {q[length-1],q[0:length-2]};
3540 
 
3541 
endmodule
3542 40 unneback 
`endif
3543 6 unneback 
 
3544 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3545 
`define MODULE cnt_shreg_ce_wrap
3546 
module `BASE`MODULE ( cke, q, rst, clk);
3547 
`undef MODULE
3548 6 unneback 
 
3549 
   parameter length = 4;
3550 
   input cke;
3551 
   output reg [0:length-1] q;
3552 
   input rst;
3553 
   input clk;
3554 
 
3555 
    always @ (posedge clk or posedge rst)
3556 
    if (rst)
3557 
        q <= {1'b1,{length-1{1'b0}}};
3558 
    else
3559 
        if (cke)
3560 
            q <= {q[length-1],q[0:length-2]};
3561 
 
3562 
endmodule
3563 40 unneback 
`endif
3564 6 unneback 
 
3565 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3566 
`define MODULE cnt_shreg_ce_clear
3567 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3568 
`undef MODULE
3569 6 unneback 
 
3570 
   parameter length = 4;
3571 
   input cke, clear;
3572 
   output reg [0:length-1] q;
3573 
   input rst;
3574 
   input clk;
3575 
 
3576 
    always @ (posedge clk or posedge rst)
3577 
    if (rst)
3578 
        q <= {1'b1,{length-1{1'b0}}};
3579 
    else
3580 
        if (cke)
3581 
            if (clear)
3582 
                q <= {1'b1,{length-1{1'b0}}};
3583 
            else
3584 
                q <= q >> 1;
3585 
 
3586 
endmodule
3587 40 unneback 
`endif
3588 6 unneback 
 
3589 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3590 
`define MODULE cnt_shreg_ce_clear_wrap
3591 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3592 
`undef MODULE
3593 6 unneback 
 
3594 
   parameter length = 4;
3595 
   input cke, clear;
3596 
   output reg [0:length-1] q;
3597 
   input rst;
3598 
   input clk;
3599 
 
3600 
    always @ (posedge clk or posedge rst)
3601 
    if (rst)
3602 
        q <= {1'b1,{length-1{1'b0}}};
3603 
    else
3604 
        if (cke)
3605 
            if (clear)
3606 
                q <= {1'b1,{length-1{1'b0}}};
3607 
            else
3608 
            q <= {q[length-1],q[0:length-2]};
3609 
 
3610 
endmodule
3611 40 unneback 
`endif
3612 6 unneback 
//////////////////////////////////////////////////////////////////////
3613 
////                                                              ////
3614 
////  Versatile library, memories                                 ////
3615 
////                                                              ////
3616 
////  Description                                                 ////
3617 
////  memories                                                    ////
3618 
////                                                              ////
3619 
////                                                              ////
3620 
////  To Do:                                                      ////
3621 
////   - add more memory types                                    ////
3622 
////                                                              ////
3623 
////  Author(s):                                                  ////
3624 
////      - Michael Unneback, unneback@opencores.org              ////
3625 
////        ORSoC AB                                              ////
3626 
////                                                              ////
3627 
//////////////////////////////////////////////////////////////////////
3628 
////                                                              ////
3629 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3630 
////                                                              ////
3631 
//// This source file may be used and distributed without         ////
3632 
//// restriction provided that this copyright statement is not    ////
3633 
//// removed from the file and that any derivative work contains  ////
3634 
//// the original copyright notice and the associated disclaimer. ////
3635 
////                                                              ////
3636 
//// This source file is free software; you can redistribute it   ////
3637 
//// and/or modify it under the terms of the GNU Lesser General   ////
3638 
//// Public License as published by the Free Software Foundation; ////
3639 
//// either version 2.1 of the License, or (at your option) any   ////
3640 
//// later version.                                               ////
3641 
////                                                              ////
3642 
//// This source is distributed in the hope that it will be       ////
3643 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3644 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3645 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3646 
//// details.                                                     ////
3647 
////                                                              ////
3648 
//// You should have received a copy of the GNU Lesser General    ////
3649 
//// Public License along with this source; if not, download it   ////
3650 
//// from http://www.opencores.org/lgpl.shtml                     ////
3651 
////                                                              ////
3652 
//////////////////////////////////////////////////////////////////////
3653 
 
3654 40 unneback 
`ifdef ROM_INIT
3655 6 unneback 
/// ROM
3656 40 unneback 
`define MODULE rom_init
3657 
module `BASE`MODULE ( adr, q, clk);
3658 
`undef MODULE
3659 6 unneback 
 
3660 7 unneback 
   parameter data_width = 32;
3661 
   parameter addr_width = 8;
3662 75 unneback 
   parameter mem_size = 1<<addr_width;
3663 7 unneback 
   input [(addr_width-1):0]       adr;
3664 
   output reg [(data_width-1):0] q;
3665 
   input                         clk;
3666 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3667 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3668 
   initial
3669 
     begin
3670 
        $readmemh(memory_file, rom);
3671 
     end
3672 
 
3673 
   always @ (posedge clk)
3674 
     q <= rom[adr];
3675 6 unneback 
 
3676 7 unneback 
endmodule
3677 40 unneback 
`endif
3678 7 unneback 
 
3679 40 unneback 
`ifdef RAM
3680 
`define MODULE ram
3681 6 unneback 
// Single port RAM
3682 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3683 
`undef MODULE
3684 6 unneback 
 
3685 
   parameter data_width = 32;
3686 
   parameter addr_width = 8;
3687 75 unneback 
   parameter mem_size = 1<<addr_width;
3688 6 unneback 
   input [(data_width-1):0]      d;
3689 
   input [(addr_width-1):0]       adr;
3690 
   input                         we;
3691 7 unneback 
   output reg [(data_width-1):0] q;
3692 6 unneback 
   input                         clk;
3693 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0];
3694 7 unneback 
   parameter init = 0;
3695 
   parameter memory_file = "vl_ram.vmem";
3696 
   generate if (init) begin : init_mem
3697 
   initial
3698 
     begin
3699 
        $readmemh(memory_file, ram);
3700 
     end
3701 
   end
3702 
   endgenerate
3703 
 
3704 6 unneback 
   always @ (posedge clk)
3705 
   begin
3706 
   if (we)
3707 
     ram[adr] <= d;
3708 
   q <= ram[adr];
3709 
   end
3710 
 
3711 
endmodule
3712 40 unneback 
`endif
3713 6 unneback 
 
3714 40 unneback 
`ifdef RAM_BE
3715 
`define MODULE ram_be
3716 91 unneback 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3717 40 unneback 
`undef MODULE
3718 
 
3719 7 unneback 
   parameter data_width = 32;
3720 72 unneback 
   parameter addr_width = 6;
3721 75 unneback 
   parameter mem_size = 1<<addr_width;
3722 7 unneback 
   input [(data_width-1):0]      d;
3723 
   input [(addr_width-1):0]       adr;
3724 73 unneback 
   input [(data_width/8)-1:0]    be;
3725 7 unneback 
   input                         we;
3726 
   output reg [(data_width-1):0] q;
3727 
   input                         clk;
3728 
 
3729 85 unneback 
 
3730 65 unneback 
`ifdef SYSTEMVERILOG
3731 68 unneback 
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
3732 65 unneback 
`else
3733 85 unneback 
    reg [data_width-1:0] ram [mem_size-1:0];
3734 
    wire [data_width/8-1:0] cke;
3735 65 unneback 
`endif
3736 
 
3737 60 unneback 
   parameter memory_init = 0;
3738 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3739 60 unneback 
   generate if (memory_init) begin : init_mem
3740 7 unneback 
   initial
3741 
     begin
3742 
        $readmemh(memory_file, ram);
3743 
     end
3744 
   end
3745 
   endgenerate
3746 
 
3747 60 unneback 
`ifdef SYSTEMVERILOG
3748 
// use a multi-dimensional packed array
3749 
//to model individual bytes within the word
3750 
 
3751 
always_ff@(posedge clk)
3752 
begin
3753 
    if(we) begin // note: we should have a for statement to support any bus width
3754 86 unneback 
        if(be[3]) ram[adr][3] <= d[31:24];
3755 
        if(be[2]) ram[adr][2] <= d[23:16];
3756 
        if(be[1]) ram[adr][1] <= d[15:8];
3757 
        if(be[0]) ram[adr][0] <= d[7:0];
3758 60 unneback 
    end
3759 90 unneback 
        q <= ram[adr];
3760 60 unneback 
end
3761 
 
3762 
`else
3763 
 
3764 85 unneback 
assign cke = {data_width/8{we}} & be;
3765 7 unneback 
   genvar i;
3766 85 unneback 
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3767 7 unneback 
      always @ (posedge clk)
3768 85 unneback 
      if (cke[i])
3769 7 unneback 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3770 
   end
3771 
   endgenerate
3772 
 
3773 
   always @ (posedge clk)
3774 
      q <= ram[adr];
3775 
 
3776 60 unneback 
`endif
3777 
 
3778 85 unneback 
   // Function to access RAM (for use by Verilator).
3779 
   function [31:0] get_mem;
3780 
      // verilator public
3781 90 unneback 
      input [addr_width-1:0]             addr;
3782 85 unneback 
      get_mem = ram[addr];
3783 
   endfunction // get_mem
3784 
 
3785 
   // Function to write RAM (for use by Verilator).
3786 
   function set_mem;
3787 
      // verilator public
3788 90 unneback 
      input [addr_width-1:0]             addr;
3789 
      input [data_width-1:0]             data;
3790 85 unneback 
      ram[addr] = data;
3791 
   endfunction // set_mem
3792 
 
3793 7 unneback 
endmodule
3794 40 unneback 
`endif
3795 7 unneback 
 
3796 6 unneback 
`ifdef ACTEL
3797 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3798 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3799 
`else
3800 
        `define SYN
3801 
`endif
3802 
 
3803 40 unneback 
`ifdef DPRAM_1R1W
3804 
`define MODULE dpram_1r1w
3805 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3806 
`undef MODULE
3807 6 unneback 
   parameter data_width = 32;
3808 
   parameter addr_width = 8;
3809 75 unneback 
   parameter mem_size = 1<<addr_width;
3810 6 unneback 
   input [(data_width-1):0]      d_a;
3811 
   input [(addr_width-1):0]       adr_a;
3812 
   input [(addr_width-1):0]       adr_b;
3813 
   input                         we_a;
3814 
   output [(data_width-1):0]      q_b;
3815 
   input                         clk_a, clk_b;
3816 
   reg [(addr_width-1):0]         adr_b_reg;
3817 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3818 7 unneback 
 
3819 
   parameter init = 0;
3820 
   parameter memory_file = "vl_ram.vmem";
3821 
   generate if (init) begin : init_mem
3822 
   initial
3823 
     begin
3824 
        $readmemh(memory_file, ram);
3825 
     end
3826 
   end
3827 
   endgenerate
3828 
 
3829 6 unneback 
   always @ (posedge clk_a)
3830 
   if (we_a)
3831 
     ram[adr_a] <= d_a;
3832 
   always @ (posedge clk_b)
3833 
   adr_b_reg <= adr_b;
3834 
   assign q_b = ram[adr_b_reg];
3835 40 unneback 
 
3836 6 unneback 
endmodule
3837 40 unneback 
`endif
3838 6 unneback 
 
3839 40 unneback 
`ifdef DPRAM_2R1W
3840 
`define MODULE dpram_2r1w
3841 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3842 
`undef MODULE
3843 
 
3844 6 unneback 
   parameter data_width = 32;
3845 
   parameter addr_width = 8;
3846 75 unneback 
   parameter mem_size = 1<<addr_width;
3847 6 unneback 
   input [(data_width-1):0]      d_a;
3848 
   input [(addr_width-1):0]       adr_a;
3849 
   input [(addr_width-1):0]       adr_b;
3850 
   input                         we_a;
3851 
   output [(data_width-1):0]      q_b;
3852 
   output reg [(data_width-1):0] q_a;
3853 
   input                         clk_a, clk_b;
3854 
   reg [(data_width-1):0]         q_b;
3855 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3856 7 unneback 
 
3857 
   parameter init = 0;
3858 
   parameter memory_file = "vl_ram.vmem";
3859 
   generate if (init) begin : init_mem
3860 
   initial
3861 
     begin
3862 
        $readmemh(memory_file, ram);
3863 
     end
3864 
   end
3865 
   endgenerate
3866 
 
3867 6 unneback 
   always @ (posedge clk_a)
3868 
     begin
3869 
        q_a <= ram[adr_a];
3870 
        if (we_a)
3871 
             ram[adr_a] <= d_a;
3872 
     end
3873 
   always @ (posedge clk_b)
3874 
          q_b <= ram[adr_b];
3875 
endmodule
3876 40 unneback 
`endif
3877 6 unneback 
 
3878 40 unneback 
`ifdef DPRAM_2R2W
3879 
`define MODULE dpram_2r2w
3880 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3881 
`undef MODULE
3882 
 
3883 6 unneback 
   parameter data_width = 32;
3884 
   parameter addr_width = 8;
3885 75 unneback 
   parameter mem_size = 1<<addr_width;
3886 6 unneback 
   input [(data_width-1):0]      d_a;
3887 
   input [(addr_width-1):0]       adr_a;
3888 
   input [(addr_width-1):0]       adr_b;
3889 
   input                         we_a;
3890 
   output [(data_width-1):0]      q_b;
3891 
   input [(data_width-1):0]       d_b;
3892 
   output reg [(data_width-1):0] q_a;
3893 
   input                         we_b;
3894 
   input                         clk_a, clk_b;
3895 
   reg [(data_width-1):0]         q_b;
3896 75 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
3897 7 unneback 
 
3898 
   parameter init = 0;
3899 
   parameter memory_file = "vl_ram.vmem";
3900 
   generate if (init) begin : init_mem
3901 
   initial
3902 
     begin
3903 
        $readmemh(memory_file, ram);
3904 
     end
3905 
   end
3906 
   endgenerate
3907 
 
3908 6 unneback 
   always @ (posedge clk_a)
3909 
     begin
3910 
        q_a <= ram[adr_a];
3911 
        if (we_a)
3912 
             ram[adr_a] <= d_a;
3913 
     end
3914 
   always @ (posedge clk_b)
3915 
     begin
3916 
        q_b <= ram[adr_b];
3917 
        if (we_b)
3918 
          ram[adr_b] <= d_b;
3919 
     end
3920 
endmodule
3921 40 unneback 
`endif
3922 6 unneback 
 
3923 83 unneback 
 
3924 75 unneback 
`ifdef DPRAM_BE_2R2W
3925 
`define MODULE dpram_be_2r2w
3926 91 unneback 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
3927 75 unneback 
`undef MODULE
3928 
 
3929 
   parameter a_data_width = 32;
3930 
   parameter a_addr_width = 8;
3931 91 unneback 
   parameter b_data_width = 32;
3932 
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
3933 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
3934 
 
3935 75 unneback 
   input [(a_data_width-1):0]      d_a;
3936 91 unneback 
   input [(a_addr_width-1):0]       adr_a;
3937 
   input [(a_data_width/8-1):0]    be_a;
3938 
   input                           re_a;
3939 
   input                           we_a;
3940 75 unneback 
   output reg [(a_data_width-1):0] q_a;
3941 91 unneback 
   input [(b_data_width-1):0]       d_b;
3942 
   input [(b_addr_width-1):0]       adr_b;
3943 
   input                           re_b,we_b;
3944 
   output [(b_data_width-1):0]      q_b;
3945 
   input                           clk_a, clk_b;
3946 75 unneback 
 
3947 91 unneback 
`ifdef SYSTEMVERILOG
3948 
// use a multi-dimensional packed array
3949 
//to model individual bytes within the word
3950 
 
3951 75 unneback 
generate
3952 91 unneback 
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
3953 75 unneback 
 
3954 91 unneback 
   logic [3:0][7:0] ram [0:mem_size-1];
3955 
    reg [a_addr_width-1:0] rd_adr_a;
3956 
    reg [b_addr_width-1:0] rd_adr_b;
3957 
 
3958 
    always_ff@(posedge clk_a)
3959 
    begin
3960 
        if(we_a) begin
3961 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
3962 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
3963 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
3964 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
3965 
        end
3966 
    end
3967 
 
3968 
    always@(posedge clk_a or posedge rst)
3969 
    if (rst)
3970 
        rd_adr_a <= 0;
3971 
    else if (re_a)
3972 
        rd_adr_a <= adr_a;
3973 
 
3974 
    assign q_a = ram[rd_adr_a];
3975 
 
3976 
    always_ff@(posedge clk_b)
3977 
    if(we_b)
3978 
        ram[adr_b] <= d_b;
3979 
 
3980 
    always@(posedge clk_b or posedge rst)
3981 
    if (rst)
3982 
        rd_adr_b <= 0;
3983 
    else if (re_b)
3984 
        rd_adr_b <= adr_b;
3985 
 
3986 
    assign q_b = ram[rd_adr_b];
3987 
 
3988 75 unneback 
end
3989 
endgenerate
3990 
 
3991 91 unneback 
`else
3992 
`endif
3993 75 unneback 
endmodule
3994 
`endif
3995 
 
3996 91 unneback 
`ifdef CAM
3997 6 unneback 
// Content addresable memory, CAM
3998 91 unneback 
`endif
3999 6 unneback 
 
4000 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4001 6 unneback 
// FIFO
4002 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4003 
module `BASE`MODULE (
4004 
`undef MODULE
4005 25 unneback 
    d, wr, fifo_full,
4006 
    q, rd, fifo_empty,
4007 
    fill_level,
4008 
    clk, rst
4009 
    );
4010 
 
4011 
parameter data_width = 18;
4012 
parameter addr_width = 4;
4013 6 unneback 
 
4014 25 unneback 
// write side
4015 
input  [data_width-1:0] d;
4016 
input                   wr;
4017 
output                  fifo_full;
4018 
// read side
4019 
output [data_width-1:0] q;
4020 
input                   rd;
4021 
output                  fifo_empty;
4022 
// common
4023 
output [addr_width:0]   fill_level;
4024 
input rst, clk;
4025 
 
4026 
wire [addr_width:1] wadr, radr;
4027 
 
4028 40 unneback 
`define MODULE cnt_bin_ce
4029 
`BASE`MODULE
4030 25 unneback 
    # ( .length(addr_width))
4031 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4032 40 unneback 
`BASE`MODULE
4033 25 unneback 
    # (.length(addr_width))
4034 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4035 40 unneback 
`undef MODULE
4036 25 unneback 
 
4037 40 unneback 
`define MODULE dpram_1r1w
4038 
`BASE`MODULE
4039 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4040 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4041 40 unneback 
`undef MODULE
4042 25 unneback 
 
4043 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4044 
`BASE`MODULE
4045 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4046 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4047 40 unneback 
`undef MODULE
4048 25 unneback 
endmodule
4049 40 unneback 
`endif
4050 25 unneback 
 
4051 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4052 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4053 
// RAM is supposed to be larger than the two FIFOs
4054 
// LFSR counters used adr pointers
4055 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4056 
module `BASE`MODULE (
4057 
`undef MODULE
4058 27 unneback 
    // a side
4059 
    a_d, a_wr, a_fifo_full,
4060 
    a_q, a_rd, a_fifo_empty,
4061 
    a_fill_level,
4062 
    // b side
4063 
    b_d, b_wr, b_fifo_full,
4064 
    b_q, b_rd, b_fifo_empty,
4065 
    b_fill_level,
4066 
    // common
4067 
    clk, rst
4068 
    );
4069 
parameter data_width = 8;
4070 
parameter addr_width = 5;
4071 
parameter fifo_full_level = (1<<addr_width)-1;
4072 
 
4073 
// a side
4074 
input  [data_width-1:0] a_d;
4075 
input                   a_wr;
4076 
output                  a_fifo_full;
4077 
output [data_width-1:0] a_q;
4078 
input                   a_rd;
4079 
output                  a_fifo_empty;
4080 
output [addr_width-1:0] a_fill_level;
4081 
 
4082 
// b side
4083 
input  [data_width-1:0] b_d;
4084 
input                   b_wr;
4085 
output                  b_fifo_full;
4086 
output [data_width-1:0] b_q;
4087 
input                   b_rd;
4088 
output                  b_fifo_empty;
4089 
output [addr_width-1:0] b_fill_level;
4090 
 
4091 
input                   clk;
4092 
input                   rst;
4093 
 
4094 
// adr_gen
4095 
wire [addr_width:1] a_wadr, a_radr;
4096 
wire [addr_width:1] b_wadr, b_radr;
4097 
// dpram
4098 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4099 
 
4100 40 unneback 
`define MODULE cnt_lfsr_ce
4101 
`BASE`MODULE
4102 27 unneback 
    # ( .length(addr_width))
4103 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4104 
 
4105 40 unneback 
`BASE`MODULE
4106 27 unneback 
    # (.length(addr_width))
4107 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4108 
 
4109 40 unneback 
`BASE`MODULE
4110 27 unneback 
    # ( .length(addr_width))
4111 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4112 
 
4113 40 unneback 
`BASE`MODULE
4114 27 unneback 
    # (.length(addr_width))
4115 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4116 40 unneback 
`undef MODULE
4117 27 unneback 
 
4118 
// mux read or write adr to DPRAM
4119 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4120 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4121 
 
4122 40 unneback 
`define MODULE dpram_2r2w
4123 
`BASE`MODULE
4124 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4125 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4126 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4127 40 unneback 
`undef MODULE
4128 
 
4129 
`define MODULE cnt_bin_ce_rew_zq_l1
4130 
`BASE`MODULE
4131 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4132 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4133 
 
4134 40 unneback 
`BASE`MODULE
4135 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4136 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4137 40 unneback 
`undef MODULE
4138 27 unneback 
 
4139 
endmodule
4140 40 unneback 
`endif
4141 27 unneback 
 
4142 40 unneback 
`ifdef FIFO_CMP_ASYNC
4143 
`define MODULE fifo_cmp_async
4144 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4145 
`undef MODULE
4146 6 unneback 
 
4147 11 unneback 
   parameter addr_width = 4;
4148 
   parameter N = addr_width-1;
4149 6 unneback 
 
4150 
   parameter Q1 = 2'b00;
4151 
   parameter Q2 = 2'b01;
4152 
   parameter Q3 = 2'b11;
4153 
   parameter Q4 = 2'b10;
4154 
 
4155 
   parameter going_empty = 1'b0;
4156 
   parameter going_full  = 1'b1;
4157 
 
4158 
   input [N:0]  wptr, rptr;
4159 14 unneback 
   output       fifo_empty;
4160 6 unneback 
   output       fifo_full;
4161 
   input        wclk, rclk, rst;
4162 
 
4163 
`ifndef GENERATE_DIRECTION_AS_LATCH
4164 
   wire direction;
4165 
`endif
4166 
`ifdef GENERATE_DIRECTION_AS_LATCH
4167 
   reg direction;
4168 
`endif
4169 
   reg  direction_set, direction_clr;
4170 
 
4171 
   wire async_empty, async_full;
4172 
   wire fifo_full2;
4173 14 unneback 
   wire fifo_empty2;
4174 6 unneback 
 
4175 
   // direction_set
4176 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4177 
     case ({wptr[N:N-1],rptr[N:N-1]})
4178 
       {Q1,Q2} : direction_set <= 1'b1;
4179 
       {Q2,Q3} : direction_set <= 1'b1;
4180 
       {Q3,Q4} : direction_set <= 1'b1;
4181 
       {Q4,Q1} : direction_set <= 1'b1;
4182 
       default : direction_set <= 1'b0;
4183 
     endcase
4184 
 
4185 
   // direction_clear
4186 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4187 
     if (rst)
4188 
       direction_clr <= 1'b1;
4189 
     else
4190 
       case ({wptr[N:N-1],rptr[N:N-1]})
4191 
         {Q2,Q1} : direction_clr <= 1'b1;
4192 
         {Q3,Q2} : direction_clr <= 1'b1;
4193 
         {Q4,Q3} : direction_clr <= 1'b1;
4194 
         {Q1,Q4} : direction_clr <= 1'b1;
4195 
         default : direction_clr <= 1'b0;
4196 
       endcase
4197 
 
4198 40 unneback 
`define MODULE dff_sr
4199 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4200 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4201 6 unneback 
`endif
4202 
 
4203 
`ifdef GENERATE_DIRECTION_AS_LATCH
4204 
   always @ (posedge direction_set or posedge direction_clr)
4205 
     if (direction_clr)
4206 
       direction <= going_empty;
4207 
     else
4208 
       direction <= going_full;
4209 
`endif
4210 
 
4211 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4212 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4213 
 
4214 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4215 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4216 
`undef MODULE
4217 6 unneback 
 
4218 
/*
4219 
   always @ (posedge wclk or posedge rst or posedge async_full)
4220 
     if (rst)
4221 
       {fifo_full, fifo_full2} <= 2'b00;
4222 
     else if (async_full)
4223 
       {fifo_full, fifo_full2} <= 2'b11;
4224 
     else
4225 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4226 
*/
4227 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4228 6 unneback 
     if (async_empty)
4229 
       {fifo_empty, fifo_empty2} <= 2'b11;
4230 
     else
4231 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4232 40 unneback 
`define MODULE dff
4233 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4234 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4235 
`undef MODULE
4236 27 unneback 
endmodule // async_compb
4237 40 unneback 
`endif
4238 6 unneback 
 
4239 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4240 
`define MODULE fifo_1r1w_async
4241 
module `BASE`MODULE (
4242 
`undef MODULE
4243 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4244 
    q, rd, fifo_empty, rd_clk, rd_rst
4245 
    );
4246 
 
4247 
parameter data_width = 18;
4248 
parameter addr_width = 4;
4249 
 
4250 
// write side
4251 
input  [data_width-1:0] d;
4252 
input                   wr;
4253 
output                  fifo_full;
4254 
input                   wr_clk;
4255 
input                   wr_rst;
4256 
// read side
4257 
output [data_width-1:0] q;
4258 
input                   rd;
4259 
output                  fifo_empty;
4260 
input                   rd_clk;
4261 
input                   rd_rst;
4262 
 
4263 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4264 23 unneback 
 
4265 40 unneback 
`define MODULE cnt_gray_ce_bin
4266 
`BASE`MODULE
4267 6 unneback 
    # ( .length(addr_width))
4268 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4269 
 
4270 40 unneback 
`BASE`MODULE
4271 6 unneback 
    # (.length(addr_width))
4272 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4273 40 unneback 
`undef MODULE
4274 6 unneback 
 
4275 40 unneback 
`define MODULE dpram_1r1w
4276 
`BASE`MODULE
4277 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4278 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4279 40 unneback 
`undef MODULE
4280 6 unneback 
 
4281 40 unneback 
`define MODULE fifo_cmp_async
4282 
`BASE`MODULE
4283 6 unneback 
    # (.addr_width(addr_width))
4284 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4285 40 unneback 
`undef MODULE
4286 6 unneback 
 
4287 
endmodule
4288 40 unneback 
`endif
4289 6 unneback 
 
4290 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4291 
`define MODULE fifo_2r2w_async
4292 
module `BASE`MODULE (
4293 
`undef MODULE
4294 6 unneback 
    // a side
4295 
    a_d, a_wr, a_fifo_full,
4296 
    a_q, a_rd, a_fifo_empty,
4297 
    a_clk, a_rst,
4298 
    // b side
4299 
    b_d, b_wr, b_fifo_full,
4300 
    b_q, b_rd, b_fifo_empty,
4301 
    b_clk, b_rst
4302 
    );
4303 
 
4304 
parameter data_width = 18;
4305 
parameter addr_width = 4;
4306 
 
4307 
// a side
4308 
input  [data_width-1:0] a_d;
4309 
input                   a_wr;
4310 
output                  a_fifo_full;
4311 
output [data_width-1:0] a_q;
4312 
input                   a_rd;
4313 
output                  a_fifo_empty;
4314 
input                   a_clk;
4315 
input                   a_rst;
4316 
 
4317 
// b side
4318 
input  [data_width-1:0] b_d;
4319 
input                   b_wr;
4320 
output                  b_fifo_full;
4321 
output [data_width-1:0] b_q;
4322 
input                   b_rd;
4323 
output                  b_fifo_empty;
4324 
input                   b_clk;
4325 
input                   b_rst;
4326 
 
4327 40 unneback 
`define MODULE fifo_1r1w_async
4328 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4329 6 unneback 
vl_fifo_1r1w_async_a (
4330 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4331 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4332 
    );
4333 
 
4334 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4335 6 unneback 
vl_fifo_1r1w_async_b (
4336 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4337 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4338 
    );
4339 40 unneback 
`undef MODULE
4340 
 
4341 6 unneback 
endmodule
4342 40 unneback 
`endif
4343 6 unneback 
 
4344 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4345 
`define MODULE fifo_2r2w_async_simplex
4346 
module `BASE`MODULE (
4347 
`undef MODULE
4348 6 unneback 
    // a side
4349 
    a_d, a_wr, a_fifo_full,
4350 
    a_q, a_rd, a_fifo_empty,
4351 
    a_clk, a_rst,
4352 
    // b side
4353 
    b_d, b_wr, b_fifo_full,
4354 
    b_q, b_rd, b_fifo_empty,
4355 
    b_clk, b_rst
4356 
    );
4357 
 
4358 
parameter data_width = 18;
4359 
parameter addr_width = 4;
4360 
 
4361 
// a side
4362 
input  [data_width-1:0] a_d;
4363 
input                   a_wr;
4364 
output                  a_fifo_full;
4365 
output [data_width-1:0] a_q;
4366 
input                   a_rd;
4367 
output                  a_fifo_empty;
4368 
input                   a_clk;
4369 
input                   a_rst;
4370 
 
4371 
// b side
4372 
input  [data_width-1:0] b_d;
4373 
input                   b_wr;
4374 
output                  b_fifo_full;
4375 
output [data_width-1:0] b_q;
4376 
input                   b_rd;
4377 
output                  b_fifo_empty;
4378 
input                   b_clk;
4379 
input                   b_rst;
4380 
 
4381 
// adr_gen
4382 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4383 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4384 
// dpram
4385 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4386 
 
4387 40 unneback 
`define MODULE cnt_gray_ce_bin
4388 
`BASE`MODULE
4389 6 unneback 
    # ( .length(addr_width))
4390 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4391 
 
4392 40 unneback 
`BASE`MODULE
4393 6 unneback 
    # (.length(addr_width))
4394 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4395 
 
4396 40 unneback 
`BASE`MODULE
4397 6 unneback 
    # ( .length(addr_width))
4398 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4399 
 
4400 40 unneback 
`BASE`MODULE
4401 6 unneback 
    # (.length(addr_width))
4402 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4403 40 unneback 
`undef MODULE
4404 6 unneback 
 
4405 
// mux read or write adr to DPRAM
4406 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4407 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4408 
 
4409 40 unneback 
`define MODULE dpram_2r2w
4410 
`BASE`MODULE
4411 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4412 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4413 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4414 40 unneback 
`undef MODULE
4415 6 unneback 
 
4416 40 unneback 
`define MODULE fifo_cmp_async
4417 
`BASE`MODULE
4418 6 unneback 
    # (.addr_width(addr_width))
4419 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4420 
 
4421 40 unneback 
`BASE`MODULE
4422 6 unneback 
    # (.addr_width(addr_width))
4423 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4424 40 unneback 
`undef MODULE
4425 6 unneback 
 
4426 
endmodule
4427 40 unneback 
`endif
4428 48 unneback 
 
4429 
`ifdef REG_FILE
4430 
`define MODULE reg_file
4431 
module `BASE`MODULE (
4432 
`undef MODULE
4433 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4434 
);
4435 
parameter data_width = 32;
4436 
parameter addr_width = 5;
4437 
input [addr_width-1:0] a1, a2, a3;
4438 
input [data_width-1:0] wd3;
4439 
input we3;
4440 
output [data_width-1:0] rd1, rd2;
4441 
input clk;
4442 
 
4443 
`ifdef ACTEL
4444 
reg [data_width-1:0] wd3_reg;
4445 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4446 
reg we3_reg;
4447 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4448 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4449 
always @ (posedge clk or posedge rst)
4450 
if (rst)
4451 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4452 
else
4453 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4454 
 
4455 
    always @ (negedge clk)
4456 
    if (we3_reg)
4457 
        ram1[a3_reg] <= wd3;
4458 
    always @ (posedge clk)
4459 
        a1_reg <= a1;
4460 
    assign rd1 = ram1[a1_reg];
4461 
 
4462 
    always @ (negedge clk)
4463 
    if (we3_reg)
4464 
        ram2[a3_reg] <= wd3;
4465 
    always @ (posedge clk)
4466 
        a2_reg <= a2;
4467 
    assign rd2 = ram2[a2_reg];
4468 
 
4469 
`else
4470 
 
4471 
`define MODULE dpram_1r1w
4472 
`BASE`MODULE
4473 
    # ( .data_width(data_width), .addr_width(addr_width))
4474 
    ram1 (
4475 
        .d_a(wd3),
4476 
        .adr_a(a3),
4477 
        .we_a(we3),
4478 
        .clk_a(clk),
4479 
        .q_b(rd1),
4480 
        .adr_b(a1),
4481 
        .clk_b(clk) );
4482 
 
4483 
`BASE`MODULE
4484 
    # ( .data_width(data_width), .addr_width(addr_width))
4485 
    ram2 (
4486 
        .d_a(wd3),
4487 
        .adr_a(a3),
4488 
        .we_a(we3),
4489 
        .clk_a(clk),
4490 
        .q_b(rd2),
4491 
        .adr_b(a2),
4492 
        .clk_b(clk) );
4493 
`undef MODULE
4494 
 
4495 
`endif
4496 
 
4497 
endmodule
4498 
`endif
4499 12 unneback 
//////////////////////////////////////////////////////////////////////
4500 
////                                                              ////
4501 
////  Versatile library, wishbone stuff                           ////
4502 
////                                                              ////
4503 
////  Description                                                 ////
4504 
////  Wishbone compliant modules                                  ////
4505 
////                                                              ////
4506 
////                                                              ////
4507 
////  To Do:                                                      ////
4508 
////   -                                                          ////
4509 
////                                                              ////
4510 
////  Author(s):                                                  ////
4511 
////      - Michael Unneback, unneback@opencores.org              ////
4512 
////        ORSoC AB                                              ////
4513 
////                                                              ////
4514 
//////////////////////////////////////////////////////////////////////
4515 
////                                                              ////
4516 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4517 
////                                                              ////
4518 
//// This source file may be used and distributed without         ////
4519 
//// restriction provided that this copyright statement is not    ////
4520 
//// removed from the file and that any derivative work contains  ////
4521 
//// the original copyright notice and the associated disclaimer. ////
4522 
////                                                              ////
4523 
//// This source file is free software; you can redistribute it   ////
4524 
//// and/or modify it under the terms of the GNU Lesser General   ////
4525 
//// Public License as published by the Free Software Foundation; ////
4526 
//// either version 2.1 of the License, or (at your option) any   ////
4527 
//// later version.                                               ////
4528 
////                                                              ////
4529 
//// This source is distributed in the hope that it will be       ////
4530 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4531 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4532 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4533 
//// details.                                                     ////
4534 
////                                                              ////
4535 
//// You should have received a copy of the GNU Lesser General    ////
4536 
//// Public License along with this source; if not, download it   ////
4537 
//// from http://www.opencores.org/lgpl.shtml                     ////
4538 
////                                                              ////
4539 
//////////////////////////////////////////////////////////////////////
4540 
 
4541 75 unneback 
`ifdef WB_ADR_INC
4542 
// async wb3 - wb3 bridge
4543 
`timescale 1ns/1ns
4544 
`define MODULE wb_adr_inc
4545 85 unneback 
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4546 75 unneback 
`undef MODULE
4547 83 unneback 
parameter adr_width = 10;
4548 
parameter max_burst_width = 4;
4549 85 unneback 
input cyc_i, stb_i, we_i;
4550 83 unneback 
input [2:0] cti_i;
4551 
input [1:0] bte_i;
4552 
input [adr_width-1:0] adr_i;
4553 
output [adr_width-1:0] adr_o;
4554 
output ack_o;
4555 
input clk, rst;
4556 75 unneback 
 
4557 83 unneback 
reg [adr_width-1:0] adr;
4558 90 unneback 
wire [max_burst_width-1:0] to_adr;
4559 91 unneback 
reg [max_burst_width-1:0] last_adr;
4560 
reg [1:0] last_cycle;
4561 
localparam idle = 2'b00;
4562 
localparam cyc  = 2'b01;
4563 
localparam ws   = 2'b10;
4564 
localparam eoc  = 2'b11;
4565 90 unneback 
 
4566 91 unneback 
always @ (posedge clk or posedge rst)
4567 
if (rst)
4568 
    last_adr <= {max_burst_width{1'b0}};
4569 
else
4570 
    if (stb_i)
4571 
        last_adr <=adr_o;
4572 
 
4573 83 unneback 
generate
4574 
if (max_burst_width==0) begin : inst_0
4575 
    reg ack_o;
4576 
    assign adr_o = adr_i;
4577 75 unneback 
    always @ (posedge clk or posedge rst)
4578 83 unneback 
    if (rst)
4579 
        ack_o <= 1'b0;
4580 
    else
4581 
        ack_o <= cyc_i & stb_i & !ack_o;
4582 
end else begin
4583 
 
4584 
    always @ (posedge clk or posedge rst)
4585 
    if (rst)
4586 
        last_cycle <= idle;
4587 
    else
4588 
        last_cycle <= (!cyc_i) ? idle :
4589 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
4590 
                      (cyc_i & !stb_i) ? ws :
4591 
                      cyc;
4592 
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
4593 85 unneback 
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
4594 91 unneback 
                                        (!stb_i) ? last_adr :
4595 85 unneback 
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
4596 
                                        adr[max_burst_width-1:0];
4597 90 unneback 
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
4598 83 unneback 
end
4599 
endgenerate
4600 
 
4601 
generate
4602 
if (max_burst_width==2) begin : inst_2
4603 
    always @ (posedge clk or posedge rst)
4604 
    if (rst)
4605 
        adr <= 2'h0;
4606 
    else
4607 
        if (cyc_i & stb_i)
4608 
            adr[1:0] <= to_adr[1:0] + 2'd1;
4609 75 unneback 
        else
4610 83 unneback 
            adr <= to_adr[1:0];
4611 
end
4612 
endgenerate
4613 
 
4614 
generate
4615 
if (max_burst_width==3) begin : inst_3
4616 
    always @ (posedge clk or posedge rst)
4617 
    if (rst)
4618 
        adr <= 3'h0;
4619 
    else
4620 
        if (cyc_i & stb_i)
4621 
            case (bte_i)
4622 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
4623 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
4624 75 unneback 
            endcase
4625 83 unneback 
        else
4626 
            adr <= to_adr[2:0];
4627 
end
4628 
endgenerate
4629 
 
4630 
generate
4631 
if (max_burst_width==4) begin : inst_4
4632 
    always @ (posedge clk or posedge rst)
4633 
    if (rst)
4634 
        adr <= 4'h0;
4635 
    else
4636 91 unneback 
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
4637 83 unneback 
            case (bte_i)
4638 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
4639 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
4640 
            default: adr[3:0] <= to_adr + 4'd1;
4641 
            endcase
4642 
        else
4643 
            adr <= to_adr[3:0];
4644 
end
4645 
endgenerate
4646 
 
4647 
generate
4648 
if (adr_width > max_burst_width) begin : pass_through
4649 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
4650 
end
4651 
endgenerate
4652 
 
4653 
endmodule
4654 75 unneback 
`endif
4655 
 
4656 40 unneback 
`ifdef WB3WB3_BRIDGE
4657 12 unneback 
// async wb3 - wb3 bridge
4658 
`timescale 1ns/1ns
4659 40 unneback 
`define MODULE wb3wb3_bridge
4660 
module `BASE`MODULE (
4661 
`undef MODULE
4662 12 unneback 
        // wishbone slave side
4663 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4664 
        // wishbone master side
4665 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4666 
 
4667 
input [31:0] wbs_dat_i;
4668 
input [31:2] wbs_adr_i;
4669 
input [3:0]  wbs_sel_i;
4670 
input [1:0]  wbs_bte_i;
4671 
input [2:0]  wbs_cti_i;
4672 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4673 
output [31:0] wbs_dat_o;
4674 14 unneback 
output wbs_ack_o;
4675 12 unneback 
input wbs_clk, wbs_rst;
4676 
 
4677 
output [31:0] wbm_dat_o;
4678 
output reg [31:2] wbm_adr_o;
4679 
output [3:0]  wbm_sel_o;
4680 
output reg [1:0]  wbm_bte_o;
4681 
output reg [2:0]  wbm_cti_o;
4682 14 unneback 
output reg wbm_we_o;
4683 
output wbm_cyc_o;
4684 12 unneback 
output wbm_stb_o;
4685 
input [31:0]  wbm_dat_i;
4686 
input wbm_ack_i;
4687 
input wbm_clk, wbm_rst;
4688 
 
4689 
parameter addr_width = 4;
4690 
 
4691 
// bte
4692 
parameter linear       = 2'b00;
4693 
parameter wrap4        = 2'b01;
4694 
parameter wrap8        = 2'b10;
4695 
parameter wrap16       = 2'b11;
4696 
// cti
4697 
parameter classic      = 3'b000;
4698 
parameter incburst     = 3'b010;
4699 
parameter endofburst   = 3'b111;
4700 
 
4701 
parameter wbs_adr  = 1'b0;
4702 
parameter wbs_data = 1'b1;
4703 
 
4704 33 unneback 
parameter wbm_adr0      = 2'b00;
4705 
parameter wbm_adr1      = 2'b01;
4706 
parameter wbm_data      = 2'b10;
4707 
parameter wbm_data_wait = 2'b11;
4708 12 unneback 
 
4709 
reg [1:0] wbs_bte_reg;
4710 
reg wbs;
4711 
wire wbs_eoc_alert, wbm_eoc_alert;
4712 
reg wbs_eoc, wbm_eoc;
4713 
reg [1:0] wbm;
4714 
 
4715 14 unneback 
wire [1:16] wbs_count, wbm_count;
4716 12 unneback 
 
4717 
wire [35:0] a_d, a_q, b_d, b_q;
4718 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4719 
reg a_rd_reg;
4720 
wire b_rd_adr, b_rd_data;
4721 14 unneback 
wire b_rd_data_reg;
4722 
wire [35:0] temp;
4723 12 unneback 
 
4724 
`define WE 5
4725 
`define BTE 4:3
4726 
`define CTI 2:0
4727 
 
4728 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4729 
always @ (posedge wbs_clk or posedge wbs_rst)
4730 
if (wbs_rst)
4731 
        wbs_eoc <= 1'b0;
4732 
else
4733 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4734 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
4735 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4736 
                wbs_eoc <= 1'b1;
4737 
 
4738 40 unneback 
`define MODULE cnt_shreg_ce_clear
4739 
`BASE`MODULE # ( .length(16))
4740 
`undef MODULE
4741 12 unneback 
    cnt0 (
4742 
        .cke(wbs_ack_o),
4743 
        .clear(wbs_eoc),
4744 
        .q(wbs_count),
4745 
        .rst(wbs_rst),
4746 
        .clk(wbs_clk));
4747 
 
4748 
always @ (posedge wbs_clk or posedge wbs_rst)
4749 
if (wbs_rst)
4750 
        wbs <= wbs_adr;
4751 
else
4752 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
4753 12 unneback 
                wbs <= wbs_data;
4754 
        else if (wbs_eoc & wbs_ack_o)
4755 
                wbs <= wbs_adr;
4756 
 
4757 
// wbs FIFO
4758 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
4759 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
4760 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4761 
              1'b0;
4762 
assign a_rd = !a_fifo_empty;
4763 
always @ (posedge wbs_clk or posedge wbs_rst)
4764 
if (wbs_rst)
4765 
        a_rd_reg <= 1'b0;
4766 
else
4767 
        a_rd_reg <= a_rd;
4768 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4769 
 
4770 
assign wbs_dat_o = a_q[35:4];
4771 
 
4772 
always @ (posedge wbs_clk or posedge wbs_rst)
4773 
if (wbs_rst)
4774 13 unneback 
        wbs_bte_reg <= 2'b00;
4775 12 unneback 
else
4776 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4777 12 unneback 
 
4778 
// wbm FIFO
4779 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4780 
always @ (posedge wbm_clk or posedge wbm_rst)
4781 
if (wbm_rst)
4782 
        wbm_eoc <= 1'b0;
4783 
else
4784 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4785 
                wbm_eoc <= b_q[`BTE] == linear;
4786 
        else if (wbm_eoc_alert & wbm_ack_i)
4787 
                wbm_eoc <= 1'b1;
4788 
 
4789 
always @ (posedge wbm_clk or posedge wbm_rst)
4790 
if (wbm_rst)
4791 
        wbm <= wbm_adr0;
4792 
else
4793 33 unneback 
/*
4794 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4795 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4796 
        (wbm==wbm_adr1 & !wbm_we_o) |
4797 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4798 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4799 33 unneback 
*/
4800 
    case (wbm)
4801 
    wbm_adr0:
4802 
        if (!b_fifo_empty)
4803 
            wbm <= wbm_adr1;
4804 
    wbm_adr1:
4805 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4806 
            wbm <= wbm_data;
4807 
    wbm_data:
4808 
        if (wbm_ack_i & wbm_eoc)
4809 
            wbm <= wbm_adr0;
4810 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4811 
            wbm <= wbm_data_wait;
4812 
    wbm_data_wait:
4813 
        if (!b_fifo_empty)
4814 
            wbm <= wbm_data;
4815 
    endcase
4816 12 unneback 
 
4817 
assign b_d = {wbm_dat_i,4'b1111};
4818 
assign b_wr = !wbm_we_o & wbm_ack_i;
4819 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4820 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4821 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4822 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4823 12 unneback 
                   1'b0;
4824 
assign b_rd = b_rd_adr | b_rd_data;
4825 
 
4826 40 unneback 
`define MODULE dff
4827 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4828 
`undef MODULE
4829 
`define MODULE dff_ce
4830 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4831 
`undef MODULE
4832 12 unneback 
 
4833 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4834 
 
4835 40 unneback 
`define MODULE cnt_shreg_ce_clear
4836 42 unneback 
`BASE`MODULE # ( .length(16))
4837 40 unneback 
`undef MODULE
4838 12 unneback 
    cnt1 (
4839 
        .cke(wbm_ack_i),
4840 
        .clear(wbm_eoc),
4841 
        .q(wbm_count),
4842 
        .rst(wbm_rst),
4843 
        .clk(wbm_clk));
4844 
 
4845 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4846 
assign wbm_stb_o = (wbm==wbm_data);
4847 12 unneback 
 
4848 
always @ (posedge wbm_clk or posedge wbm_rst)
4849 
if (wbm_rst)
4850 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4851 
else begin
4852 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4853 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4854 
        else if (wbm_eoc_alert & wbm_ack_i)
4855 
                wbm_cti_o <= endofburst;
4856 
end
4857 
 
4858 
//async_fifo_dw_simplex_top
4859 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4860 
`BASE`MODULE
4861 
`undef MODULE
4862 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4863 
fifo (
4864 
    // a side
4865 
    .a_d(a_d),
4866 
    .a_wr(a_wr),
4867 
    .a_fifo_full(a_fifo_full),
4868 
    .a_q(a_q),
4869 
    .a_rd(a_rd),
4870 
    .a_fifo_empty(a_fifo_empty),
4871 
    .a_clk(wbs_clk),
4872 
    .a_rst(wbs_rst),
4873 
    // b side
4874 
    .b_d(b_d),
4875 
    .b_wr(b_wr),
4876 
    .b_fifo_full(b_fifo_full),
4877 
    .b_q(b_q),
4878 
    .b_rd(b_rd),
4879 
    .b_fifo_empty(b_fifo_empty),
4880 
    .b_clk(wbm_clk),
4881 
    .b_rst(wbm_rst)
4882 
    );
4883 
 
4884 
endmodule
4885 40 unneback 
`undef WE
4886 
`undef BTE
4887 
`undef CTI
4888 
`endif
4889 17 unneback 
 
4890 75 unneback 
`ifdef WB3AVALON_BRIDGE
4891 
`define MODULE wb3avalon_bridge
4892 
module `BASE`MODULE (
4893 
`undef MODULE
4894 
        // wishbone slave side
4895 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4896 77 unneback 
        // avalon master side
4897 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
4898 
 
4899 85 unneback 
parameter linewrapburst = 1'b0;
4900 
 
4901 75 unneback 
input [31:0] wbs_dat_i;
4902 
input [31:2] wbs_adr_i;
4903 
input [3:0]  wbs_sel_i;
4904 
input [1:0]  wbs_bte_i;
4905 
input [2:0]  wbs_cti_i;
4906 83 unneback 
input wbs_we_i;
4907 
input wbs_cyc_i;
4908 
input wbs_stb_i;
4909 75 unneback 
output [31:0] wbs_dat_o;
4910 
output wbs_ack_o;
4911 
input wbs_clk, wbs_rst;
4912 
 
4913 
input [31:0] readdata;
4914 
output [31:0] writedata;
4915 
output [31:2] address;
4916 
output [3:0]  be;
4917 
output write;
4918 81 unneback 
output read;
4919 75 unneback 
output beginbursttransfer;
4920 
output [3:0] burstcount;
4921 
input readdatavalid;
4922 
input waitrequest;
4923 
input clk;
4924 
input rst;
4925 
 
4926 
wire [1:0] wbm_bte_o;
4927 
wire [2:0] wbm_cti_o;
4928 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
4929 
reg last_cyc;
4930 79 unneback 
reg [3:0] counter;
4931 82 unneback 
reg read_busy;
4932 75 unneback 
 
4933 
always @ (posedge clk or posedge rst)
4934 
if (rst)
4935 
    last_cyc <= 1'b0;
4936 
else
4937 
    last_cyc <= wbm_cyc_o;
4938 
 
4939 79 unneback 
always @ (posedge clk or posedge rst)
4940 
if (rst)
4941 82 unneback 
    read_busy <= 1'b0;
4942 79 unneback 
else
4943 82 unneback 
    if (read & !waitrequest)
4944 
        read_busy <= 1'b1;
4945 
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
4946 
        read_busy <= 1'b0;
4947 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
4948 81 unneback 
 
4949 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
4950 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
4951 
                    (wbm_bte_o==2'b10) ? 4'd8 :
4952 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
4953 
                    4'd1;
4954 82 unneback 
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
4955 75 unneback 
 
4956 79 unneback 
always @ (posedge clk or posedge rst)
4957 
if (rst) begin
4958 
    counter <= 4'd0;
4959 
end else
4960 80 unneback 
    if (wbm_we_o) begin
4961 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
4962 85 unneback 
            counter <= burstcount -4'd1;
4963 80 unneback 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
4964 
            counter <= burstcount;
4965 
        end else if (!waitrequest & wbm_stb_o) begin
4966 
            counter <= counter - 4'd1;
4967 
        end
4968 82 unneback 
    end
4969 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
4970 79 unneback 
 
4971 75 unneback 
`define MODULE wb3wb3_bridge
4972 77 unneback 
`BASE`MODULE wbwb3inst (
4973 75 unneback 
`undef MODULE
4974 
    // wishbone slave side
4975 
    .wbs_dat_i(wbs_dat_i),
4976 
    .wbs_adr_i(wbs_adr_i),
4977 
    .wbs_sel_i(wbs_sel_i),
4978 
    .wbs_bte_i(wbs_bte_i),
4979 
    .wbs_cti_i(wbs_cti_i),
4980 
    .wbs_we_i(wbs_we_i),
4981 
    .wbs_cyc_i(wbs_cyc_i),
4982 
    .wbs_stb_i(wbs_stb_i),
4983 
    .wbs_dat_o(wbs_dat_o),
4984 
    .wbs_ack_o(wbs_ack_o),
4985 
    .wbs_clk(wbs_clk),
4986 
    .wbs_rst(wbs_rst),
4987 
    // wishbone master side
4988 
    .wbm_dat_o(writedata),
4989 78 unneback 
    .wbm_adr_o(address),
4990 75 unneback 
    .wbm_sel_o(be),
4991 
    .wbm_bte_o(wbm_bte_o),
4992 
    .wbm_cti_o(wbm_cti_o),
4993 
    .wbm_we_o(wbm_we_o),
4994 
    .wbm_cyc_o(wbm_cyc_o),
4995 
    .wbm_stb_o(wbm_stb_o),
4996 
    .wbm_dat_i(readdata),
4997 
    .wbm_ack_i(wbm_ack_i),
4998 
    .wbm_clk(clk),
4999 
    .wbm_rst(rst));
5000 
 
5001 
 
5002 
endmodule
5003 
`endif
5004 
 
5005 40 unneback 
`ifdef WB3_ARBITER_TYPE1
5006 
`define MODULE wb3_arbiter_type1
5007 42 unneback 
module `BASE`MODULE (
5008 40 unneback 
`undef MODULE
5009 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5010 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5011 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5012 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5013 
    wb_clk, wb_rst
5014 
);
5015 
 
5016 
parameter nr_of_ports = 3;
5017 
parameter adr_size = 26;
5018 
parameter adr_lo   = 2;
5019 
parameter dat_size = 32;
5020 
parameter sel_size = dat_size/8;
5021 
 
5022 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5023 
localparam dw = dat_size * nr_of_ports;
5024 
localparam sw = sel_size * nr_of_ports;
5025 
localparam cw = 3 * nr_of_ports;
5026 
localparam bw = 2 * nr_of_ports;
5027 
 
5028 
input  [dw-1:0] wbm_dat_o;
5029 
input  [aw-1:0] wbm_adr_o;
5030 
input  [sw-1:0] wbm_sel_o;
5031 
input  [cw-1:0] wbm_cti_o;
5032 
input  [bw-1:0] wbm_bte_o;
5033 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5034 
output [dw-1:0] wbm_dat_i;
5035 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5036 
 
5037 
output [dat_size-1:0] wbs_dat_i;
5038 
output [adr_size-1:adr_lo] wbs_adr_i;
5039 
output [sel_size-1:0] wbs_sel_i;
5040 
output [2:0] wbs_cti_i;
5041 
output [1:0] wbs_bte_i;
5042 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5043 
input  [dat_size-1:0] wbs_dat_o;
5044 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5045 
 
5046 
input wb_clk, wb_rst;
5047 
 
5048 44 unneback 
reg  [nr_of_ports-1:0] select;
5049 39 unneback 
wire [nr_of_ports-1:0] state;
5050 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5051 
wire [nr_of_ports-1:0] sel;
5052 
wire idle;
5053 
 
5054 
genvar i;
5055 
 
5056 
assign idle = !(|state);
5057 
 
5058 
generate
5059 
if (nr_of_ports == 2) begin
5060 
 
5061 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5062 
 
5063 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5064 
 
5065 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5066 
 
5067 
    always @ (idle or wbm_cyc_o)
5068 
    if (idle)
5069 
        casex (wbm_cyc_o)
5070 
        2'b1x : select = 2'b10;
5071 
        2'b01 : select = 2'b01;
5072 
        default : select = {nr_of_ports{1'b0}};
5073 
        endcase
5074 
    else
5075 
        select = {nr_of_ports{1'b0}};
5076 
 
5077 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5078 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5079 
 
5080 
end
5081 
endgenerate
5082 
 
5083 
generate
5084 
if (nr_of_ports == 3) begin
5085 
 
5086 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5087 
 
5088 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5089 
 
5090 44 unneback 
    always @ (idle or wbm_cyc_o)
5091 
    if (idle)
5092 
        casex (wbm_cyc_o)
5093 
        3'b1xx : select = 3'b100;
5094 
        3'b01x : select = 3'b010;
5095 
        3'b001 : select = 3'b001;
5096 
        default : select = {nr_of_ports{1'b0}};
5097 
        endcase
5098 
    else
5099 
        select = {nr_of_ports{1'b0}};
5100 
 
5101 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5102 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5103 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5104 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5105 
 
5106 
end
5107 
endgenerate
5108 
 
5109 
generate
5110 44 unneback 
if (nr_of_ports == 4) begin
5111 
 
5112 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5113 
 
5114 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5115 
 
5116 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5117 
 
5118 
    always @ (idle or wbm_cyc_o)
5119 
    if (idle)
5120 
        casex (wbm_cyc_o)
5121 
        4'b1xxx : select = 4'b1000;
5122 
        4'b01xx : select = 4'b0100;
5123 
        4'b001x : select = 4'b0010;
5124 
        4'b0001 : select = 4'b0001;
5125 
        default : select = {nr_of_ports{1'b0}};
5126 
        endcase
5127 
    else
5128 
        select = {nr_of_ports{1'b0}};
5129 
 
5130 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5131 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5132 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5133 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5134 
 
5135 
end
5136 
endgenerate
5137 
 
5138 
generate
5139 
if (nr_of_ports == 5) begin
5140 
 
5141 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5142 
 
5143 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5144 
 
5145 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5146 
 
5147 
    always @ (idle or wbm_cyc_o)
5148 
    if (idle)
5149 
        casex (wbm_cyc_o)
5150 
        5'b1xxxx : select = 5'b10000;
5151 
        5'b01xxx : select = 5'b01000;
5152 
        5'b001xx : select = 5'b00100;
5153 
        5'b0001x : select = 5'b00010;
5154 
        5'b00001 : select = 5'b00001;
5155 
        default : select = {nr_of_ports{1'b0}};
5156 
        endcase
5157 
    else
5158 
        select = {nr_of_ports{1'b0}};
5159 
 
5160 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5161 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5162 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5163 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5164 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5165 
 
5166 
end
5167 
endgenerate
5168 
 
5169 
generate
5170 67 unneback 
if (nr_of_ports == 6) begin
5171 
 
5172 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5173 
 
5174 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5175 
 
5176 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5177 
 
5178 
    always @ (idle or wbm_cyc_o)
5179 
    if (idle)
5180 
        casex (wbm_cyc_o)
5181 
        6'b1xxxxx : select = 6'b100000;
5182 
        6'b01xxxx : select = 6'b010000;
5183 
        6'b001xxx : select = 6'b001000;
5184 
        6'b0001xx : select = 6'b000100;
5185 
        6'b00001x : select = 6'b000010;
5186 
        6'b000001 : select = 6'b000001;
5187 
        default : select = {nr_of_ports{1'b0}};
5188 
        endcase
5189 
    else
5190 
        select = {nr_of_ports{1'b0}};
5191 
 
5192 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5193 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5194 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5195 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5196 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5197 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5198 
 
5199 
end
5200 
endgenerate
5201 
 
5202 
generate
5203 
if (nr_of_ports == 7) begin
5204 
 
5205 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5206 
 
5207 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5208 
 
5209 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5210 
 
5211 
    always @ (idle or wbm_cyc_o)
5212 
    if (idle)
5213 
        casex (wbm_cyc_o)
5214 
        7'b1xxxxxx : select = 7'b1000000;
5215 
        7'b01xxxxx : select = 7'b0100000;
5216 
        7'b001xxxx : select = 7'b0010000;
5217 
        7'b0001xxx : select = 7'b0001000;
5218 
        7'b00001xx : select = 7'b0000100;
5219 
        7'b000001x : select = 7'b0000010;
5220 
        7'b0000001 : select = 7'b0000001;
5221 
        default : select = {nr_of_ports{1'b0}};
5222 
        endcase
5223 
    else
5224 
        select = {nr_of_ports{1'b0}};
5225 
 
5226 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5227 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5228 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5229 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5230 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5231 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5232 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5233 
 
5234 
end
5235 
endgenerate
5236 
 
5237 
generate
5238 
if (nr_of_ports == 8) begin
5239 
 
5240 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5241 
 
5242 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5243 
 
5244 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5245 
 
5246 
    always @ (idle or wbm_cyc_o)
5247 
    if (idle)
5248 
        casex (wbm_cyc_o)
5249 
        8'b1xxxxxxx : select = 8'b10000000;
5250 
        8'b01xxxxxx : select = 8'b01000000;
5251 
        8'b001xxxxx : select = 8'b00100000;
5252 
        8'b0001xxxx : select = 8'b00010000;
5253 
        8'b00001xxx : select = 8'b00001000;
5254 
        8'b000001xx : select = 8'b00000100;
5255 
        8'b0000001x : select = 8'b00000010;
5256 
        8'b00000001 : select = 8'b00000001;
5257 
        default : select = {nr_of_ports{1'b0}};
5258 
        endcase
5259 
    else
5260 
        select = {nr_of_ports{1'b0}};
5261 
 
5262 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5263 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5264 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5265 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5266 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5267 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5268 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5269 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5270 
 
5271 
end
5272 
endgenerate
5273 
 
5274 
generate
5275 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5276 42 unneback 
`define MODULE spr
5277 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5278 
`undef MODULE
5279 39 unneback 
end
5280 
endgenerate
5281 
 
5282 
    assign sel = select | state;
5283 
 
5284 40 unneback 
`define MODULE mux_andor
5285 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5286 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5287 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5288 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5289 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5290 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5291 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5292 
`undef MODULE
5293 39 unneback 
    assign wbs_cyc_i = |sel;
5294 
 
5295 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5296 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5297 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5298 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5299 
 
5300 
endmodule
5301 40 unneback 
`endif
5302 39 unneback 
 
5303 60 unneback 
`ifdef WB_B3_RAM_BE
5304 49 unneback 
// WB RAM with byte enable
5305 59 unneback 
`define MODULE wb_b3_ram_be
5306 
module `BASE`MODULE (
5307 
`undef MODULE
5308 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5309 
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
5310 59 unneback 
 
5311 68 unneback 
parameter adr_size = 16;
5312 85 unneback 
parameter mem_size = 1<<adr_size;
5313 60 unneback 
parameter dat_size = 32;
5314 83 unneback 
parameter max_burst_width = 4;
5315 60 unneback 
parameter memory_init = 1;
5316 
parameter memory_file = "vl_ram.vmem";
5317 59 unneback 
 
5318 85 unneback 
localparam aw = (adr_size);
5319 69 unneback 
localparam dw = dat_size;
5320 
localparam sw = dat_size/8;
5321 
localparam cw = 3;
5322 
localparam bw = 2;
5323 60 unneback 
 
5324 70 unneback 
input [dw-1:0] wbs_dat_i;
5325 
input [aw-1:0] wbs_adr_i;
5326 
input [cw-1:0] wbs_cti_i;
5327 
input [bw-1:0] wbs_bte_i;
5328 
input [sw-1:0] wbs_sel_i;
5329 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5330 
output [dw-1:0] wbs_dat_o;
5331 
output wbs_ack_o;
5332 71 unneback 
input wb_clk, wb_rst;
5333 59 unneback 
 
5334 83 unneback 
wire [aw-1:0] adr;
5335 59 unneback 
 
5336 60 unneback 
`define MODULE ram_be
5337 
`BASE`MODULE # (
5338 
    .data_width(dat_size),
5339 83 unneback 
    .addr_width(aw),
5340 69 unneback 
    .mem_size(mem_size),
5341 68 unneback 
    .memory_init(memory_init),
5342 
    .memory_file(memory_file))
5343 60 unneback 
ram0(
5344 
`undef MODULE
5345 
    .d(wbs_dat_i),
5346 83 unneback 
    .adr(adr),
5347 60 unneback 
    .be(wbs_sel_i),
5348 86 unneback 
    .we(wbs_we_i & wbs_ack_o),
5349 60 unneback 
    .q(wbs_dat_o),
5350 
    .clk(wb_clk)
5351 
);
5352 
 
5353 83 unneback 
`define MODULE wb_adr_inc
5354 
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
5355 
    .cyc_i(wbs_cyc_i),
5356 
    .stb_i(wbs_stb_i),
5357 
    .cti_i(wbs_cti_i),
5358 
    .bte_i(wbs_bte_i),
5359 
    .adr_i(wbs_adr_i),
5360 85 unneback 
    .we_i(wbs_we_i),
5361 83 unneback 
    .ack_o(wbs_ack_o),
5362 
    .adr_o(adr),
5363 
    .clk(wb_clk),
5364 
    .rst(wb_rst));
5365 
`undef MODULE
5366 60 unneback 
 
5367 59 unneback 
endmodule
5368 
`endif
5369 
 
5370 
`ifdef WB_B4_RAM_BE
5371 
// WB RAM with byte enable
5372 49 unneback 
`define MODULE wb_b4_ram_be
5373 
module `BASE`MODULE (
5374 
`undef MODULE
5375 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
5376 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
5377 49 unneback 
 
5378 
    parameter dat_width = 32;
5379 
    parameter adr_width = 8;
5380 
 
5381 
input [dat_width-1:0] wb_dat_i;
5382 
input [adr_width-1:0] wb_adr_i;
5383 
input [dat_width/8-1:0] wb_sel_i;
5384 
input wb_we_i, wb_stb_i, wb_cyc_i;
5385 
output [dat_width-1:0] wb_dat_o;
5386 51 unneback 
reg [dat_width-1:0] wb_dat_o;
5387 52 unneback 
output wb_stall_o;
5388 49 unneback 
output wb_ack_o;
5389 
reg wb_ack_o;
5390 
input wb_clk, wb_rst;
5391 
 
5392 56 unneback 
wire [dat_width/8-1:0] cke;
5393 
 
5394 49 unneback 
generate
5395 
if (dat_width==32) begin
5396 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
5397 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
5398 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
5399 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
5400 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
5401 49 unneback 
    always @ (posedge wb_clk)
5402 
    begin
5403 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
5404 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
5405 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
5406 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
5407 49 unneback 
    end
5408 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
5409 
    begin
5410 
        if (wb_rst)
5411 
            wb_dat_o <= 32'h0;
5412 
        else
5413 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
5414 
    end
5415 49 unneback 
end
5416 
endgenerate
5417 
 
5418 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5419 55 unneback 
if (wb_rst)
5420 52 unneback 
    wb_ack_o <= 1'b0;
5421 
else
5422 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
5423 52 unneback 
 
5424 
assign wb_stall_o = 1'b0;
5425 
 
5426 49 unneback 
endmodule
5427 
`endif
5428 
 
5429 48 unneback 
`ifdef WB_B4_ROM
5430 
// WB ROM
5431 
`define MODULE wb_b4_rom
5432 
module `BASE`MODULE (
5433 
`undef MODULE
5434 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5435 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5436 
 
5437 
    parameter dat_width = 32;
5438 
    parameter dat_default = 32'h15000000;
5439 
    parameter adr_width = 32;
5440 
 
5441 
/*
5442 
`ifndef ROM
5443 
`define ROM "rom.v"
5444 
`endif
5445 
*/
5446 
    input [adr_width-1:2]   wb_adr_i;
5447 
    input                   wb_stb_i;
5448 
    input                   wb_cyc_i;
5449 
    output [dat_width-1:0]  wb_dat_o;
5450 
    reg [dat_width-1:0]     wb_dat_o;
5451 
    output                  wb_ack_o;
5452 
    reg                     wb_ack_o;
5453 
    output                  stall_o;
5454 
    input                   wb_clk;
5455 
    input                   wb_rst;
5456 
 
5457 
always @ (posedge wb_clk or posedge wb_rst)
5458 
    if (wb_rst)
5459 
        wb_dat_o <= {dat_width{1'b0}};
5460 
    else
5461 
         case (wb_adr_i[adr_width-1:2])
5462 
`ifdef ROM
5463 
`include `ROM
5464 
`endif
5465 
           default:
5466 
             wb_dat_o <= dat_default;
5467 
 
5468 
         endcase // case (wb_adr_i)
5469 
 
5470 
 
5471 
always @ (posedge wb_clk or posedge wb_rst)
5472 
    if (wb_rst)
5473 
        wb_ack_o <= 1'b0;
5474 
    else
5475 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5476 
 
5477 
assign stall_o = 1'b0;
5478 
 
5479 
endmodule
5480 
`endif
5481 
 
5482 
 
5483 40 unneback 
`ifdef WB_BOOT_ROM
5484 17 unneback 
// WB ROM
5485 40 unneback 
`define MODULE wb_boot_rom
5486 
module `BASE`MODULE (
5487 
`undef MODULE
5488 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5489 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5490 17 unneback 
 
5491 18 unneback 
    parameter adr_hi = 31;
5492 
    parameter adr_lo = 28;
5493 
    parameter adr_sel = 4'hf;
5494 
    parameter addr_width = 5;
5495 33 unneback 
/*
5496 17 unneback 
`ifndef BOOT_ROM
5497 
`define BOOT_ROM "boot_rom.v"
5498 
`endif
5499 33 unneback 
*/
5500 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5501 
    input               wb_stb_i;
5502 
    input               wb_cyc_i;
5503 
    output [31:0]        wb_dat_o;
5504 
    output              wb_ack_o;
5505 
    output              hit_o;
5506 
    input               wb_clk;
5507 
    input               wb_rst;
5508 
 
5509 
    wire hit;
5510 
    reg [31:0] wb_dat;
5511 
    reg wb_ack;
5512 
 
5513 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5514 17 unneback 
 
5515 
always @ (posedge wb_clk or posedge wb_rst)
5516 
    if (wb_rst)
5517 18 unneback 
        wb_dat <= 32'h15000000;
5518 17 unneback 
    else
5519 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5520 33 unneback 
`ifdef BOOT_ROM
5521 17 unneback 
`include `BOOT_ROM
5522 33 unneback 
`endif
5523 17 unneback 
           /*
5524 
            // Zero r0 and jump to 0x00000100
5525 18 unneback 
 
5526 
            1 : wb_dat <= 32'hA8200000;
5527 
            2 : wb_dat <= 32'hA8C00100;
5528 
            3 : wb_dat <= 32'h44003000;
5529 
            4 : wb_dat <= 32'h15000000;
5530 17 unneback 
            */
5531 
           default:
5532 18 unneback 
             wb_dat <= 32'h00000000;
5533 17 unneback 
 
5534 
         endcase // case (wb_adr_i)
5535 
 
5536 
 
5537 
always @ (posedge wb_clk or posedge wb_rst)
5538 
    if (wb_rst)
5539 18 unneback 
        wb_ack <= 1'b0;
5540 17 unneback 
    else
5541 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5542 17 unneback 
 
5543 18 unneback 
assign hit_o = hit;
5544 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5545 
assign wb_ack_o = wb_ack;
5546 
 
5547 17 unneback 
endmodule
5548 40 unneback 
`endif
5549 32 unneback 
 
5550 40 unneback 
`ifdef WB_DPRAM
5551 
`define MODULE wb_dpram
5552 
module `BASE`MODULE (
5553 
`undef MODULE
5554 32 unneback 
        // wishbone slave side a
5555 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5556 
        wbsa_clk, wbsa_rst,
5557 
        // wishbone slave side a
5558 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5559 
        wbsb_clk, wbsb_rst);
5560 
 
5561 
parameter data_width = 32;
5562 
parameter addr_width = 8;
5563 
 
5564 
parameter dat_o_mask_a = 1;
5565 
parameter dat_o_mask_b = 1;
5566 
 
5567 
input [31:0] wbsa_dat_i;
5568 
input [addr_width-1:2] wbsa_adr_i;
5569 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5570 
output [31:0] wbsa_dat_o;
5571 
output wbsa_ack_o;
5572 
input wbsa_clk, wbsa_rst;
5573 
 
5574 
input [31:0] wbsb_dat_i;
5575 
input [addr_width-1:2] wbsb_adr_i;
5576 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5577 
output [31:0] wbsb_dat_o;
5578 
output wbsb_ack_o;
5579 
input wbsb_clk, wbsb_rst;
5580 
 
5581 
wire wbsa_dat_tmp, wbsb_dat_tmp;
5582 
 
5583 40 unneback 
`define MODULE dpram_2r2w
5584 
`BASE`MODULE # (
5585 
`undef MODULE
5586 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
5587 32 unneback 
dpram0(
5588 
    .d_a(wbsa_dat_i),
5589 
    .q_a(wbsa_dat_tmp),
5590 
    .adr_a(wbsa_adr_i),
5591 
    .we_a(wbsa_we_i),
5592 
    .clk_a(wbsa_clk),
5593 
    .d_b(wbsb_dat_i),
5594 
    .q_b(wbsb_dat_tmp),
5595 
    .adr_b(wbsb_adr_i),
5596 
    .we_b(wbsb_we_i),
5597 
    .clk_b(wbsb_clk) );
5598 
 
5599 33 unneback 
generate if (dat_o_mask_a==1)
5600 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
5601 
endgenerate
5602 33 unneback 
generate if (dat_o_mask_a==0)
5603 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
5604 
endgenerate
5605 
 
5606 33 unneback 
generate if (dat_o_mask_b==1)
5607 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
5608 
endgenerate
5609 33 unneback 
generate if (dat_o_mask_b==0)
5610 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
5611 
endgenerate
5612 
 
5613 40 unneback 
`define MODULE spr
5614 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
5615 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
5616 
`undef MODULE
5617 32 unneback 
 
5618 
endmodule
5619 40 unneback 
`endif
5620 18 unneback 
//////////////////////////////////////////////////////////////////////
5621 
////                                                              ////
5622 
////  Arithmetic functions                                        ////
5623 
////                                                              ////
5624 
////  Description                                                 ////
5625 
////  Arithmetic functions for ALU and DSP                        ////
5626 
////                                                              ////
5627 
////                                                              ////
5628 
////  To Do:                                                      ////
5629 
////   -                                                          ////
5630 
////                                                              ////
5631 
////  Author(s):                                                  ////
5632 
////      - Michael Unneback, unneback@opencores.org              ////
5633 
////        ORSoC AB                                              ////
5634 
////                                                              ////
5635 
//////////////////////////////////////////////////////////////////////
5636 
////                                                              ////
5637 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5638 
////                                                              ////
5639 
//// This source file may be used and distributed without         ////
5640 
//// restriction provided that this copyright statement is not    ////
5641 
//// removed from the file and that any derivative work contains  ////
5642 
//// the original copyright notice and the associated disclaimer. ////
5643 
////                                                              ////
5644 
//// This source file is free software; you can redistribute it   ////
5645 
//// and/or modify it under the terms of the GNU Lesser General   ////
5646 
//// Public License as published by the Free Software Foundation; ////
5647 
//// either version 2.1 of the License, or (at your option) any   ////
5648 
//// later version.                                               ////
5649 
////                                                              ////
5650 
//// This source is distributed in the hope that it will be       ////
5651 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5652 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5653 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5654 
//// details.                                                     ////
5655 
////                                                              ////
5656 
//// You should have received a copy of the GNU Lesser General    ////
5657 
//// Public License along with this source; if not, download it   ////
5658 
//// from http://www.opencores.org/lgpl.shtml                     ////
5659 
////                                                              ////
5660 
//////////////////////////////////////////////////////////////////////
5661 
 
5662 40 unneback 
`ifdef MULTS
5663 18 unneback 
// signed multiplication
5664 40 unneback 
`define MODULE mults
5665 
module `BASE`MODULE (a,b,p);
5666 
`undef MODULE
5667 18 unneback 
parameter operand_a_width = 18;
5668 
parameter operand_b_width = 18;
5669 
parameter result_hi = 35;
5670 
parameter result_lo = 0;
5671 
input [operand_a_width-1:0] a;
5672 
input [operand_b_width-1:0] b;
5673 
output [result_hi:result_lo] p;
5674 
wire signed [operand_a_width-1:0] ai;
5675 
wire signed [operand_b_width-1:0] bi;
5676 
wire signed [operand_a_width+operand_b_width-1:0] result;
5677 
 
5678 
    assign ai = a;
5679 
    assign bi = b;
5680 
    assign result = ai * bi;
5681 
    assign p = result[result_hi:result_lo];
5682 
 
5683 
endmodule
5684 40 unneback 
`endif
5685 
`ifdef MULTS18X18
5686 
`define MODULE mults18x18
5687 
module `BASE`MODULE (a,b,p);
5688 
`undef MODULE
5689 18 unneback 
input [17:0] a,b;
5690 
output [35:0] p;
5691 
vl_mult
5692 
    # (.operand_a_width(18), .operand_b_width(18))
5693 
    mult0 (.a(a), .b(b), .p(p));
5694 
endmodule
5695 40 unneback 
`endif
5696 18 unneback 
 
5697 40 unneback 
`ifdef MULT
5698 
`define MODULE mult
5699 18 unneback 
// unsigned multiplication
5700 40 unneback 
module `BASE`MODULE (a,b,p);
5701 
`undef MODULE
5702 18 unneback 
parameter operand_a_width = 18;
5703 
parameter operand_b_width = 18;
5704 
parameter result_hi = 35;
5705 
parameter result_lo = 0;
5706 
input [operand_a_width-1:0] a;
5707 
input [operand_b_width-1:0] b;
5708 
output [result_hi:result_hi] p;
5709 
 
5710 
wire [operand_a_width+operand_b_width-1:0] result;
5711 
 
5712 
    assign result = a * b;
5713 
    assign p = result[result_hi:result_lo];
5714 
 
5715 
endmodule
5716 40 unneback 
`endif
5717 18 unneback 
 
5718 40 unneback 
`ifdef SHIFT_UNIT_32
5719 
`define MODULE shift_unit_32
5720 18 unneback 
// shift unit
5721 
// supporting the following shift functions
5722 
//   SLL
5723 
//   SRL
5724 
//   SRA
5725 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5726 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
5727 
`undef MODULE
5728 18 unneback 
input [31:0] din; // data in operand
5729 
input [4:0] s; // shift operand
5730 
input [1:0] opcode;
5731 
output [31:0] dout;
5732 
 
5733 
parameter opcode_sll = 2'b00;
5734 
//parameter opcode_srl = 2'b01;
5735 
parameter opcode_sra = 2'b10;
5736 
//parameter opcode_ror = 2'b11;
5737 
 
5738 
wire sll, sra;
5739 
assign sll = opcode == opcode_sll;
5740 
assign sra = opcode == opcode_sra;
5741 
 
5742 
wire [15:1] s1;
5743 
wire [3:0] sign;
5744 
wire [7:0] tmp [0:3];
5745 
 
5746 
// first stage is multiplier based
5747 
// shift operand as fractional 8.7
5748 
assign s1[15] = sll & s[2:0]==3'd7;
5749 
assign s1[14] = sll & s[2:0]==3'd6;
5750 
assign s1[13] = sll & s[2:0]==3'd5;
5751 
assign s1[12] = sll & s[2:0]==3'd4;
5752 
assign s1[11] = sll & s[2:0]==3'd3;
5753 
assign s1[10] = sll & s[2:0]==3'd2;
5754 
assign s1[ 9] = sll & s[2:0]==3'd1;
5755 
assign s1[ 8] = s[2:0]==3'd0;
5756 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5757 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5758 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5759 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5760 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5761 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5762 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5763 
 
5764 
assign sign[3] = din[31] & sra;
5765 
assign sign[2] = sign[3] & (&din[31:24]);
5766 
assign sign[1] = sign[2] & (&din[23:16]);
5767 
assign sign[0] = sign[1] & (&din[15:8]);
5768 40 unneback 
`define MODULE mults
5769 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5770 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5771 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5772 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5773 
`undef MODULE
5774 18 unneback 
// second stage is multiplexer based
5775 
// shift on byte level
5776 
 
5777 
// mux byte 3
5778 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5779 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5780 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5781 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5782 
                     {8{sign[3]}};
5783 
 
5784 
// mux byte 2
5785 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5786 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5787 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5788 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5789 
                     (s[4:3]==2'b01) ? tmp[3] :
5790 
                     {8{sign[3]}};
5791 
 
5792 
// mux byte 1
5793 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5794 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5795 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5796 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5797 
                     (s[4:3]==2'b01) ? tmp[2] :
5798 
                     (s[4:3]==2'b10) ? tmp[3] :
5799 
                     {8{sign[3]}};
5800 
 
5801 
// mux byte 0
5802 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5803 
                     (sll) ?  {8{1'b0}}:
5804 
                     (s[4:3]==2'b01) ? tmp[1] :
5805 
                     (s[4:3]==2'b10) ? tmp[2] :
5806 
                     tmp[3];
5807 
 
5808 
endmodule
5809 40 unneback 
`endif
5810 18 unneback 
 
5811 40 unneback 
`ifdef LOGIC_UNIT
5812 18 unneback 
// logic unit
5813 
// supporting the following logic functions
5814 
//    a and b
5815 
//    a or  b
5816 
//    a xor b
5817 
//    not b
5818 40 unneback 
`define MODULE logic_unit
5819 
module `BASE`MODULE( a, b, result, opcode);
5820 
`undef MODULE
5821 18 unneback 
parameter width = 32;
5822 
parameter opcode_and = 2'b00;
5823 
parameter opcode_or  = 2'b01;
5824 
parameter opcode_xor = 2'b10;
5825 
input [width-1:0] a,b;
5826 
output [width-1:0] result;
5827 
input [1:0] opcode;
5828 
 
5829 
assign result = (opcode==opcode_and) ? a & b :
5830 
                (opcode==opcode_or)  ? a | b :
5831 
                (opcode==opcode_xor) ? a ^ b :
5832 
                b;
5833 
 
5834 
endmodule
5835 48 unneback 
`endif
5836 18 unneback 
 
5837 48 unneback 
`ifdef ARITH_UNIT
5838 
`define MODULE arith_unit
5839 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5840 
`undef MODULE
5841 18 unneback 
parameter width = 32;
5842 
parameter opcode_add = 1'b0;
5843 
parameter opcode_sub = 1'b1;
5844 
input [width-1:0] a,b;
5845 
input c_in, add_sub, sign;
5846 
output [width-1:0] result;
5847 
output c_out, z, ovfl;
5848 
 
5849 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5850 
assign z = (result=={width{1'b0}});
5851 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5852 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5853 
endmodule
5854 40 unneback 
`endif
5855 48 unneback 
 
5856 
`ifdef COUNT_UNIT
5857 
`define MODULE count_unit
5858 
module `BASE`MODULE (din, dout, opcode);
5859 
`undef MODULE
5860 
parameter width = 32;
5861 
input [width-1:0] din;
5862 
output [width-1:0] dout;
5863 
input opcode;
5864 
 
5865 
integer i;
5866 58 unneback 
wire [width/32+4:0] ff1, fl1;
5867 48 unneback 
 
5868 57 unneback 
/*
5869 48 unneback 
always @(din) begin
5870 
    ff1 = 0; i = 0;
5871 
    while (din[i] == 0 && i < width) begin // complex condition
5872 
        ff1 = ff1 + 1;
5873 
        i = i + 1;
5874 
    end
5875 
end
5876 
 
5877 
always @(din) begin
5878 
    fl1 = width; i = width-1;
5879 
    while (din[i] == 0 && i >= width) begin // complex condition
5880 
        fl1 = fl1 - 1;
5881 
        i = i - 1;
5882 
    end
5883 
end
5884 57 unneback 
*/
5885 48 unneback 
 
5886 
generate
5887 
if (width==32) begin
5888 57 unneback 
 
5889 
    assign ff1 = din[0] ? 6'd1 :
5890 
                 din[1] ? 6'd2 :
5891 
                 din[2] ? 6'd3 :
5892 
                 din[3] ? 6'd4 :
5893 
                 din[4] ? 6'd5 :
5894 
                 din[5] ? 6'd6 :
5895 
                 din[6] ? 6'd7 :
5896 
                 din[7] ? 6'd8 :
5897 
                 din[8] ? 6'd9 :
5898 
                 din[9] ? 6'd10 :
5899 
                 din[10] ? 6'd11 :
5900 
                 din[11] ? 6'd12 :
5901 
                 din[12] ? 6'd13 :
5902 
                 din[13] ? 6'd14 :
5903 
                 din[14] ? 6'd15 :
5904 
                 din[15] ? 6'd16 :
5905 
                 din[16] ? 6'd17 :
5906 
                 din[17] ? 6'd18 :
5907 
                 din[18] ? 6'd19 :
5908 
                 din[19] ? 6'd20 :
5909 
                 din[20] ? 6'd21 :
5910 
                 din[21] ? 6'd22 :
5911 
                 din[22] ? 6'd23 :
5912 
                 din[23] ? 6'd24 :
5913 
                 din[24] ? 6'd25 :
5914 
                 din[25] ? 6'd26 :
5915 
                 din[26] ? 6'd27 :
5916 
                 din[27] ? 6'd28 :
5917 
                 din[28] ? 6'd29 :
5918 
                 din[29] ? 6'd30 :
5919 
                 din[30] ? 6'd31 :
5920 
                 din[31] ? 6'd32 :
5921 
                 6'd0;
5922 
 
5923 
    assign fl1 = din[31] ? 6'd32 :
5924 
                 din[30] ? 6'd31 :
5925 
                 din[29] ? 6'd30 :
5926 
                 din[28] ? 6'd29 :
5927 
                 din[27] ? 6'd28 :
5928 
                 din[26] ? 6'd27 :
5929 
                 din[25] ? 6'd26 :
5930 
                 din[24] ? 6'd25 :
5931 
                 din[23] ? 6'd24 :
5932 
                 din[22] ? 6'd23 :
5933 
                 din[21] ? 6'd22 :
5934 
                 din[20] ? 6'd21 :
5935 
                 din[19] ? 6'd20 :
5936 
                 din[18] ? 6'd19 :
5937 
                 din[17] ? 6'd18 :
5938 
                 din[16] ? 6'd17 :
5939 
                 din[15] ? 6'd16 :
5940 
                 din[14] ? 6'd15 :
5941 
                 din[13] ? 6'd14 :
5942 
                 din[12] ? 6'd13 :
5943 
                 din[11] ? 6'd12 :
5944 
                 din[10] ? 6'd11 :
5945 
                 din[9] ? 6'd10 :
5946 
                 din[8] ? 6'd9 :
5947 
                 din[7] ? 6'd8 :
5948 
                 din[6] ? 6'd7 :
5949 
                 din[5] ? 6'd6 :
5950 
                 din[4] ? 6'd5 :
5951 
                 din[3] ? 6'd4 :
5952 
                 din[2] ? 6'd3 :
5953 
                 din[1] ? 6'd2 :
5954 
                 din[0] ? 6'd1 :
5955 
                 6'd0;
5956 
 
5957 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5958 48 unneback 
end
5959 
endgenerate
5960 57 unneback 
 
5961 48 unneback 
generate
5962 
if (width==64) begin
5963 57 unneback 
    assign ff1 = 7'd0;
5964 
    assign fl1 = 7'd0;
5965 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5966 48 unneback 
end
5967 
endgenerate
5968 
 
5969 
endmodule
5970 
`endif
5971 
 
5972 
`ifdef EXT_UNIT
5973 
`define MODULE ext_unit
5974 
module `BASE`MODULE ( a, b, F, result, opcode);
5975 
`undef MODULE
5976 
parameter width = 32;
5977 
input [width-1:0] a, b;
5978 
input F;
5979 
output reg [width-1:0] result;
5980 
input [2:0] opcode;
5981 
 
5982 
generate
5983 
if (width==32) begin
5984 
always @ (a or b or F or opcode)
5985 
begin
5986 
    case (opcode)
5987 
    3'b000: result = {{24{1'b0}},a[7:0]};
5988 
    3'b001: result = {{24{a[7]}},a[7:0]};
5989 
    3'b010: result = {{16{1'b0}},a[7:0]};
5990 
    3'b011: result = {{16{a[15]}},a[15:0]};
5991 
    3'b110: result = (F) ? a : b;
5992 
    default: result = {b[15:0],16'h0000};
5993 
    endcase
5994 
end
5995 
end
5996 
endgenerate
5997 
 
5998 
generate
5999 
if (width==64) begin
6000 
always @ (a or b or F or opcode)
6001 
begin
6002 
    case (opcode)
6003 
    3'b000: result = {{56{1'b0}},a[7:0]};
6004 
    3'b001: result = {{56{a[7]}},a[7:0]};
6005 
    3'b010: result = {{48{1'b0}},a[7:0]};
6006 
    3'b011: result = {{48{a[15]}},a[15:0]};
6007 57 unneback 
    3'b110: result = (F) ? a : b;
6008 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
6009 
    endcase
6010 
end
6011 
end
6012 
endgenerate
6013 
endmodule
6014 
`endif

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