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1 6 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Versatile library, clock and reset                          ////
4 
////                                                              ////
5 
////  Description                                                 ////
6 
////  Logic related to clock and reset                            ////
7 
////                                                              ////
8 
////                                                              ////
9 
////  To Do:                                                      ////
10 
////   - add more different registers                             ////
11 
////                                                              ////
12 
////  Author(s):                                                  ////
13 
////      - Michael Unneback, unneback@opencores.org              ////
14 
////        ORSoC AB                                              ////
15 
////                                                              ////
16 
//////////////////////////////////////////////////////////////////////
17 
////                                                              ////
18 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19 
////                                                              ////
20 
//// This source file may be used and distributed without         ////
21 
//// restriction provided that this copyright statement is not    ////
22 
//// removed from the file and that any derivative work contains  ////
23 
//// the original copyright notice and the associated disclaimer. ////
24 
////                                                              ////
25 
//// This source file is free software; you can redistribute it   ////
26 
//// and/or modify it under the terms of the GNU Lesser General   ////
27 
//// Public License as published by the Free Software Foundation; ////
28 
//// either version 2.1 of the License, or (at your option) any   ////
29 
//// later version.                                               ////
30 
////                                                              ////
31 
//// This source is distributed in the hope that it will be       ////
32 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35 
//// details.                                                     ////
36 
////                                                              ////
37 
//// You should have received a copy of the GNU Lesser General    ////
38 
//// Public License along with this source; if not, download it   ////
39 
//// from http://www.opencores.org/lgpl.shtml                     ////
40 
////                                                              ////
41 
//////////////////////////////////////////////////////////////////////
42 
// Global buffer
43 
// usage:
44 
// use to enable global buffers for high fan out signals such as clock and reset
45 
`timescale 1 ns/100 ps
46 
// Version: 8.4 8.4.0.33
47 
module gbuf(GL,CLK);
48 
output GL;
49 
input  CLK;
50 
    wire GND;
51 
    GND GND_1_net(.Y(GND));
52 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54 
endmodule
55 
`timescale 1 ns/1 ns
56 
module vl_gbuf ( i, o);
57 
input i;
58 
output o;
59 
`ifdef SIM_GBUF
60 
assign o=i;
61 
`else
62 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63 
`endif
64 
endmodule
65 
 //ACTEL
66 
// sync reset
67 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback 
// output active high global reset sync with two DFFs
69 
`timescale 1 ns/100 ps
70 
module vl_sync_rst ( rst_n_i, rst_o, clk);
71 
input rst_n_i, clk;
72 
output rst_o;
73 
reg [0:1] tmp;
74 
always @ (posedge clk or negedge rst_n_i)
75 
if (!rst_n_i)
76 17 unneback 
        tmp <= 2'b11;
77 6 unneback 
else
78 17 unneback 
        tmp <= {1'b0,tmp[0]};
79 
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback 
endmodule
81 
// vl_pll
82 17 unneback 
`timescale 1 ps/1 ps
83 6 unneback 
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84 
parameter index = 0;
85 
parameter number_of_clk = 1;
86 17 unneback 
parameter period_time_0 = 20000;
87 
parameter period_time_1 = 20000;
88 
parameter period_time_2 = 20000;
89 
parameter lock_delay = 2000000;
90 6 unneback 
input clk_i, rst_n_i;
91 
output lock;
92 
output reg [0:number_of_clk-1] clk_o;
93 
output [0:number_of_clk-1] rst_o;
94 
`ifdef SIM_PLL
95 
always
96 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97 
generate if (number_of_clk > 1)
98 
always
99 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100 
endgenerate
101 
generate if (number_of_clk > 2)
102 
always
103 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104 
endgenerate
105 
genvar i;
106 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108 
end
109 
endgenerate
110 
assign #lock_delay lock = rst_n_i;
111 
endmodule
112 
`else
113 
generate if (number_of_clk==1 & index==0) begin
114 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115 
end
116 
endgenerate // index==0
117 
generate if (number_of_clk==1 & index==1) begin
118 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119 
end
120 
endgenerate // index==1
121 
generate if (number_of_clk==1 & index==2) begin
122 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123 
end
124 
endgenerate // index==2
125 
generate if (number_of_clk==1 & index==3) begin
126 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127 
end
128 
endgenerate // index==0
129 
generate if (number_of_clk==2 & index==0) begin
130 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131 
end
132 
endgenerate // index==0
133 
generate if (number_of_clk==2 & index==1) begin
134 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135 
end
136 
endgenerate // index==1
137 
generate if (number_of_clk==2 & index==2) begin
138 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139 
end
140 
endgenerate // index==2
141 
generate if (number_of_clk==2 & index==3) begin
142 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143 
end
144 
endgenerate // index==0
145 
generate if (number_of_clk==3 & index==0) begin
146 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147 
end
148 
endgenerate // index==0
149 
generate if (number_of_clk==3 & index==1) begin
150 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151 
end
152 
endgenerate // index==1
153 
generate if (number_of_clk==3 & index==2) begin
154 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155 
end
156 
endgenerate // index==2
157 
generate if (number_of_clk==3 & index==3) begin
158 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159 
end
160 
endgenerate // index==0
161 
genvar i;
162 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163 
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164 
end
165 
endgenerate
166 
endmodule
167 
`endif
168 
 //actel
169 
//////////////////////////////////////////////////////////////////////
170 
////                                                              ////
171 
////  Versatile library, registers                                ////
172 
////                                                              ////
173 
////  Description                                                 ////
174 
////  Different type of registers                                 ////
175 
////                                                              ////
176 
////                                                              ////
177 
////  To Do:                                                      ////
178 
////   - add more different registers                             ////
179 
////                                                              ////
180 
////  Author(s):                                                  ////
181 
////      - Michael Unneback, unneback@opencores.org              ////
182 
////        ORSoC AB                                              ////
183 
////                                                              ////
184 
//////////////////////////////////////////////////////////////////////
185 
////                                                              ////
186 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187 
////                                                              ////
188 
//// This source file may be used and distributed without         ////
189 
//// restriction provided that this copyright statement is not    ////
190 
//// removed from the file and that any derivative work contains  ////
191 
//// the original copyright notice and the associated disclaimer. ////
192 
////                                                              ////
193 
//// This source file is free software; you can redistribute it   ////
194 
//// and/or modify it under the terms of the GNU Lesser General   ////
195 
//// Public License as published by the Free Software Foundation; ////
196 
//// either version 2.1 of the License, or (at your option) any   ////
197 
//// later version.                                               ////
198 
////                                                              ////
199 
//// This source is distributed in the hope that it will be       ////
200 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203 
//// details.                                                     ////
204 
////                                                              ////
205 
//// You should have received a copy of the GNU Lesser General    ////
206 
//// Public License along with this source; if not, download it   ////
207 
//// from http://www.opencores.org/lgpl.shtml                     ////
208 
////                                                              ////
209 
//////////////////////////////////////////////////////////////////////
210 
module dff ( d, q, clk, rst);
211 
        parameter width = 1;
212 
        parameter reset_value = 0;
213 
        input [width-1:0] d;
214 
        input clk, rst;
215 
        output reg [width-1:0] q;
216 
        always @ (posedge clk or posedge rst)
217 
        if (rst)
218 
                q <= reset_value;
219 
        else
220 
                q <= d;
221 
endmodule
222 
module dff_array ( d, q, clk, rst);
223 
        parameter width = 1;
224 
        parameter depth = 2;
225 
        parameter reset_value = 1'b0;
226 
        input [width-1:0] d;
227 
        input clk, rst;
228 
        output [width-1:0] q;
229 
        reg  [0:depth-1] q_tmp [width-1:0];
230 
        integer i;
231 
        always @ (posedge clk or posedge rst)
232 
        if (rst) begin
233 
            for (i=0;i<depth;i=i+1)
234 
                q_tmp[i] <= {width{reset_value}};
235 
        end else begin
236 
            q_tmp[0] <= d;
237 
            for (i=1;i<depth;i=i+1)
238 
                q_tmp[i] <= q_tmp[i-1];
239 
        end
240 
    assign q = q_tmp[depth-1];
241 
endmodule
242 
module dff_ce ( d, ce, q, clk, rst);
243 
        parameter width = 1;
244 
        parameter reset_value = 0;
245 
        input [width-1:0] d;
246 
        input ce, clk, rst;
247 
        output reg [width-1:0] q;
248 
        always @ (posedge clk or posedge rst)
249 
        if (rst)
250 
                q <= reset_value;
251 
        else
252 
                if (ce)
253 
                        q <= d;
254 
endmodule
255 8 unneback 
module dff_ce_clear ( d, ce, clear, q, clk, rst);
256 
        parameter width = 1;
257 
        parameter reset_value = 0;
258 
        input [width-1:0] d;
259 10 unneback 
        input ce, clear, clk, rst;
260 8 unneback 
        output reg [width-1:0] q;
261 
        always @ (posedge clk or posedge rst)
262 
        if (rst)
263 
            q <= reset_value;
264 
        else
265 
            if (ce)
266 
                if (clear)
267 
                    q <= {width{1'b0}};
268 
                else
269 
                    q <= d;
270 
endmodule
271 6 unneback 
module dff_sr ( aclr, aset, clock, data, q);
272 
    input         aclr;
273 
    input         aset;
274 
    input         clock;
275 
    input         data;
276 
    output reg    q;
277 
   always @ (posedge clock or posedge aclr or posedge aset)
278 
     if (aclr)
279 
       q <= 1'b0;
280 
     else if (aset)
281 
       q <= 1'b1;
282 
     else
283 
       q <= data;
284 
endmodule
285 
// LATCH
286 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
287 
module latch ( d, le, q, clk);
288 
input d, le;
289 
output q;
290 
input clk;/*
291 
   always @ (posedge direction_set or posedge direction_clr)
292 
     if (direction_clr)
293 
       direction <= going_empty;
294 
     else
295 
       direction <= going_full;*/
296 
endmodule
297 17 unneback 
module shreg ( d, q, clk, rst);
298 
parameter depth = 10;
299 
input d;
300 
output q;
301 
input clk, rst;
302 
reg [1:depth] dffs;
303 
always @ (posedge clk or posedge rst)
304 
if (rst)
305 
    dffs <= {depth{1'b0}};
306 
else
307 
    dffs <= {d,dffs[1:depth-1]};
308 
assign q = dffs[depth];
309 
endmodule
310 
module shreg_ce ( d, ce, q, clk, rst);
311 
parameter depth = 10;
312 
input d, ce;
313 
output q;
314 
input clk, rst;
315 
reg [1:depth] dffs;
316 
always @ (posedge clk or posedge rst)
317 
if (rst)
318 
    dffs <= {depth{1'b0}};
319 
else
320 
    if (ce)
321 
        dffs <= {d,dffs[1:depth-1]};
322 
assign q = dffs[depth];
323 
endmodule
324 15 unneback 
module delay ( d, q, clk, rst);
325 
parameter depth = 10;
326 
input d;
327 
output q;
328 
input clk, rst;
329 
reg [1:depth] dffs;
330 
always @ (posedge clk or posedge rst)
331 
if (rst)
332 
    dffs <= {depth{1'b0}};
333 
else
334 
    dffs <= {d,dffs[1:depth-1]};
335 
assign q = dffs[depth];
336 
endmodule
337 17 unneback 
module delay_emptyflag ( d, q, emptyflag, clk, rst);
338 
parameter depth = 10;
339 
input d;
340 
output q, emptyflag;
341 
input clk, rst;
342 
reg [1:depth] dffs;
343 
always @ (posedge clk or posedge rst)
344 
if (rst)
345 
    dffs <= {depth{1'b0}};
346 
else
347 
    dffs <= {d,dffs[1:depth-1]};
348 
assign q = dffs[depth];
349 
assign emptyflag = !(|dffs);
350 
endmodule
351 6 unneback 
//////////////////////////////////////////////////////////////////////
352 
////                                                              ////
353 
////  Versatile counter                                           ////
354 
////                                                              ////
355 
////  Description                                                 ////
356 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
357 
////  counter                                                     ////
358 
////                                                              ////
359 
////  To Do:                                                      ////
360 
////   - add LFSR with more taps                                  ////
361 
////                                                              ////
362 
////  Author(s):                                                  ////
363 
////      - Michael Unneback, unneback@opencores.org              ////
364 
////        ORSoC AB                                              ////
365 
////                                                              ////
366 
//////////////////////////////////////////////////////////////////////
367 
////                                                              ////
368 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
369 
////                                                              ////
370 
//// This source file may be used and distributed without         ////
371 
//// restriction provided that this copyright statement is not    ////
372 
//// removed from the file and that any derivative work contains  ////
373 
//// the original copyright notice and the associated disclaimer. ////
374 
////                                                              ////
375 
//// This source file is free software; you can redistribute it   ////
376 
//// and/or modify it under the terms of the GNU Lesser General   ////
377 
//// Public License as published by the Free Software Foundation; ////
378 
//// either version 2.1 of the License, or (at your option) any   ////
379 
//// later version.                                               ////
380 
////                                                              ////
381 
//// This source is distributed in the hope that it will be       ////
382 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
383 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
384 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
385 
//// details.                                                     ////
386 
////                                                              ////
387 
//// You should have received a copy of the GNU Lesser General    ////
388 
//// Public License along with this source; if not, download it   ////
389 
//// from http://www.opencores.org/lgpl.shtml                     ////
390 
////                                                              ////
391 
//////////////////////////////////////////////////////////////////////
392 
// binary counter
393 
module cnt_bin_ce ( cke, q, rst, clk);
394 
   parameter length = 4;
395 
   input cke;
396 
   output [length:1] q;
397 
   input rst;
398 
   input clk;
399 
   parameter clear_value = 0;
400 
   parameter set_value = 1;
401 
   parameter wrap_value = 0;
402 
   parameter level1_value = 15;
403 
   reg  [length:1] qi;
404 
   wire [length:1] q_next;
405 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
406 
   always @ (posedge clk or posedge rst)
407 
     if (rst)
408 
       qi <= {length{1'b0}};
409 
     else
410 
     if (cke)
411 
       qi <= q_next;
412 
   assign q = qi;
413 
endmodule
414 
//////////////////////////////////////////////////////////////////////
415 
////                                                              ////
416 
////  Versatile counter                                           ////
417 
////                                                              ////
418 
////  Description                                                 ////
419 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
420 
////  counter                                                     ////
421 
////                                                              ////
422 
////  To Do:                                                      ////
423 
////   - add LFSR with more taps                                  ////
424 
////                                                              ////
425 
////  Author(s):                                                  ////
426 
////      - Michael Unneback, unneback@opencores.org              ////
427 
////        ORSoC AB                                              ////
428 
////                                                              ////
429 
//////////////////////////////////////////////////////////////////////
430 
////                                                              ////
431 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
432 
////                                                              ////
433 
//// This source file may be used and distributed without         ////
434 
//// restriction provided that this copyright statement is not    ////
435 
//// removed from the file and that any derivative work contains  ////
436 
//// the original copyright notice and the associated disclaimer. ////
437 
////                                                              ////
438 
//// This source file is free software; you can redistribute it   ////
439 
//// and/or modify it under the terms of the GNU Lesser General   ////
440 
//// Public License as published by the Free Software Foundation; ////
441 
//// either version 2.1 of the License, or (at your option) any   ////
442 
//// later version.                                               ////
443 
////                                                              ////
444 
//// This source is distributed in the hope that it will be       ////
445 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
446 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
447 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
448 
//// details.                                                     ////
449 
////                                                              ////
450 
//// You should have received a copy of the GNU Lesser General    ////
451 
//// Public License along with this source; if not, download it   ////
452 
//// from http://www.opencores.org/lgpl.shtml                     ////
453 
////                                                              ////
454 
//////////////////////////////////////////////////////////////////////
455 
// binary counter
456 
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
457 
   parameter length = 4;
458 
   input clear;
459 
   input cke;
460 
   output [length:1] q;
461 
   input rst;
462 
   input clk;
463 
   parameter clear_value = 0;
464 
   parameter set_value = 1;
465 
   parameter wrap_value = 0;
466 
   parameter level1_value = 15;
467 
   reg  [length:1] qi;
468 
   wire [length:1] q_next;
469 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
470 
   always @ (posedge clk or posedge rst)
471 
     if (rst)
472 
       qi <= {length{1'b0}};
473 
     else
474 
     if (cke)
475 
       qi <= q_next;
476 
   assign q = qi;
477 
endmodule
478 
//////////////////////////////////////////////////////////////////////
479 
////                                                              ////
480 
////  Versatile counter                                           ////
481 
////                                                              ////
482 
////  Description                                                 ////
483 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
484 
////  counter                                                     ////
485 
////                                                              ////
486 
////  To Do:                                                      ////
487 
////   - add LFSR with more taps                                  ////
488 
////                                                              ////
489 
////  Author(s):                                                  ////
490 
////      - Michael Unneback, unneback@opencores.org              ////
491 
////        ORSoC AB                                              ////
492 
////                                                              ////
493 
//////////////////////////////////////////////////////////////////////
494 
////                                                              ////
495 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
496 
////                                                              ////
497 
//// This source file may be used and distributed without         ////
498 
//// restriction provided that this copyright statement is not    ////
499 
//// removed from the file and that any derivative work contains  ////
500 
//// the original copyright notice and the associated disclaimer. ////
501 
////                                                              ////
502 
//// This source file is free software; you can redistribute it   ////
503 
//// and/or modify it under the terms of the GNU Lesser General   ////
504 
//// Public License as published by the Free Software Foundation; ////
505 
//// either version 2.1 of the License, or (at your option) any   ////
506 
//// later version.                                               ////
507 
////                                                              ////
508 
//// This source is distributed in the hope that it will be       ////
509 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
510 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
511 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
512 
//// details.                                                     ////
513 
////                                                              ////
514 
//// You should have received a copy of the GNU Lesser General    ////
515 
//// Public License along with this source; if not, download it   ////
516 
//// from http://www.opencores.org/lgpl.shtml                     ////
517 
////                                                              ////
518 
//////////////////////////////////////////////////////////////////////
519 
// binary counter
520 
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
521 
   parameter length = 4;
522 
   input clear;
523 
   input set;
524 
   input cke;
525 
   input rew;
526 
   output [length:1] q;
527 
   input rst;
528 
   input clk;
529 
   parameter clear_value = 0;
530 
   parameter set_value = 1;
531 
   parameter wrap_value = 0;
532 
   parameter level1_value = 15;
533 
   reg  [length:1] qi;
534 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
535 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
536 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
537 
   assign q_next = rew ? q_next_rew : q_next_fw;
538 
   always @ (posedge clk or posedge rst)
539 
     if (rst)
540 
       qi <= {length{1'b0}};
541 
     else
542 
     if (cke)
543 
       qi <= q_next;
544 
   assign q = qi;
545 
endmodule
546 
//////////////////////////////////////////////////////////////////////
547 
////                                                              ////
548 
////  Versatile counter                                           ////
549 
////                                                              ////
550 
////  Description                                                 ////
551 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
552 
////  counter                                                     ////
553 
////                                                              ////
554 
////  To Do:                                                      ////
555 
////   - add LFSR with more taps                                  ////
556 
////                                                              ////
557 
////  Author(s):                                                  ////
558 
////      - Michael Unneback, unneback@opencores.org              ////
559 
////        ORSoC AB                                              ////
560 
////                                                              ////
561 
//////////////////////////////////////////////////////////////////////
562 
////                                                              ////
563 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
564 
////                                                              ////
565 
//// This source file may be used and distributed without         ////
566 
//// restriction provided that this copyright statement is not    ////
567 
//// removed from the file and that any derivative work contains  ////
568 
//// the original copyright notice and the associated disclaimer. ////
569 
////                                                              ////
570 
//// This source file is free software; you can redistribute it   ////
571 
//// and/or modify it under the terms of the GNU Lesser General   ////
572 
//// Public License as published by the Free Software Foundation; ////
573 
//// either version 2.1 of the License, or (at your option) any   ////
574 
//// later version.                                               ////
575 
////                                                              ////
576 
//// This source is distributed in the hope that it will be       ////
577 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
578 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
579 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
580 
//// details.                                                     ////
581 
////                                                              ////
582 
//// You should have received a copy of the GNU Lesser General    ////
583 
//// Public License along with this source; if not, download it   ////
584 
//// from http://www.opencores.org/lgpl.shtml                     ////
585 
////                                                              ////
586 
//////////////////////////////////////////////////////////////////////
587 
// binary counter
588 
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
589 
   parameter length = 4;
590 
   input cke;
591 
   input rew;
592 
   output reg level1;
593 
   input rst;
594 
   input clk;
595 
   parameter clear_value = 0;
596 
   parameter set_value = 1;
597 
   parameter wrap_value = 1;
598 
   parameter level1_value = 15;
599 
   reg  [length:1] qi;
600 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
601 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
602 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
603 
   assign q_next = rew ? q_next_rew : q_next_fw;
604 
   always @ (posedge clk or posedge rst)
605 
     if (rst)
606 
       qi <= {length{1'b0}};
607 
     else
608 
     if (cke)
609 
       qi <= q_next;
610 
    always @ (posedge clk or posedge rst)
611 
    if (rst)
612 
        level1 <= 1'b0;
613 
    else
614 
    if (cke)
615 
    if (q_next == level1_value)
616 
        level1 <= 1'b1;
617 
    else if (qi == level1_value & rew)
618 
        level1 <= 1'b0;
619 
endmodule
620 
//////////////////////////////////////////////////////////////////////
621 
////                                                              ////
622 
////  Versatile counter                                           ////
623 
////                                                              ////
624 
////  Description                                                 ////
625 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
626 
////  counter                                                     ////
627 
////                                                              ////
628 
////  To Do:                                                      ////
629 
////   - add LFSR with more taps                                  ////
630 
////                                                              ////
631 
////  Author(s):                                                  ////
632 
////      - Michael Unneback, unneback@opencores.org              ////
633 
////        ORSoC AB                                              ////
634 
////                                                              ////
635 
//////////////////////////////////////////////////////////////////////
636 
////                                                              ////
637 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
638 
////                                                              ////
639 
//// This source file may be used and distributed without         ////
640 
//// restriction provided that this copyright statement is not    ////
641 
//// removed from the file and that any derivative work contains  ////
642 
//// the original copyright notice and the associated disclaimer. ////
643 
////                                                              ////
644 
//// This source file is free software; you can redistribute it   ////
645 
//// and/or modify it under the terms of the GNU Lesser General   ////
646 
//// Public License as published by the Free Software Foundation; ////
647 
//// either version 2.1 of the License, or (at your option) any   ////
648 
//// later version.                                               ////
649 
////                                                              ////
650 
//// This source is distributed in the hope that it will be       ////
651 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
652 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
653 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
654 
//// details.                                                     ////
655 
////                                                              ////
656 
//// You should have received a copy of the GNU Lesser General    ////
657 
//// Public License along with this source; if not, download it   ////
658 
//// from http://www.opencores.org/lgpl.shtml                     ////
659 
////                                                              ////
660 
//////////////////////////////////////////////////////////////////////
661 
// LFSR counter
662 
module cnt_lfsr_zq ( zq, rst, clk);
663 
   parameter length = 4;
664 
   output reg zq;
665 
   input rst;
666 
   input clk;
667 
   parameter clear_value = 0;
668 
   parameter set_value = 1;
669 
   parameter wrap_value = 8;
670 
   parameter level1_value = 15;
671 
   reg  [length:1] qi;
672 
   reg lfsr_fb;
673 
   wire [length:1] q_next;
674 
   reg [32:1] polynom;
675 
   integer i;
676 
   always @ (qi)
677 
   begin
678 
        case (length)
679 
         2: polynom = 32'b11;                               // 0x3
680 
         3: polynom = 32'b110;                              // 0x6
681 
         4: polynom = 32'b1100;                             // 0xC
682 
         5: polynom = 32'b10100;                            // 0x14
683 
         6: polynom = 32'b110000;                           // 0x30
684 
         7: polynom = 32'b1100000;                          // 0x60
685 
         8: polynom = 32'b10111000;                         // 0xb8
686 
         9: polynom = 32'b100010000;                        // 0x110
687 
        10: polynom = 32'b1001000000;                       // 0x240
688 
        11: polynom = 32'b10100000000;                      // 0x500
689 
        12: polynom = 32'b100000101001;                     // 0x829
690 
        13: polynom = 32'b1000000001100;                    // 0x100C
691 
        14: polynom = 32'b10000000010101;                   // 0x2015
692 
        15: polynom = 32'b110000000000000;                  // 0x6000
693 
        16: polynom = 32'b1101000000001000;                 // 0xD008
694 
        17: polynom = 32'b10010000000000000;                // 0x12000
695 
        18: polynom = 32'b100000010000000000;               // 0x20400
696 
        19: polynom = 32'b1000000000000100011;              // 0x40023
697 
        20: polynom = 32'b10000010000000000000;             // 0x82000
698 
        21: polynom = 32'b101000000000000000000;            // 0x140000
699 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
700 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
701 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
702 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
703 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
704 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
705 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
706 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
707 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
708 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
709 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
710 
        default: polynom = 32'b0;
711 
        endcase
712 
        lfsr_fb = qi[length];
713 
        for (i=length-1; i>=1; i=i-1) begin
714 
            if (polynom[i])
715 
                lfsr_fb = lfsr_fb  ~^ qi[i];
716 
        end
717 
    end
718 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
719 
   always @ (posedge clk or posedge rst)
720 
     if (rst)
721 
       qi <= {length{1'b0}};
722 
     else
723 
       qi <= q_next;
724 
   always @ (posedge clk or posedge rst)
725 
     if (rst)
726 
       zq <= 1'b1;
727 
     else
728 
       zq <= q_next == {length{1'b0}};
729 
endmodule
730 
//////////////////////////////////////////////////////////////////////
731 
////                                                              ////
732 
////  Versatile counter                                           ////
733 
////                                                              ////
734 
////  Description                                                 ////
735 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
736 
////  counter                                                     ////
737 
////                                                              ////
738 
////  To Do:                                                      ////
739 
////   - add LFSR with more taps                                  ////
740 
////                                                              ////
741 
////  Author(s):                                                  ////
742 
////      - Michael Unneback, unneback@opencores.org              ////
743 
////        ORSoC AB                                              ////
744 
////                                                              ////
745 
//////////////////////////////////////////////////////////////////////
746 
////                                                              ////
747 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
748 
////                                                              ////
749 
//// This source file may be used and distributed without         ////
750 
//// restriction provided that this copyright statement is not    ////
751 
//// removed from the file and that any derivative work contains  ////
752 
//// the original copyright notice and the associated disclaimer. ////
753 
////                                                              ////
754 
//// This source file is free software; you can redistribute it   ////
755 
//// and/or modify it under the terms of the GNU Lesser General   ////
756 
//// Public License as published by the Free Software Foundation; ////
757 
//// either version 2.1 of the License, or (at your option) any   ////
758 
//// later version.                                               ////
759 
////                                                              ////
760 
//// This source is distributed in the hope that it will be       ////
761 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
762 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
763 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
764 
//// details.                                                     ////
765 
////                                                              ////
766 
//// You should have received a copy of the GNU Lesser General    ////
767 
//// Public License along with this source; if not, download it   ////
768 
//// from http://www.opencores.org/lgpl.shtml                     ////
769 
////                                                              ////
770 
//////////////////////////////////////////////////////////////////////
771 
// LFSR counter
772 
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
773 
   parameter length = 4;
774 
   input cke;
775 
   output reg zq;
776 
   input rst;
777 
   input clk;
778 
   parameter clear_value = 0;
779 
   parameter set_value = 1;
780 
   parameter wrap_value = 8;
781 
   parameter level1_value = 15;
782 
   reg  [length:1] qi;
783 
   reg lfsr_fb;
784 
   wire [length:1] q_next;
785 
   reg [32:1] polynom;
786 
   integer i;
787 
   always @ (qi)
788 
   begin
789 
        case (length)
790 
         2: polynom = 32'b11;                               // 0x3
791 
         3: polynom = 32'b110;                              // 0x6
792 
         4: polynom = 32'b1100;                             // 0xC
793 
         5: polynom = 32'b10100;                            // 0x14
794 
         6: polynom = 32'b110000;                           // 0x30
795 
         7: polynom = 32'b1100000;                          // 0x60
796 
         8: polynom = 32'b10111000;                         // 0xb8
797 
         9: polynom = 32'b100010000;                        // 0x110
798 
        10: polynom = 32'b1001000000;                       // 0x240
799 
        11: polynom = 32'b10100000000;                      // 0x500
800 
        12: polynom = 32'b100000101001;                     // 0x829
801 
        13: polynom = 32'b1000000001100;                    // 0x100C
802 
        14: polynom = 32'b10000000010101;                   // 0x2015
803 
        15: polynom = 32'b110000000000000;                  // 0x6000
804 
        16: polynom = 32'b1101000000001000;                 // 0xD008
805 
        17: polynom = 32'b10010000000000000;                // 0x12000
806 
        18: polynom = 32'b100000010000000000;               // 0x20400
807 
        19: polynom = 32'b1000000000000100011;              // 0x40023
808 
        20: polynom = 32'b10000010000000000000;             // 0x82000
809 
        21: polynom = 32'b101000000000000000000;            // 0x140000
810 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
811 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
812 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
813 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
814 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
815 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
816 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
817 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
818 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
819 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
820 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
821 
        default: polynom = 32'b0;
822 
        endcase
823 
        lfsr_fb = qi[length];
824 
        for (i=length-1; i>=1; i=i-1) begin
825 
            if (polynom[i])
826 
                lfsr_fb = lfsr_fb  ~^ qi[i];
827 
        end
828 
    end
829 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
830 
   always @ (posedge clk or posedge rst)
831 
     if (rst)
832 
       qi <= {length{1'b0}};
833 
     else
834 
     if (cke)
835 
       qi <= q_next;
836 
   always @ (posedge clk or posedge rst)
837 
     if (rst)
838 
       zq <= 1'b1;
839 
     else
840 
     if (cke)
841 
       zq <= q_next == {length{1'b0}};
842 
endmodule
843 
//////////////////////////////////////////////////////////////////////
844 
////                                                              ////
845 
////  Versatile counter                                           ////
846 
////                                                              ////
847 
////  Description                                                 ////
848 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
849 
////  counter                                                     ////
850 
////                                                              ////
851 
////  To Do:                                                      ////
852 
////   - add LFSR with more taps                                  ////
853 
////                                                              ////
854 
////  Author(s):                                                  ////
855 
////      - Michael Unneback, unneback@opencores.org              ////
856 
////        ORSoC AB                                              ////
857 
////                                                              ////
858 
//////////////////////////////////////////////////////////////////////
859 
////                                                              ////
860 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
861 
////                                                              ////
862 
//// This source file may be used and distributed without         ////
863 
//// restriction provided that this copyright statement is not    ////
864 
//// removed from the file and that any derivative work contains  ////
865 
//// the original copyright notice and the associated disclaimer. ////
866 
////                                                              ////
867 
//// This source file is free software; you can redistribute it   ////
868 
//// and/or modify it under the terms of the GNU Lesser General   ////
869 
//// Public License as published by the Free Software Foundation; ////
870 
//// either version 2.1 of the License, or (at your option) any   ////
871 
//// later version.                                               ////
872 
////                                                              ////
873 
//// This source is distributed in the hope that it will be       ////
874 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
875 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
876 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
877 
//// details.                                                     ////
878 
////                                                              ////
879 
//// You should have received a copy of the GNU Lesser General    ////
880 
//// Public License along with this source; if not, download it   ////
881 
//// from http://www.opencores.org/lgpl.shtml                     ////
882 
////                                                              ////
883 
//////////////////////////////////////////////////////////////////////
884 
// LFSR counter
885 
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
886 
   parameter length = 4;
887 
   input cke;
888 
   input rew;
889 
   output reg level1;
890 
   input rst;
891 
   input clk;
892 
   parameter clear_value = 0;
893 
   parameter set_value = 1;
894 
   parameter wrap_value = 8;
895 
   parameter level1_value = 15;
896 
   reg  [length:1] qi;
897 
   reg lfsr_fb, lfsr_fb_rew;
898 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
899 
   reg [32:1] polynom_rew;
900 
   integer j;
901 
   reg [32:1] polynom;
902 
   integer i;
903 
   always @ (qi)
904 
   begin
905 
        case (length)
906 
         2: polynom = 32'b11;                               // 0x3
907 
         3: polynom = 32'b110;                              // 0x6
908 
         4: polynom = 32'b1100;                             // 0xC
909 
         5: polynom = 32'b10100;                            // 0x14
910 
         6: polynom = 32'b110000;                           // 0x30
911 
         7: polynom = 32'b1100000;                          // 0x60
912 
         8: polynom = 32'b10111000;                         // 0xb8
913 
         9: polynom = 32'b100010000;                        // 0x110
914 
        10: polynom = 32'b1001000000;                       // 0x240
915 
        11: polynom = 32'b10100000000;                      // 0x500
916 
        12: polynom = 32'b100000101001;                     // 0x829
917 
        13: polynom = 32'b1000000001100;                    // 0x100C
918 
        14: polynom = 32'b10000000010101;                   // 0x2015
919 
        15: polynom = 32'b110000000000000;                  // 0x6000
920 
        16: polynom = 32'b1101000000001000;                 // 0xD008
921 
        17: polynom = 32'b10010000000000000;                // 0x12000
922 
        18: polynom = 32'b100000010000000000;               // 0x20400
923 
        19: polynom = 32'b1000000000000100011;              // 0x40023
924 
        20: polynom = 32'b10000010000000000000;             // 0x82000
925 
        21: polynom = 32'b101000000000000000000;            // 0x140000
926 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
927 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
928 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
929 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
930 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
931 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
932 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
933 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
934 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
935 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
936 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
937 
        default: polynom = 32'b0;
938 
        endcase
939 
        lfsr_fb = qi[length];
940 
        for (i=length-1; i>=1; i=i-1) begin
941 
            if (polynom[i])
942 
                lfsr_fb = lfsr_fb  ~^ qi[i];
943 
        end
944 
    end
945 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
946 
   always @ (qi)
947 
   begin
948 
        case (length)
949 
         2: polynom_rew = 32'b11;
950 
         3: polynom_rew = 32'b110;
951 
         4: polynom_rew = 32'b1100;
952 
         5: polynom_rew = 32'b10100;
953 
         6: polynom_rew = 32'b110000;
954 
         7: polynom_rew = 32'b1100000;
955 
         8: polynom_rew = 32'b10111000;
956 
         9: polynom_rew = 32'b100010000;
957 
        10: polynom_rew = 32'b1001000000;
958 
        11: polynom_rew = 32'b10100000000;
959 
        12: polynom_rew = 32'b100000101001;
960 
        13: polynom_rew = 32'b1000000001100;
961 
        14: polynom_rew = 32'b10000000010101;
962 
        15: polynom_rew = 32'b110000000000000;
963 
        16: polynom_rew = 32'b1101000000001000;
964 
        17: polynom_rew = 32'b10010000000000000;
965 
        18: polynom_rew = 32'b100000010000000000;
966 
        19: polynom_rew = 32'b1000000000000100011;
967 
        20: polynom_rew = 32'b10000010000000000000;
968 
        21: polynom_rew = 32'b101000000000000000000;
969 
        22: polynom_rew = 32'b1100000000000000000000;
970 
        23: polynom_rew = 32'b10000100000000000000000;
971 
        24: polynom_rew = 32'b111000010000000000000000;
972 
        25: polynom_rew = 32'b1001000000000000000000000;
973 
        26: polynom_rew = 32'b10000000000000000000100011;
974 
        27: polynom_rew = 32'b100000000000000000000010011;
975 
        28: polynom_rew = 32'b1100100000000000000000000000;
976 
        29: polynom_rew = 32'b10100000000000000000000000000;
977 
        30: polynom_rew = 32'b100000000000000000000000101001;
978 
        31: polynom_rew = 32'b1001000000000000000000000000000;
979 
        32: polynom_rew = 32'b10000000001000000000000000000011;
980 
        default: polynom_rew = 32'b0;
981 
        endcase
982 
        // rotate left
983 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
984 
        lfsr_fb_rew = qi[length];
985 
        for (i=length-1; i>=1; i=i-1) begin
986 
            if (polynom_rew[i])
987 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
988 
        end
989 
    end
990 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
991 
   assign q_next = rew ? q_next_rew : q_next_fw;
992 
   always @ (posedge clk or posedge rst)
993 
     if (rst)
994 
       qi <= {length{1'b0}};
995 
     else
996 
     if (cke)
997 
       qi <= q_next;
998 
    always @ (posedge clk or posedge rst)
999 
    if (rst)
1000 
        level1 <= 1'b0;
1001 
    else
1002 
    if (cke)
1003 
    if (q_next == level1_value)
1004 
        level1 <= 1'b1;
1005 
    else if (qi == level1_value & rew)
1006 
        level1 <= 1'b0;
1007 
endmodule
1008 
//////////////////////////////////////////////////////////////////////
1009 
////                                                              ////
1010 
////  Versatile counter                                           ////
1011 
////                                                              ////
1012 
////  Description                                                 ////
1013 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1014 
////  counter                                                     ////
1015 
////                                                              ////
1016 
////  To Do:                                                      ////
1017 
////   - add LFSR with more taps                                  ////
1018 
////                                                              ////
1019 
////  Author(s):                                                  ////
1020 
////      - Michael Unneback, unneback@opencores.org              ////
1021 
////        ORSoC AB                                              ////
1022 
////                                                              ////
1023 
//////////////////////////////////////////////////////////////////////
1024 
////                                                              ////
1025 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1026 
////                                                              ////
1027 
//// This source file may be used and distributed without         ////
1028 
//// restriction provided that this copyright statement is not    ////
1029 
//// removed from the file and that any derivative work contains  ////
1030 
//// the original copyright notice and the associated disclaimer. ////
1031 
////                                                              ////
1032 
//// This source file is free software; you can redistribute it   ////
1033 
//// and/or modify it under the terms of the GNU Lesser General   ////
1034 
//// Public License as published by the Free Software Foundation; ////
1035 
//// either version 2.1 of the License, or (at your option) any   ////
1036 
//// later version.                                               ////
1037 
////                                                              ////
1038 
//// This source is distributed in the hope that it will be       ////
1039 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1040 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1041 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1042 
//// details.                                                     ////
1043 
////                                                              ////
1044 
//// You should have received a copy of the GNU Lesser General    ////
1045 
//// Public License along with this source; if not, download it   ////
1046 
//// from http://www.opencores.org/lgpl.shtml                     ////
1047 
////                                                              ////
1048 
//////////////////////////////////////////////////////////////////////
1049 
// GRAY counter
1050 
module cnt_gray ( q, rst, clk);
1051 
   parameter length = 4;
1052 
   output reg [length:1] q;
1053 
   input rst;
1054 
   input clk;
1055 
   parameter clear_value = 0;
1056 
   parameter set_value = 1;
1057 
   parameter wrap_value = 8;
1058 
   parameter level1_value = 15;
1059 
   reg  [length:1] qi;
1060 
   wire [length:1] q_next;
1061 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1062 
   always @ (posedge clk or posedge rst)
1063 
     if (rst)
1064 
       qi <= {length{1'b0}};
1065 
     else
1066 
       qi <= q_next;
1067 
   always @ (posedge clk or posedge rst)
1068 
     if (rst)
1069 
       q <= {length{1'b0}};
1070 
     else
1071 
         q <= (q_next>>1) ^ q_next;
1072 
endmodule
1073 
//////////////////////////////////////////////////////////////////////
1074 
////                                                              ////
1075 
////  Versatile counter                                           ////
1076 
////                                                              ////
1077 
////  Description                                                 ////
1078 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1079 
////  counter                                                     ////
1080 
////                                                              ////
1081 
////  To Do:                                                      ////
1082 
////   - add LFSR with more taps                                  ////
1083 
////                                                              ////
1084 
////  Author(s):                                                  ////
1085 
////      - Michael Unneback, unneback@opencores.org              ////
1086 
////        ORSoC AB                                              ////
1087 
////                                                              ////
1088 
//////////////////////////////////////////////////////////////////////
1089 
////                                                              ////
1090 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1091 
////                                                              ////
1092 
//// This source file may be used and distributed without         ////
1093 
//// restriction provided that this copyright statement is not    ////
1094 
//// removed from the file and that any derivative work contains  ////
1095 
//// the original copyright notice and the associated disclaimer. ////
1096 
////                                                              ////
1097 
//// This source file is free software; you can redistribute it   ////
1098 
//// and/or modify it under the terms of the GNU Lesser General   ////
1099 
//// Public License as published by the Free Software Foundation; ////
1100 
//// either version 2.1 of the License, or (at your option) any   ////
1101 
//// later version.                                               ////
1102 
////                                                              ////
1103 
//// This source is distributed in the hope that it will be       ////
1104 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1105 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1106 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1107 
//// details.                                                     ////
1108 
////                                                              ////
1109 
//// You should have received a copy of the GNU Lesser General    ////
1110 
//// Public License along with this source; if not, download it   ////
1111 
//// from http://www.opencores.org/lgpl.shtml                     ////
1112 
////                                                              ////
1113 
//////////////////////////////////////////////////////////////////////
1114 
// GRAY counter
1115 
module cnt_gray_ce ( cke, q, rst, clk);
1116 
   parameter length = 4;
1117 
   input cke;
1118 
   output reg [length:1] q;
1119 
   input rst;
1120 
   input clk;
1121 
   parameter clear_value = 0;
1122 
   parameter set_value = 1;
1123 
   parameter wrap_value = 8;
1124 
   parameter level1_value = 15;
1125 
   reg  [length:1] qi;
1126 
   wire [length:1] q_next;
1127 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1128 
   always @ (posedge clk or posedge rst)
1129 
     if (rst)
1130 
       qi <= {length{1'b0}};
1131 
     else
1132 
     if (cke)
1133 
       qi <= q_next;
1134 
   always @ (posedge clk or posedge rst)
1135 
     if (rst)
1136 
       q <= {length{1'b0}};
1137 
     else
1138 
       if (cke)
1139 
         q <= (q_next>>1) ^ q_next;
1140 
endmodule
1141 
//////////////////////////////////////////////////////////////////////
1142 
////                                                              ////
1143 
////  Versatile counter                                           ////
1144 
////                                                              ////
1145 
////  Description                                                 ////
1146 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1147 
////  counter                                                     ////
1148 
////                                                              ////
1149 
////  To Do:                                                      ////
1150 
////   - add LFSR with more taps                                  ////
1151 
////                                                              ////
1152 
////  Author(s):                                                  ////
1153 
////      - Michael Unneback, unneback@opencores.org              ////
1154 
////        ORSoC AB                                              ////
1155 
////                                                              ////
1156 
//////////////////////////////////////////////////////////////////////
1157 
////                                                              ////
1158 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1159 
////                                                              ////
1160 
//// This source file may be used and distributed without         ////
1161 
//// restriction provided that this copyright statement is not    ////
1162 
//// removed from the file and that any derivative work contains  ////
1163 
//// the original copyright notice and the associated disclaimer. ////
1164 
////                                                              ////
1165 
//// This source file is free software; you can redistribute it   ////
1166 
//// and/or modify it under the terms of the GNU Lesser General   ////
1167 
//// Public License as published by the Free Software Foundation; ////
1168 
//// either version 2.1 of the License, or (at your option) any   ////
1169 
//// later version.                                               ////
1170 
////                                                              ////
1171 
//// This source is distributed in the hope that it will be       ////
1172 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1173 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1174 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1175 
//// details.                                                     ////
1176 
////                                                              ////
1177 
//// You should have received a copy of the GNU Lesser General    ////
1178 
//// Public License along with this source; if not, download it   ////
1179 
//// from http://www.opencores.org/lgpl.shtml                     ////
1180 
////                                                              ////
1181 
//////////////////////////////////////////////////////////////////////
1182 
// GRAY counter
1183 
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1184 
   parameter length = 4;
1185 
   input cke;
1186 
   output reg [length:1] q;
1187 
   output [length:1] q_bin;
1188 
   input rst;
1189 
   input clk;
1190 
   parameter clear_value = 0;
1191 
   parameter set_value = 1;
1192 
   parameter wrap_value = 8;
1193 
   parameter level1_value = 15;
1194 
   reg  [length:1] qi;
1195 
   wire [length:1] q_next;
1196 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1197 
   always @ (posedge clk or posedge rst)
1198 
     if (rst)
1199 
       qi <= {length{1'b0}};
1200 
     else
1201 
     if (cke)
1202 
       qi <= q_next;
1203 
   always @ (posedge clk or posedge rst)
1204 
     if (rst)
1205 
       q <= {length{1'b0}};
1206 
     else
1207 
       if (cke)
1208 
         q <= (q_next>>1) ^ q_next;
1209 
   assign q_bin = qi;
1210 
endmodule
1211 
//////////////////////////////////////////////////////////////////////
1212 
////                                                              ////
1213 
////  Versatile library, counters                                 ////
1214 
////                                                              ////
1215 
////  Description                                                 ////
1216 
////  counters                                                    ////
1217 
////                                                              ////
1218 
////                                                              ////
1219 
////  To Do:                                                      ////
1220 
////   - add more counters                                        ////
1221 
////                                                              ////
1222 
////  Author(s):                                                  ////
1223 
////      - Michael Unneback, unneback@opencores.org              ////
1224 
////        ORSoC AB                                              ////
1225 
////                                                              ////
1226 
//////////////////////////////////////////////////////////////////////
1227 
////                                                              ////
1228 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1229 
////                                                              ////
1230 
//// This source file may be used and distributed without         ////
1231 
//// restriction provided that this copyright statement is not    ////
1232 
//// removed from the file and that any derivative work contains  ////
1233 
//// the original copyright notice and the associated disclaimer. ////
1234 
////                                                              ////
1235 
//// This source file is free software; you can redistribute it   ////
1236 
//// and/or modify it under the terms of the GNU Lesser General   ////
1237 
//// Public License as published by the Free Software Foundation; ////
1238 
//// either version 2.1 of the License, or (at your option) any   ////
1239 
//// later version.                                               ////
1240 
////                                                              ////
1241 
//// This source is distributed in the hope that it will be       ////
1242 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1243 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1244 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1245 
//// details.                                                     ////
1246 
////                                                              ////
1247 
//// You should have received a copy of the GNU Lesser General    ////
1248 
//// Public License along with this source; if not, download it   ////
1249 
//// from http://www.opencores.org/lgpl.shtml                     ////
1250 
////                                                              ////
1251 
//////////////////////////////////////////////////////////////////////
1252 
module cnt_shreg_wrap ( q, rst, clk);
1253 
   parameter length = 4;
1254 
   output reg [0:length-1] q;
1255 
   input rst;
1256 
   input clk;
1257 
    always @ (posedge clk or posedge rst)
1258 
    if (rst)
1259 
        q <= {1'b1,{length-1{1'b0}}};
1260 
    else
1261 
        q <= {q[length-1],q[0:length-2]};
1262 
endmodule
1263 
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1264 
   parameter length = 4;
1265 
   input cke;
1266 
   output reg [0:length-1] q;
1267 
   input rst;
1268 
   input clk;
1269 
    always @ (posedge clk or posedge rst)
1270 
    if (rst)
1271 
        q <= {1'b1,{length-1{1'b0}}};
1272 
    else
1273 
        if (cke)
1274 
            q <= {q[length-1],q[0:length-2]};
1275 
endmodule
1276 
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1277 
   parameter length = 4;
1278 
   input cke, clear;
1279 
   output reg [0:length-1] q;
1280 
   input rst;
1281 
   input clk;
1282 
    always @ (posedge clk or posedge rst)
1283 
    if (rst)
1284 
        q <= {1'b1,{length-1{1'b0}}};
1285 
    else
1286 
        if (cke)
1287 
            if (clear)
1288 
                q <= {1'b1,{length-1{1'b0}}};
1289 
            else
1290 
                q <= q >> 1;
1291 
endmodule
1292 
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1293 
   parameter length = 4;
1294 
   input cke, clear;
1295 
   output reg [0:length-1] q;
1296 
   input rst;
1297 
   input clk;
1298 
    always @ (posedge clk or posedge rst)
1299 
    if (rst)
1300 
        q <= {1'b1,{length-1{1'b0}}};
1301 
    else
1302 
        if (cke)
1303 
            if (clear)
1304 
                q <= {1'b1,{length-1{1'b0}}};
1305 
            else
1306 
            q <= {q[length-1],q[0:length-2]};
1307 
endmodule
1308 
//////////////////////////////////////////////////////////////////////
1309 
////                                                              ////
1310 
////  Versatile library, memories                                 ////
1311 
////                                                              ////
1312 
////  Description                                                 ////
1313 
////  memories                                                    ////
1314 
////                                                              ////
1315 
////                                                              ////
1316 
////  To Do:                                                      ////
1317 
////   - add more memory types                                    ////
1318 
////                                                              ////
1319 
////  Author(s):                                                  ////
1320 
////      - Michael Unneback, unneback@opencores.org              ////
1321 
////        ORSoC AB                                              ////
1322 
////                                                              ////
1323 
//////////////////////////////////////////////////////////////////////
1324 
////                                                              ////
1325 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1326 
////                                                              ////
1327 
//// This source file may be used and distributed without         ////
1328 
//// restriction provided that this copyright statement is not    ////
1329 
//// removed from the file and that any derivative work contains  ////
1330 
//// the original copyright notice and the associated disclaimer. ////
1331 
////                                                              ////
1332 
//// This source file is free software; you can redistribute it   ////
1333 
//// and/or modify it under the terms of the GNU Lesser General   ////
1334 
//// Public License as published by the Free Software Foundation; ////
1335 
//// either version 2.1 of the License, or (at your option) any   ////
1336 
//// later version.                                               ////
1337 
////                                                              ////
1338 
//// This source is distributed in the hope that it will be       ////
1339 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1340 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1341 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1342 
//// details.                                                     ////
1343 
////                                                              ////
1344 
//// You should have received a copy of the GNU Lesser General    ////
1345 
//// Public License along with this source; if not, download it   ////
1346 
//// from http://www.opencores.org/lgpl.shtml                     ////
1347 
////                                                              ////
1348 
//////////////////////////////////////////////////////////////////////
1349 
/// ROM
1350 7 unneback 
module vl_rom_init ( adr, q, clk);
1351 
   parameter data_width = 32;
1352 
   parameter addr_width = 8;
1353 
   input [(addr_width-1):0]       adr;
1354 
   output reg [(data_width-1):0] q;
1355 
   input                         clk;
1356 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1357 
   parameter memory_file = "vl_rom.vmem";
1358 
   initial
1359 
     begin
1360 
        $readmemh(memory_file, rom);
1361 
     end
1362 
   always @ (posedge clk)
1363 
     q <= rom[adr];
1364 
endmodule
1365 14 unneback 
/*
1366 7 unneback 
module vl_rom ( adr, q, clk);
1367 6 unneback 
parameter data_width = 32;
1368 
parameter addr_width = 4;
1369 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1370 
    {32'h18000000},
1371 
    {32'hA8200000},
1372 
    {32'hA8200000},
1373 
    {32'hA8200000},
1374 
    {32'h44003000},
1375 
    {32'h15000000},
1376 
    {32'h15000000},
1377 
    {32'h15000000},
1378 
    {32'h15000000},
1379 
    {32'h15000000},
1380 
    {32'h15000000},
1381 
    {32'h15000000},
1382 
    {32'h15000000},
1383 
    {32'h15000000},
1384 
    {32'h15000000},
1385 
    {32'h15000000}};
1386 7 unneback 
input [addr_width-1:0] adr;
1387 6 unneback 
output reg [data_width-1:0] q;
1388 
input clk;
1389 
always @ (posedge clk)
1390 7 unneback 
    q <= data[adr];
1391 6 unneback 
endmodule
1392 14 unneback 
*/
1393 6 unneback 
// Single port RAM
1394 
module vl_ram ( d, adr, we, q, clk);
1395 
   parameter data_width = 32;
1396 
   parameter addr_width = 8;
1397 
   input [(data_width-1):0]      d;
1398 
   input [(addr_width-1):0]       adr;
1399 
   input                         we;
1400 7 unneback 
   output reg [(data_width-1):0] q;
1401 6 unneback 
   input                         clk;
1402 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1403 7 unneback 
   parameter init = 0;
1404 
   parameter memory_file = "vl_ram.vmem";
1405 
   generate if (init) begin : init_mem
1406 
   initial
1407 
     begin
1408 
        $readmemh(memory_file, ram);
1409 
     end
1410 
   end
1411 
   endgenerate
1412 6 unneback 
   always @ (posedge clk)
1413 
   begin
1414 
   if (we)
1415 
     ram[adr] <= d;
1416 
   q <= ram[adr];
1417 
   end
1418 
endmodule
1419 7 unneback 
module vl_ram_be ( d, adr, be, we, q, clk);
1420 
   parameter data_width = 32;
1421 
   parameter addr_width = 8;
1422 
   input [(data_width-1):0]      d;
1423 
   input [(addr_width-1):0]       adr;
1424 
   input [(addr_width/4)-1:0]    be;
1425 
   input                         we;
1426 
   output reg [(data_width-1):0] q;
1427 
   input                         clk;
1428 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1429 
   parameter init = 0;
1430 
   parameter memory_file = "vl_ram.vmem";
1431 
   generate if (init) begin : init_mem
1432 
   initial
1433 
     begin
1434 
        $readmemh(memory_file, ram);
1435 
     end
1436 
   end
1437 
   endgenerate
1438 
   genvar i;
1439 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1440 
      always @ (posedge clk)
1441 
      if (we & be[i])
1442 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1443 
   end
1444 
   endgenerate
1445 
   always @ (posedge clk)
1446 
      q <= ram[adr];
1447 
endmodule
1448 6 unneback 
// Dual port RAM
1449 
// ACTEL FPGA should not use logic to handle rw collision
1450 7 unneback 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1451 6 unneback 
   parameter data_width = 32;
1452 
   parameter addr_width = 8;
1453 
   input [(data_width-1):0]      d_a;
1454 
   input [(addr_width-1):0]       adr_a;
1455 
   input [(addr_width-1):0]       adr_b;
1456 
   input                         we_a;
1457 
   output [(data_width-1):0]      q_b;
1458 
   input                         clk_a, clk_b;
1459 
   reg [(addr_width-1):0]         adr_b_reg;
1460 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1461 7 unneback 
   parameter init = 0;
1462 
   parameter memory_file = "vl_ram.vmem";
1463 
   generate if (init) begin : init_mem
1464 
   initial
1465 
     begin
1466 
        $readmemh(memory_file, ram);
1467 
     end
1468 
   end
1469 
   endgenerate
1470 6 unneback 
   always @ (posedge clk_a)
1471 
   if (we_a)
1472 
     ram[adr_a] <= d_a;
1473 
   always @ (posedge clk_b)
1474 
   adr_b_reg <= adr_b;
1475 
   assign q_b = ram[adr_b_reg];
1476 
endmodule
1477 7 unneback 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1478 6 unneback 
   parameter data_width = 32;
1479 
   parameter addr_width = 8;
1480 
   input [(data_width-1):0]      d_a;
1481 
   input [(addr_width-1):0]       adr_a;
1482 
   input [(addr_width-1):0]       adr_b;
1483 
   input                         we_a;
1484 
   output [(data_width-1):0]      q_b;
1485 
   output reg [(data_width-1):0] q_a;
1486 
   input                         clk_a, clk_b;
1487 
   reg [(data_width-1):0]         q_b;
1488 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1489 7 unneback 
   parameter init = 0;
1490 
   parameter memory_file = "vl_ram.vmem";
1491 
   generate if (init) begin : init_mem
1492 
   initial
1493 
     begin
1494 
        $readmemh(memory_file, ram);
1495 
     end
1496 
   end
1497 
   endgenerate
1498 6 unneback 
   always @ (posedge clk_a)
1499 
     begin
1500 
        q_a <= ram[adr_a];
1501 
        if (we_a)
1502 
             ram[adr_a] <= d_a;
1503 
     end
1504 
   always @ (posedge clk_b)
1505 
          q_b <= ram[adr_b];
1506 
endmodule
1507 7 unneback 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1508 6 unneback 
   parameter data_width = 32;
1509 
   parameter addr_width = 8;
1510 
   input [(data_width-1):0]      d_a;
1511 
   input [(addr_width-1):0]       adr_a;
1512 
   input [(addr_width-1):0]       adr_b;
1513 
   input                         we_a;
1514 
   output [(data_width-1):0]      q_b;
1515 
   input [(data_width-1):0]       d_b;
1516 
   output reg [(data_width-1):0] q_a;
1517 
   input                         we_b;
1518 
   input                         clk_a, clk_b;
1519 
   reg [(data_width-1):0]         q_b;
1520 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1521 7 unneback 
   parameter init = 0;
1522 
   parameter memory_file = "vl_ram.vmem";
1523 
   generate if (init) begin : init_mem
1524 
   initial
1525 
     begin
1526 
        $readmemh(memory_file, ram);
1527 
     end
1528 
   end
1529 
   endgenerate
1530 6 unneback 
   always @ (posedge clk_a)
1531 
     begin
1532 
        q_a <= ram[adr_a];
1533 
        if (we_a)
1534 
             ram[adr_a] <= d_a;
1535 
     end
1536 
   always @ (posedge clk_b)
1537 
     begin
1538 
        q_b <= ram[adr_b];
1539 
        if (we_b)
1540 
          ram[adr_b] <= d_b;
1541 
     end
1542 
endmodule
1543 
// Content addresable memory, CAM
1544 
// FIFO
1545 
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1546 11 unneback 
   parameter addr_width = 4;
1547 
   parameter N = addr_width-1;
1548 6 unneback 
   parameter Q1 = 2'b00;
1549 
   parameter Q2 = 2'b01;
1550 
   parameter Q3 = 2'b11;
1551 
   parameter Q4 = 2'b10;
1552 
   parameter going_empty = 1'b0;
1553 
   parameter going_full  = 1'b1;
1554 
   input [N:0]  wptr, rptr;
1555 14 unneback 
   output       fifo_empty;
1556 6 unneback 
   output       fifo_full;
1557 
   input        wclk, rclk, rst;
1558 
   wire direction;
1559 
   reg  direction_set, direction_clr;
1560 
   wire async_empty, async_full;
1561 
   wire fifo_full2;
1562 14 unneback 
   wire fifo_empty2;
1563 6 unneback 
   // direction_set
1564 
   always @ (wptr[N:N-1] or rptr[N:N-1])
1565 
     case ({wptr[N:N-1],rptr[N:N-1]})
1566 
       {Q1,Q2} : direction_set <= 1'b1;
1567 
       {Q2,Q3} : direction_set <= 1'b1;
1568 
       {Q3,Q4} : direction_set <= 1'b1;
1569 
       {Q4,Q1} : direction_set <= 1'b1;
1570 
       default : direction_set <= 1'b0;
1571 
     endcase
1572 
   // direction_clear
1573 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1574 
     if (rst)
1575 
       direction_clr <= 1'b1;
1576 
     else
1577 
       case ({wptr[N:N-1],rptr[N:N-1]})
1578 
         {Q2,Q1} : direction_clr <= 1'b1;
1579 
         {Q3,Q2} : direction_clr <= 1'b1;
1580 
         {Q4,Q3} : direction_clr <= 1'b1;
1581 
         {Q1,Q4} : direction_clr <= 1'b1;
1582 
         default : direction_clr <= 1'b0;
1583 
       endcase
1584 
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1585 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1586 
   assign async_full  = (wptr == rptr) && (direction==going_full);
1587 
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1588 
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1589 
/*
1590 
   always @ (posedge wclk or posedge rst or posedge async_full)
1591 
     if (rst)
1592 
       {fifo_full, fifo_full2} <= 2'b00;
1593 
     else if (async_full)
1594 
       {fifo_full, fifo_full2} <= 2'b11;
1595 
     else
1596 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1597 
*/
1598 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
1599 6 unneback 
     if (async_empty)
1600 
       {fifo_empty, fifo_empty2} <= 2'b11;
1601 
     else
1602 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1603 
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1604 
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1605 6 unneback 
endmodule // async_comp
1606 
module vl_fifo_1r1w_async (
1607 
    d, wr, fifo_full, wr_clk, wr_rst,
1608 
    q, rd, fifo_empty, rd_clk, rd_rst
1609 
    );
1610 
parameter data_width = 18;
1611 
parameter addr_width = 4;
1612 
// write side
1613 
input  [data_width-1:0] d;
1614 
input                   wr;
1615 
output                  fifo_full;
1616 
input                   wr_clk;
1617 
input                   wr_rst;
1618 
// read side
1619 
output [data_width-1:0] q;
1620 
input                   rd;
1621 
output                  fifo_empty;
1622 
input                   rd_clk;
1623 
input                   rd_rst;
1624 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1625 
vl_fifo_1r1w_async (
1626 
    d, wr, fifo_full, wr_clk, wr_rst,
1627 
    q, rd, fifo_empty, rd_clk, rd_rst
1628 
    );
1629 7 unneback 
cnt_gray_ce_bin
1630 6 unneback 
    # ( .length(addr_width))
1631 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1632 7 unneback 
cnt_gray_ce_bin
1633 6 unneback 
    # (.length(addr_width))
1634 
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1635 7 unneback 
vl_dpram_1r1w
1636 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
1637 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1638 
vl_fifo_cmp_async
1639 
    # (.addr_width(addr_width))
1640 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1641 
endmodule
1642 8 unneback 
module vl_fifo_2r2w_async (
1643 6 unneback 
    // a side
1644 
    a_d, a_wr, a_fifo_full,
1645 
    a_q, a_rd, a_fifo_empty,
1646 
    a_clk, a_rst,
1647 
    // b side
1648 
    b_d, b_wr, b_fifo_full,
1649 
    b_q, b_rd, b_fifo_empty,
1650 
    b_clk, b_rst
1651 
    );
1652 
parameter data_width = 18;
1653 
parameter addr_width = 4;
1654 
// a side
1655 
input  [data_width-1:0] a_d;
1656 
input                   a_wr;
1657 
output                  a_fifo_full;
1658 
output [data_width-1:0] a_q;
1659 
input                   a_rd;
1660 
output                  a_fifo_empty;
1661 
input                   a_clk;
1662 
input                   a_rst;
1663 
// b side
1664 
input  [data_width-1:0] b_d;
1665 
input                   b_wr;
1666 
output                  b_fifo_full;
1667 
output [data_width-1:0] b_q;
1668 
input                   b_rd;
1669 
output                  b_fifo_empty;
1670 
input                   b_clk;
1671 
input                   b_rst;
1672 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1673 
vl_fifo_1r1w_async_a (
1674 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1675 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1676 
    );
1677 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1678 
vl_fifo_1r1w_async_b (
1679 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1680 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1681 
    );
1682 
endmodule
1683 8 unneback 
module vl_fifo_2r2w_async_simplex (
1684 6 unneback 
    // a side
1685 
    a_d, a_wr, a_fifo_full,
1686 
    a_q, a_rd, a_fifo_empty,
1687 
    a_clk, a_rst,
1688 
    // b side
1689 
    b_d, b_wr, b_fifo_full,
1690 
    b_q, b_rd, b_fifo_empty,
1691 
    b_clk, b_rst
1692 
    );
1693 
parameter data_width = 18;
1694 
parameter addr_width = 4;
1695 
// a side
1696 
input  [data_width-1:0] a_d;
1697 
input                   a_wr;
1698 
output                  a_fifo_full;
1699 
output [data_width-1:0] a_q;
1700 
input                   a_rd;
1701 
output                  a_fifo_empty;
1702 
input                   a_clk;
1703 
input                   a_rst;
1704 
// b side
1705 
input  [data_width-1:0] b_d;
1706 
input                   b_wr;
1707 
output                  b_fifo_full;
1708 
output [data_width-1:0] b_q;
1709 
input                   b_rd;
1710 
output                  b_fifo_empty;
1711 
input                   b_clk;
1712 
input                   b_rst;
1713 
// adr_gen
1714 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1715 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1716 
// dpram
1717 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1718 7 unneback 
cnt_gray_ce_bin
1719 6 unneback 
    # ( .length(addr_width))
1720 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1721 7 unneback 
cnt_gray_ce_bin
1722 6 unneback 
    # (.length(addr_width))
1723 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1724 7 unneback 
cnt_gray_ce_bin
1725 6 unneback 
    # ( .length(addr_width))
1726 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1727 7 unneback 
cnt_gray_ce_bin
1728 6 unneback 
    # (.length(addr_width))
1729 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1730 
// mux read or write adr to DPRAM
1731 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1732 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1733 11 unneback 
vl_dpram_2r2w
1734 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
1735 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1736 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1737 11 unneback 
vl_fifo_cmp_async
1738 6 unneback 
    # (.addr_width(addr_width))
1739 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1740 11 unneback 
vl_fifo_cmp_async
1741 6 unneback 
    # (.addr_width(addr_width))
1742 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1743 
endmodule
1744 12 unneback 
//////////////////////////////////////////////////////////////////////
1745 
////                                                              ////
1746 
////  Versatile library, wishbone stuff                           ////
1747 
////                                                              ////
1748 
////  Description                                                 ////
1749 
////  Wishbone compliant modules                                  ////
1750 
////                                                              ////
1751 
////                                                              ////
1752 
////  To Do:                                                      ////
1753 
////   -                                                          ////
1754 
////                                                              ////
1755 
////  Author(s):                                                  ////
1756 
////      - Michael Unneback, unneback@opencores.org              ////
1757 
////        ORSoC AB                                              ////
1758 
////                                                              ////
1759 
//////////////////////////////////////////////////////////////////////
1760 
////                                                              ////
1761 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1762 
////                                                              ////
1763 
//// This source file may be used and distributed without         ////
1764 
//// restriction provided that this copyright statement is not    ////
1765 
//// removed from the file and that any derivative work contains  ////
1766 
//// the original copyright notice and the associated disclaimer. ////
1767 
////                                                              ////
1768 
//// This source file is free software; you can redistribute it   ////
1769 
//// and/or modify it under the terms of the GNU Lesser General   ////
1770 
//// Public License as published by the Free Software Foundation; ////
1771 
//// either version 2.1 of the License, or (at your option) any   ////
1772 
//// later version.                                               ////
1773 
////                                                              ////
1774 
//// This source is distributed in the hope that it will be       ////
1775 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1776 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1777 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1778 
//// details.                                                     ////
1779 
////                                                              ////
1780 
//// You should have received a copy of the GNU Lesser General    ////
1781 
//// Public License along with this source; if not, download it   ////
1782 
//// from http://www.opencores.org/lgpl.shtml                     ////
1783 
////                                                              ////
1784 
//////////////////////////////////////////////////////////////////////
1785 
// async wb3 - wb3 bridge
1786 
`timescale 1ns/1ns
1787 
module wb3wb3_bridge (
1788 
        // wishbone slave side
1789 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1790 
        // wishbone master side
1791 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1792 
input [31:0] wbs_dat_i;
1793 
input [31:2] wbs_adr_i;
1794 
input [3:0]  wbs_sel_i;
1795 
input [1:0]  wbs_bte_i;
1796 
input [2:0]  wbs_cti_i;
1797 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1798 
output [31:0] wbs_dat_o;
1799 14 unneback 
output wbs_ack_o;
1800 12 unneback 
input wbs_clk, wbs_rst;
1801 
output [31:0] wbm_dat_o;
1802 
output reg [31:2] wbm_adr_o;
1803 
output [3:0]  wbm_sel_o;
1804 
output reg [1:0]  wbm_bte_o;
1805 
output reg [2:0]  wbm_cti_o;
1806 14 unneback 
output reg wbm_we_o;
1807 
output wbm_cyc_o;
1808 12 unneback 
output wbm_stb_o;
1809 
input [31:0]  wbm_dat_i;
1810 
input wbm_ack_i;
1811 
input wbm_clk, wbm_rst;
1812 
parameter addr_width = 4;
1813 
// bte
1814 
parameter linear       = 2'b00;
1815 
parameter wrap4        = 2'b01;
1816 
parameter wrap8        = 2'b10;
1817 
parameter wrap16       = 2'b11;
1818 
// cti
1819 
parameter classic      = 3'b000;
1820 
parameter incburst     = 3'b010;
1821 
parameter endofburst   = 3'b111;
1822 
parameter wbs_adr  = 1'b0;
1823 
parameter wbs_data = 1'b1;
1824 
parameter wbm_adr0 = 2'b00;
1825 
parameter wbm_adr1 = 2'b01;
1826 
parameter wbm_data = 2'b10;
1827 
reg [1:0] wbs_bte_reg;
1828 
reg wbs;
1829 
wire wbs_eoc_alert, wbm_eoc_alert;
1830 
reg wbs_eoc, wbm_eoc;
1831 
reg [1:0] wbm;
1832 14 unneback 
wire [1:16] wbs_count, wbm_count;
1833 12 unneback 
wire [35:0] a_d, a_q, b_d, b_q;
1834 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1835 
reg a_rd_reg;
1836 
wire b_rd_adr, b_rd_data;
1837 14 unneback 
wire b_rd_data_reg;
1838 
wire [35:0] temp;
1839 12 unneback 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1840 
always @ (posedge wbs_clk or posedge wbs_rst)
1841 
if (wbs_rst)
1842 
        wbs_eoc <= 1'b0;
1843 
else
1844 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1845 
                wbs_eoc <= wbs_bte_i==linear;
1846 
        else if (wbs_eoc_alert & (a_rd | a_wr))
1847 
                wbs_eoc <= 1'b1;
1848 
cnt_shreg_ce_clear # ( .length(16))
1849 
    cnt0 (
1850 
        .cke(wbs_ack_o),
1851 
        .clear(wbs_eoc),
1852 
        .q(wbs_count),
1853 
        .rst(wbs_rst),
1854 
        .clk(wbs_clk));
1855 
always @ (posedge wbs_clk or posedge wbs_rst)
1856 
if (wbs_rst)
1857 
        wbs <= wbs_adr;
1858 
else
1859 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1860 
                wbs <= wbs_data;
1861 
        else if (wbs_eoc & wbs_ack_o)
1862 
                wbs <= wbs_adr;
1863 
// wbs FIFO
1864 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1865 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1866 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1867 
              1'b0;
1868 
assign a_rd = !a_fifo_empty;
1869 
always @ (posedge wbs_clk or posedge wbs_rst)
1870 
if (wbs_rst)
1871 
        a_rd_reg <= 1'b0;
1872 
else
1873 
        a_rd_reg <= a_rd;
1874 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1875 
assign wbs_dat_o = a_q[35:4];
1876 
always @ (posedge wbs_clk or posedge wbs_rst)
1877 
if (wbs_rst)
1878 13 unneback 
        wbs_bte_reg <= 2'b00;
1879 12 unneback 
else
1880 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
1881 12 unneback 
// wbm FIFO
1882 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1883 
always @ (posedge wbm_clk or posedge wbm_rst)
1884 
if (wbm_rst)
1885 
        wbm_eoc <= 1'b0;
1886 
else
1887 
        if (wbm==wbm_adr0 & !b_fifo_empty)
1888 
                wbm_eoc <= b_q[4:3] == linear;
1889 
        else if (wbm_eoc_alert & wbm_ack_i)
1890 
                wbm_eoc <= 1'b1;
1891 
always @ (posedge wbm_clk or posedge wbm_rst)
1892 
if (wbm_rst)
1893 
        wbm <= wbm_adr0;
1894 
else
1895 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1896 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1897 
        (wbm==wbm_adr1 & !wbm_we_o) |
1898 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1899 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1900 
assign b_d = {wbm_dat_i,4'b1111};
1901 
assign b_wr = !wbm_we_o & wbm_ack_i;
1902 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1903 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1904 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1905 
                   1'b0;
1906 
assign b_rd = b_rd_adr | b_rd_data;
1907 
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1908 
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1909 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1910 
cnt_shreg_ce_clear # ( .length(16))
1911 
    cnt1 (
1912 
        .cke(wbm_ack_i),
1913 
        .clear(wbm_eoc),
1914 
        .q(wbm_count),
1915 
        .rst(wbm_rst),
1916 
        .clk(wbm_clk));
1917 
assign wbm_cyc_o = wbm==wbm_data;
1918 
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
1919 
                   (wbm==wbm_data) ? 1'b1 :
1920 
                   1'b0;
1921 
always @ (posedge wbm_clk or posedge wbm_rst)
1922 
if (wbm_rst)
1923 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1924 
else begin
1925 
        if (wbm==wbm_adr0 & !b_fifo_empty)
1926 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1927 
        else if (wbm_eoc_alert & wbm_ack_i)
1928 
                wbm_cti_o <= endofburst;
1929 
end
1930 
//async_fifo_dw_simplex_top
1931 
vl_fifo_2r2w_async_simplex
1932 
# ( .data_width(36), .addr_width(addr_width))
1933 
fifo (
1934 
    // a side
1935 
    .a_d(a_d),
1936 
    .a_wr(a_wr),
1937 
    .a_fifo_full(a_fifo_full),
1938 
    .a_q(a_q),
1939 
    .a_rd(a_rd),
1940 
    .a_fifo_empty(a_fifo_empty),
1941 
    .a_clk(wbs_clk),
1942 
    .a_rst(wbs_rst),
1943 
    // b side
1944 
    .b_d(b_d),
1945 
    .b_wr(b_wr),
1946 
    .b_fifo_full(b_fifo_full),
1947 
    .b_q(b_q),
1948 
    .b_rd(b_rd),
1949 
    .b_fifo_empty(b_fifo_empty),
1950 
    .b_clk(wbm_clk),
1951 
    .b_rst(wbm_rst)
1952 
    );
1953 
endmodule
1954 17 unneback 
// WB ROM
1955 
module wb_boot_rom (
1956 
    wb_adr_i, wb_stb_i, wb_cyc_i,
1957 
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
1958 
`ifndef BOOT_ROM
1959 
`define BOOT_ROM "boot_rom.v"
1960 
`endif
1961 
    parameter addr_width = 5;
1962 
   input [(addr_width+2)-1:2]       wb_adr_i;
1963 
   input                            wb_stb_i;
1964 
   input                            wb_cyc_i;
1965 
   output reg [31:0]                 wb_dat_o;
1966 
   output reg                       wb_ack_o;
1967 
   input                            wb_clk;
1968 
   input                            wb_rst;
1969 
always @ (posedge wb_clk or posedge wb_rst)
1970 
    if (wb_rst)
1971 
        wb_dat_o <= 32'h15000000;
1972 
    else
1973 
         case (wb_adr_i)
1974 
`include `BOOT_ROM
1975 
           /*
1976 
            // Zero r0 and jump to 0x00000100
1977 
 
1978 
            1 : wb_dat_o <= 32'hA8200000;
1979 
            2 : wb_dat_o <= 32'hA8C00100;
1980 
            3 : wb_dat_o <= 32'h44003000;
1981 
            4 : wb_dat_o <= 32'h15000000;
1982 
            */
1983 
           default:
1984 
             wb_dat_o <= 32'h00000000;
1985 
         endcase // case (wb_adr_i)
1986 
always @ (posedge wb_clk or posedge wb_rst)
1987 
    if (wb_rst)
1988 
        wb_ack_o <= 1'b0;
1989 
    else
1990 
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
1991 
endmodule

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