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1 6 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Versatile library, clock and reset                          ////
4 
////                                                              ////
5 
////  Description                                                 ////
6 
////  Logic related to clock and reset                            ////
7 
////                                                              ////
8 
////                                                              ////
9 
////  To Do:                                                      ////
10 
////   - add more different registers                             ////
11 
////                                                              ////
12 
////  Author(s):                                                  ////
13 
////      - Michael Unneback, unneback@opencores.org              ////
14 
////        ORSoC AB                                              ////
15 
////                                                              ////
16 
//////////////////////////////////////////////////////////////////////
17 
////                                                              ////
18 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19 
////                                                              ////
20 
//// This source file may be used and distributed without         ////
21 
//// restriction provided that this copyright statement is not    ////
22 
//// removed from the file and that any derivative work contains  ////
23 
//// the original copyright notice and the associated disclaimer. ////
24 
////                                                              ////
25 
//// This source file is free software; you can redistribute it   ////
26 
//// and/or modify it under the terms of the GNU Lesser General   ////
27 
//// Public License as published by the Free Software Foundation; ////
28 
//// either version 2.1 of the License, or (at your option) any   ////
29 
//// later version.                                               ////
30 
////                                                              ////
31 
//// This source is distributed in the hope that it will be       ////
32 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35 
//// details.                                                     ////
36 
////                                                              ////
37 
//// You should have received a copy of the GNU Lesser General    ////
38 
//// Public License along with this source; if not, download it   ////
39 
//// from http://www.opencores.org/lgpl.shtml                     ////
40 
////                                                              ////
41 
//////////////////////////////////////////////////////////////////////
42 
// Global buffer
43 
// usage:
44 
// use to enable global buffers for high fan out signals such as clock and reset
45 
altera
46 
 // ALTERA
47 
 //ACTEL
48 
// sync reset
49 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback 
// output active high global reset sync with two DFFs
51 
`timescale 1 ns/100 ps
52 
module vl_sync_rst ( rst_n_i, rst_o, clk);
53 
input rst_n_i, clk;
54 
output rst_o;
55 18 unneback 
reg [1:0] tmp;
56 6 unneback 
always @ (posedge clk or negedge rst_n_i)
57 
if (!rst_n_i)
58 17 unneback 
        tmp <= 2'b11;
59 6 unneback 
else
60 17 unneback 
        tmp <= {1'b0,tmp[0]};
61 
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback 
endmodule
63 
// vl_pll
64 
 //altera
65 
 //actel
66 
//////////////////////////////////////////////////////////////////////
67 
////                                                              ////
68 
////  Versatile library, registers                                ////
69 
////                                                              ////
70 
////  Description                                                 ////
71 
////  Different type of registers                                 ////
72 
////                                                              ////
73 
////                                                              ////
74 
////  To Do:                                                      ////
75 
////   - add more different registers                             ////
76 
////                                                              ////
77 
////  Author(s):                                                  ////
78 
////      - Michael Unneback, unneback@opencores.org              ////
79 
////        ORSoC AB                                              ////
80 
////                                                              ////
81 
//////////////////////////////////////////////////////////////////////
82 
////                                                              ////
83 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84 
////                                                              ////
85 
//// This source file may be used and distributed without         ////
86 
//// restriction provided that this copyright statement is not    ////
87 
//// removed from the file and that any derivative work contains  ////
88 
//// the original copyright notice and the associated disclaimer. ////
89 
////                                                              ////
90 
//// This source file is free software; you can redistribute it   ////
91 
//// and/or modify it under the terms of the GNU Lesser General   ////
92 
//// Public License as published by the Free Software Foundation; ////
93 
//// either version 2.1 of the License, or (at your option) any   ////
94 
//// later version.                                               ////
95 
////                                                              ////
96 
//// This source is distributed in the hope that it will be       ////
97 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100 
//// details.                                                     ////
101 
////                                                              ////
102 
//// You should have received a copy of the GNU Lesser General    ////
103 
//// Public License along with this source; if not, download it   ////
104 
//// from http://www.opencores.org/lgpl.shtml                     ////
105 
////                                                              ////
106 
//////////////////////////////////////////////////////////////////////
107 18 unneback 
module vl_dff ( d, q, clk, rst);
108 6 unneback 
        parameter width = 1;
109 
        parameter reset_value = 0;
110 
        input [width-1:0] d;
111 
        input clk, rst;
112 
        output reg [width-1:0] q;
113 
        always @ (posedge clk or posedge rst)
114 
        if (rst)
115 
                q <= reset_value;
116 
        else
117 
                q <= d;
118 
endmodule
119 18 unneback 
module vl_dff_array ( d, q, clk, rst);
120 6 unneback 
        parameter width = 1;
121 
        parameter depth = 2;
122 
        parameter reset_value = 1'b0;
123 
        input [width-1:0] d;
124 
        input clk, rst;
125 
        output [width-1:0] q;
126 
        reg  [0:depth-1] q_tmp [width-1:0];
127 
        integer i;
128 
        always @ (posedge clk or posedge rst)
129 
        if (rst) begin
130 
            for (i=0;i<depth;i=i+1)
131 
                q_tmp[i] <= {width{reset_value}};
132 
        end else begin
133 
            q_tmp[0] <= d;
134 
            for (i=1;i<depth;i=i+1)
135 
                q_tmp[i] <= q_tmp[i-1];
136 
        end
137 
    assign q = q_tmp[depth-1];
138 
endmodule
139 18 unneback 
module vl_dff_ce ( d, ce, q, clk, rst);
140 6 unneback 
        parameter width = 1;
141 
        parameter reset_value = 0;
142 
        input [width-1:0] d;
143 
        input ce, clk, rst;
144 
        output reg [width-1:0] q;
145 
        always @ (posedge clk or posedge rst)
146 
        if (rst)
147 
                q <= reset_value;
148 
        else
149 
                if (ce)
150 
                        q <= d;
151 
endmodule
152 18 unneback 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
153 8 unneback 
        parameter width = 1;
154 
        parameter reset_value = 0;
155 
        input [width-1:0] d;
156 10 unneback 
        input ce, clear, clk, rst;
157 8 unneback 
        output reg [width-1:0] q;
158 
        always @ (posedge clk or posedge rst)
159 
        if (rst)
160 
            q <= reset_value;
161 
        else
162 
            if (ce)
163 
                if (clear)
164 
                    q <= {width{1'b0}};
165 
                else
166 
                    q <= d;
167 
endmodule
168 6 unneback 
// megafunction wizard: %LPM_FF%
169 
// GENERATION: STANDARD
170 
// VERSION: WM1.0
171 
// MODULE: lpm_ff
172 
// ============================================================
173 
// File Name: dff_sr.v
174 
// Megafunction Name(s):
175 
//                      lpm_ff
176 
//
177 
// Simulation Library Files(s):
178 
//                      lpm
179 
// ============================================================
180 
// ************************************************************
181 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
182 
//
183 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
184 
// ************************************************************
185 
//Copyright (C) 1991-2010 Altera Corporation
186 
//Your use of Altera Corporation's design tools, logic functions
187 
//and other software and tools, and its AMPP partner logic
188 
//functions, and any output files from any of the foregoing
189 
//(including device programming or simulation files), and any
190 
//associated documentation or information are expressly subject
191 
//to the terms and conditions of the Altera Program License
192 
//Subscription Agreement, Altera MegaCore Function License
193 
//Agreement, or other applicable license agreement, including,
194 
//without limitation, that your use is for the sole purpose of
195 
//programming logic devices manufactured by Altera and sold by
196 
//Altera or its authorized distributors.  Please refer to the
197 
//applicable agreement for further details.
198 
// synopsys translate_off
199 
`timescale 1 ps / 1 ps
200 
// synopsys translate_on
201 18 unneback 
module vl_dff_sr (
202 6 unneback 
        aclr,
203 
        aset,
204 
        clock,
205 
        data,
206 
        q);
207 
        input     aclr;
208 
        input     aset;
209 
        input     clock;
210 
        input     data;
211 
        output    q;
212 
        wire [0:0] sub_wire0;
213 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
214 
        wire  q = sub_wire1;
215 
        wire  sub_wire2 = data;
216 
        wire  sub_wire3 = sub_wire2;
217 
        lpm_ff  lpm_ff_component (
218 
                                .aclr (aclr),
219 
                                .clock (clock),
220 
                                .data (sub_wire3),
221 
                                .aset (aset),
222 
                                .q (sub_wire0)
223 
                                // synopsys translate_off
224 
                                ,
225 
                                .aload (),
226 
                                .enable (),
227 
                                .sclr (),
228 
                                .sload (),
229 
                                .sset ()
230 
                                // synopsys translate_on
231 
                                );
232 
        defparam
233 
                lpm_ff_component.lpm_fftype = "DFF",
234 
                lpm_ff_component.lpm_type = "LPM_FF",
235 
                lpm_ff_component.lpm_width = 1;
236 
endmodule
237 
// ============================================================
238 
// CNX file retrieval info
239 
// ============================================================
240 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
241 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
242 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
243 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
244 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
245 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
246 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
247 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
248 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
249 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
250 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
251 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
252 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
253 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
254 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
255 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
256 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
257 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
258 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
259 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
260 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
261 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
262 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
263 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
264 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
265 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
266 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
267 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
268 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
269 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
270 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
271 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
272 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
273 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
274 
// Retrieval info: LIB_FILE: lpm
275 
// LATCH
276 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
277 18 unneback 
module vl_latch ( d, le, q, clk);
278 6 unneback 
input d, le;
279 
output q;
280 
input clk;
281 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
282 
endmodule
283 18 unneback 
module vl_shreg ( d, q, clk, rst);
284 17 unneback 
parameter depth = 10;
285 
input d;
286 
output q;
287 
input clk, rst;
288 
reg [1:depth] dffs;
289 
always @ (posedge clk or posedge rst)
290 
if (rst)
291 
    dffs <= {depth{1'b0}};
292 
else
293 
    dffs <= {d,dffs[1:depth-1]};
294 
assign q = dffs[depth];
295 
endmodule
296 18 unneback 
module vl_shreg_ce ( d, ce, q, clk, rst);
297 17 unneback 
parameter depth = 10;
298 
input d, ce;
299 
output q;
300 
input clk, rst;
301 
reg [1:depth] dffs;
302 
always @ (posedge clk or posedge rst)
303 
if (rst)
304 
    dffs <= {depth{1'b0}};
305 
else
306 
    if (ce)
307 
        dffs <= {d,dffs[1:depth-1]};
308 
assign q = dffs[depth];
309 
endmodule
310 18 unneback 
module vl_delay ( d, q, clk, rst);
311 15 unneback 
parameter depth = 10;
312 
input d;
313 
output q;
314 
input clk, rst;
315 
reg [1:depth] dffs;
316 
always @ (posedge clk or posedge rst)
317 
if (rst)
318 
    dffs <= {depth{1'b0}};
319 
else
320 
    dffs <= {d,dffs[1:depth-1]};
321 
assign q = dffs[depth];
322 
endmodule
323 18 unneback 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
324 17 unneback 
parameter depth = 10;
325 
input d;
326 
output q, emptyflag;
327 
input clk, rst;
328 
reg [1:depth] dffs;
329 
always @ (posedge clk or posedge rst)
330 
if (rst)
331 
    dffs <= {depth{1'b0}};
332 
else
333 
    dffs <= {d,dffs[1:depth-1]};
334 
assign q = dffs[depth];
335 
assign emptyflag = !(|dffs);
336 
endmodule
337 6 unneback 
//////////////////////////////////////////////////////////////////////
338 
////                                                              ////
339 18 unneback 
////  Logic functions                                             ////
340 
////                                                              ////
341 
////  Description                                                 ////
342 
////  Logic functions such as multiplexers                        ////
343 
////                                                              ////
344 
////                                                              ////
345 
////  To Do:                                                      ////
346 
////   -                                                          ////
347 
////                                                              ////
348 
////  Author(s):                                                  ////
349 
////      - Michael Unneback, unneback@opencores.org              ////
350 
////        ORSoC AB                                              ////
351 
////                                                              ////
352 
//////////////////////////////////////////////////////////////////////
353 
////                                                              ////
354 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
355 
////                                                              ////
356 
//// This source file may be used and distributed without         ////
357 
//// restriction provided that this copyright statement is not    ////
358 
//// removed from the file and that any derivative work contains  ////
359 
//// the original copyright notice and the associated disclaimer. ////
360 
////                                                              ////
361 
//// This source file is free software; you can redistribute it   ////
362 
//// and/or modify it under the terms of the GNU Lesser General   ////
363 
//// Public License as published by the Free Software Foundation; ////
364 
//// either version 2.1 of the License, or (at your option) any   ////
365 
//// later version.                                               ////
366 
////                                                              ////
367 
//// This source is distributed in the hope that it will be       ////
368 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
369 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
370 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
371 
//// details.                                                     ////
372 
////                                                              ////
373 
//// You should have received a copy of the GNU Lesser General    ////
374 
//// Public License along with this source; if not, download it   ////
375 
//// from http://www.opencores.org/lgpl.shtml                     ////
376 
////                                                              ////
377 
//////////////////////////////////////////////////////////////////////
378 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
379 
parameter width = 32;
380 
parameter nr_of_ports = 4;
381 
input [width-1:0] a3, a2, a1, a0;
382 
input [nr_of_ports-1:0] sel;
383 
output reg [width-1:0] dout;
384 
reg [width-1:0] tmp [nr_of_ports-1:0];
385 
integer i;
386 
// and
387 
assign tmp[0] = {width{sel[0]}} & a0;
388 
assign tmp[1] = {width{sel[1]}} & a1;
389 
assign tmp[2] = {width{sel[2]}} & a2;
390 
assign tmp[3] = {width{sel[3]}} & a3;
391 
// or
392 
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
393 
endmodule
394 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
395 
parameter width = 32;
396 
parameter nr_of_ports = 5;
397 
input [width-1:0] a4, a3, a2, a1, a0;
398 
input [nr_of_ports-1:0] sel;
399 
output reg [width-1:0] dout;
400 
reg [width-1:0] tmp [nr_of_ports-1:0];
401 
integer i;
402 
// and
403 
assign tmp[0] = {width{sel[0]}} & a0;
404 
assign tmp[1] = {width{sel[1]}} & a1;
405 
assign tmp[2] = {width{sel[2]}} & a2;
406 
assign tmp[3] = {width{sel[3]}} & a3;
407 
assign tmp[4] = {width{sel[4]}} & a4;
408 
// or
409 
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
410 
endmodule
411 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
412 
parameter width = 32;
413 
parameter nr_of_ports = 6;
414 
input [width-1:0] a5, a4, a3, a2, a1, a0;
415 
input [nr_of_ports-1:0] sel;
416 
output reg [width-1:0] dout;
417 
reg [width-1:0] tmp [nr_of_ports-1:0];
418 
integer i;
419 
// and
420 
assign tmp[0] = {width{sel[0]}} & a0;
421 
assign tmp[1] = {width{sel[1]}} & a1;
422 
assign tmp[2] = {width{sel[2]}} & a2;
423 
assign tmp[3] = {width{sel[3]}} & a3;
424 
assign tmp[4] = {width{sel[4]}} & a4;
425 
assign tmp[5] = {width{sel[5]}} & a5;
426 
// or
427 
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
428 
endmodule
429 
//////////////////////////////////////////////////////////////////////
430 
////                                                              ////
431 6 unneback 
////  Versatile counter                                           ////
432 
////                                                              ////
433 
////  Description                                                 ////
434 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
435 
////  counter                                                     ////
436 
////                                                              ////
437 
////  To Do:                                                      ////
438 
////   - add LFSR with more taps                                  ////
439 
////                                                              ////
440 
////  Author(s):                                                  ////
441 
////      - Michael Unneback, unneback@opencores.org              ////
442 
////        ORSoC AB                                              ////
443 
////                                                              ////
444 
//////////////////////////////////////////////////////////////////////
445 
////                                                              ////
446 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
447 
////                                                              ////
448 
//// This source file may be used and distributed without         ////
449 
//// restriction provided that this copyright statement is not    ////
450 
//// removed from the file and that any derivative work contains  ////
451 
//// the original copyright notice and the associated disclaimer. ////
452 
////                                                              ////
453 
//// This source file is free software; you can redistribute it   ////
454 
//// and/or modify it under the terms of the GNU Lesser General   ////
455 
//// Public License as published by the Free Software Foundation; ////
456 
//// either version 2.1 of the License, or (at your option) any   ////
457 
//// later version.                                               ////
458 
////                                                              ////
459 
//// This source is distributed in the hope that it will be       ////
460 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
461 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
462 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
463 
//// details.                                                     ////
464 
////                                                              ////
465 
//// You should have received a copy of the GNU Lesser General    ////
466 
//// Public License along with this source; if not, download it   ////
467 
//// from http://www.opencores.org/lgpl.shtml                     ////
468 
////                                                              ////
469 
//////////////////////////////////////////////////////////////////////
470 
// binary counter
471 18 unneback 
module vl_cnt_bin_ce ( cke, q, rst, clk);
472 6 unneback 
   parameter length = 4;
473 
   input cke;
474 
   output [length:1] q;
475 
   input rst;
476 
   input clk;
477 
   parameter clear_value = 0;
478 
   parameter set_value = 1;
479 
   parameter wrap_value = 0;
480 
   parameter level1_value = 15;
481 
   reg  [length:1] qi;
482 
   wire [length:1] q_next;
483 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
484 
   always @ (posedge clk or posedge rst)
485 
     if (rst)
486 
       qi <= {length{1'b0}};
487 
     else
488 
     if (cke)
489 
       qi <= q_next;
490 
   assign q = qi;
491 
endmodule
492 
//////////////////////////////////////////////////////////////////////
493 
////                                                              ////
494 
////  Versatile counter                                           ////
495 
////                                                              ////
496 
////  Description                                                 ////
497 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
498 
////  counter                                                     ////
499 
////                                                              ////
500 
////  To Do:                                                      ////
501 
////   - add LFSR with more taps                                  ////
502 
////                                                              ////
503 
////  Author(s):                                                  ////
504 
////      - Michael Unneback, unneback@opencores.org              ////
505 
////        ORSoC AB                                              ////
506 
////                                                              ////
507 
//////////////////////////////////////////////////////////////////////
508 
////                                                              ////
509 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
510 
////                                                              ////
511 
//// This source file may be used and distributed without         ////
512 
//// restriction provided that this copyright statement is not    ////
513 
//// removed from the file and that any derivative work contains  ////
514 
//// the original copyright notice and the associated disclaimer. ////
515 
////                                                              ////
516 
//// This source file is free software; you can redistribute it   ////
517 
//// and/or modify it under the terms of the GNU Lesser General   ////
518 
//// Public License as published by the Free Software Foundation; ////
519 
//// either version 2.1 of the License, or (at your option) any   ////
520 
//// later version.                                               ////
521 
////                                                              ////
522 
//// This source is distributed in the hope that it will be       ////
523 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
524 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
525 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
526 
//// details.                                                     ////
527 
////                                                              ////
528 
//// You should have received a copy of the GNU Lesser General    ////
529 
//// Public License along with this source; if not, download it   ////
530 
//// from http://www.opencores.org/lgpl.shtml                     ////
531 
////                                                              ////
532 
//////////////////////////////////////////////////////////////////////
533 
// binary counter
534 18 unneback 
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
535 6 unneback 
   parameter length = 4;
536 
   input clear;
537 
   input cke;
538 
   output [length:1] q;
539 
   input rst;
540 
   input clk;
541 
   parameter clear_value = 0;
542 
   parameter set_value = 1;
543 
   parameter wrap_value = 0;
544 
   parameter level1_value = 15;
545 
   reg  [length:1] qi;
546 
   wire [length:1] q_next;
547 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
548 
   always @ (posedge clk or posedge rst)
549 
     if (rst)
550 
       qi <= {length{1'b0}};
551 
     else
552 
     if (cke)
553 
       qi <= q_next;
554 
   assign q = qi;
555 
endmodule
556 
//////////////////////////////////////////////////////////////////////
557 
////                                                              ////
558 
////  Versatile counter                                           ////
559 
////                                                              ////
560 
////  Description                                                 ////
561 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
562 
////  counter                                                     ////
563 
////                                                              ////
564 
////  To Do:                                                      ////
565 
////   - add LFSR with more taps                                  ////
566 
////                                                              ////
567 
////  Author(s):                                                  ////
568 
////      - Michael Unneback, unneback@opencores.org              ////
569 
////        ORSoC AB                                              ////
570 
////                                                              ////
571 
//////////////////////////////////////////////////////////////////////
572 
////                                                              ////
573 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
574 
////                                                              ////
575 
//// This source file may be used and distributed without         ////
576 
//// restriction provided that this copyright statement is not    ////
577 
//// removed from the file and that any derivative work contains  ////
578 
//// the original copyright notice and the associated disclaimer. ////
579 
////                                                              ////
580 
//// This source file is free software; you can redistribute it   ////
581 
//// and/or modify it under the terms of the GNU Lesser General   ////
582 
//// Public License as published by the Free Software Foundation; ////
583 
//// either version 2.1 of the License, or (at your option) any   ////
584 
//// later version.                                               ////
585 
////                                                              ////
586 
//// This source is distributed in the hope that it will be       ////
587 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
588 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
589 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
590 
//// details.                                                     ////
591 
////                                                              ////
592 
//// You should have received a copy of the GNU Lesser General    ////
593 
//// Public License along with this source; if not, download it   ////
594 
//// from http://www.opencores.org/lgpl.shtml                     ////
595 
////                                                              ////
596 
//////////////////////////////////////////////////////////////////////
597 
// binary counter
598 18 unneback 
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
599 6 unneback 
   parameter length = 4;
600 
   input clear;
601 
   input set;
602 
   input cke;
603 
   input rew;
604 
   output [length:1] q;
605 
   input rst;
606 
   input clk;
607 
   parameter clear_value = 0;
608 
   parameter set_value = 1;
609 
   parameter wrap_value = 0;
610 
   parameter level1_value = 15;
611 
   reg  [length:1] qi;
612 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
613 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
614 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
615 
   assign q_next = rew ? q_next_rew : q_next_fw;
616 
   always @ (posedge clk or posedge rst)
617 
     if (rst)
618 
       qi <= {length{1'b0}};
619 
     else
620 
     if (cke)
621 
       qi <= q_next;
622 
   assign q = qi;
623 
endmodule
624 
//////////////////////////////////////////////////////////////////////
625 
////                                                              ////
626 
////  Versatile counter                                           ////
627 
////                                                              ////
628 
////  Description                                                 ////
629 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
630 
////  counter                                                     ////
631 
////                                                              ////
632 
////  To Do:                                                      ////
633 
////   - add LFSR with more taps                                  ////
634 
////                                                              ////
635 
////  Author(s):                                                  ////
636 
////      - Michael Unneback, unneback@opencores.org              ////
637 
////        ORSoC AB                                              ////
638 
////                                                              ////
639 
//////////////////////////////////////////////////////////////////////
640 
////                                                              ////
641 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
642 
////                                                              ////
643 
//// This source file may be used and distributed without         ////
644 
//// restriction provided that this copyright statement is not    ////
645 
//// removed from the file and that any derivative work contains  ////
646 
//// the original copyright notice and the associated disclaimer. ////
647 
////                                                              ////
648 
//// This source file is free software; you can redistribute it   ////
649 
//// and/or modify it under the terms of the GNU Lesser General   ////
650 
//// Public License as published by the Free Software Foundation; ////
651 
//// either version 2.1 of the License, or (at your option) any   ////
652 
//// later version.                                               ////
653 
////                                                              ////
654 
//// This source is distributed in the hope that it will be       ////
655 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
656 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
657 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
658 
//// details.                                                     ////
659 
////                                                              ////
660 
//// You should have received a copy of the GNU Lesser General    ////
661 
//// Public License along with this source; if not, download it   ////
662 
//// from http://www.opencores.org/lgpl.shtml                     ////
663 
////                                                              ////
664 
//////////////////////////////////////////////////////////////////////
665 
// binary counter
666 18 unneback 
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
667 6 unneback 
   parameter length = 4;
668 
   input cke;
669 
   input rew;
670 
   output reg level1;
671 
   input rst;
672 
   input clk;
673 
   parameter clear_value = 0;
674 
   parameter set_value = 1;
675 
   parameter wrap_value = 1;
676 
   parameter level1_value = 15;
677 
   reg  [length:1] qi;
678 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
679 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
680 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
681 
   assign q_next = rew ? q_next_rew : q_next_fw;
682 
   always @ (posedge clk or posedge rst)
683 
     if (rst)
684 
       qi <= {length{1'b0}};
685 
     else
686 
     if (cke)
687 
       qi <= q_next;
688 
    always @ (posedge clk or posedge rst)
689 
    if (rst)
690 
        level1 <= 1'b0;
691 
    else
692 
    if (cke)
693 
    if (q_next == level1_value)
694 
        level1 <= 1'b1;
695 
    else if (qi == level1_value & rew)
696 
        level1 <= 1'b0;
697 
endmodule
698 
//////////////////////////////////////////////////////////////////////
699 
////                                                              ////
700 
////  Versatile counter                                           ////
701 
////                                                              ////
702 
////  Description                                                 ////
703 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
704 
////  counter                                                     ////
705 
////                                                              ////
706 
////  To Do:                                                      ////
707 
////   - add LFSR with more taps                                  ////
708 
////                                                              ////
709 
////  Author(s):                                                  ////
710 
////      - Michael Unneback, unneback@opencores.org              ////
711 
////        ORSoC AB                                              ////
712 
////                                                              ////
713 
//////////////////////////////////////////////////////////////////////
714 
////                                                              ////
715 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
716 
////                                                              ////
717 
//// This source file may be used and distributed without         ////
718 
//// restriction provided that this copyright statement is not    ////
719 
//// removed from the file and that any derivative work contains  ////
720 
//// the original copyright notice and the associated disclaimer. ////
721 
////                                                              ////
722 
//// This source file is free software; you can redistribute it   ////
723 
//// and/or modify it under the terms of the GNU Lesser General   ////
724 
//// Public License as published by the Free Software Foundation; ////
725 
//// either version 2.1 of the License, or (at your option) any   ////
726 
//// later version.                                               ////
727 
////                                                              ////
728 
//// This source is distributed in the hope that it will be       ////
729 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
730 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
731 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
732 
//// details.                                                     ////
733 
////                                                              ////
734 
//// You should have received a copy of the GNU Lesser General    ////
735 
//// Public License along with this source; if not, download it   ////
736 
//// from http://www.opencores.org/lgpl.shtml                     ////
737 
////                                                              ////
738 
//////////////////////////////////////////////////////////////////////
739 
// LFSR counter
740 18 unneback 
module vl_cnt_lfsr_zq ( zq, rst, clk);
741 6 unneback 
   parameter length = 4;
742 
   output reg zq;
743 
   input rst;
744 
   input clk;
745 
   parameter clear_value = 0;
746 
   parameter set_value = 1;
747 
   parameter wrap_value = 8;
748 
   parameter level1_value = 15;
749 
   reg  [length:1] qi;
750 
   reg lfsr_fb;
751 
   wire [length:1] q_next;
752 
   reg [32:1] polynom;
753 
   integer i;
754 
   always @ (qi)
755 
   begin
756 
        case (length)
757 
         2: polynom = 32'b11;                               // 0x3
758 
         3: polynom = 32'b110;                              // 0x6
759 
         4: polynom = 32'b1100;                             // 0xC
760 
         5: polynom = 32'b10100;                            // 0x14
761 
         6: polynom = 32'b110000;                           // 0x30
762 
         7: polynom = 32'b1100000;                          // 0x60
763 
         8: polynom = 32'b10111000;                         // 0xb8
764 
         9: polynom = 32'b100010000;                        // 0x110
765 
        10: polynom = 32'b1001000000;                       // 0x240
766 
        11: polynom = 32'b10100000000;                      // 0x500
767 
        12: polynom = 32'b100000101001;                     // 0x829
768 
        13: polynom = 32'b1000000001100;                    // 0x100C
769 
        14: polynom = 32'b10000000010101;                   // 0x2015
770 
        15: polynom = 32'b110000000000000;                  // 0x6000
771 
        16: polynom = 32'b1101000000001000;                 // 0xD008
772 
        17: polynom = 32'b10010000000000000;                // 0x12000
773 
        18: polynom = 32'b100000010000000000;               // 0x20400
774 
        19: polynom = 32'b1000000000000100011;              // 0x40023
775 
        20: polynom = 32'b10000010000000000000;             // 0x82000
776 
        21: polynom = 32'b101000000000000000000;            // 0x140000
777 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
778 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
779 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
780 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
781 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
782 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
783 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
784 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
785 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
786 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
787 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
788 
        default: polynom = 32'b0;
789 
        endcase
790 
        lfsr_fb = qi[length];
791 
        for (i=length-1; i>=1; i=i-1) begin
792 
            if (polynom[i])
793 
                lfsr_fb = lfsr_fb  ~^ qi[i];
794 
        end
795 
    end
796 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
797 
   always @ (posedge clk or posedge rst)
798 
     if (rst)
799 
       qi <= {length{1'b0}};
800 
     else
801 
       qi <= q_next;
802 
   always @ (posedge clk or posedge rst)
803 
     if (rst)
804 
       zq <= 1'b1;
805 
     else
806 
       zq <= q_next == {length{1'b0}};
807 
endmodule
808 
//////////////////////////////////////////////////////////////////////
809 
////                                                              ////
810 
////  Versatile counter                                           ////
811 
////                                                              ////
812 
////  Description                                                 ////
813 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
814 
////  counter                                                     ////
815 
////                                                              ////
816 
////  To Do:                                                      ////
817 
////   - add LFSR with more taps                                  ////
818 
////                                                              ////
819 
////  Author(s):                                                  ////
820 
////      - Michael Unneback, unneback@opencores.org              ////
821 
////        ORSoC AB                                              ////
822 
////                                                              ////
823 
//////////////////////////////////////////////////////////////////////
824 
////                                                              ////
825 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
826 
////                                                              ////
827 
//// This source file may be used and distributed without         ////
828 
//// restriction provided that this copyright statement is not    ////
829 
//// removed from the file and that any derivative work contains  ////
830 
//// the original copyright notice and the associated disclaimer. ////
831 
////                                                              ////
832 
//// This source file is free software; you can redistribute it   ////
833 
//// and/or modify it under the terms of the GNU Lesser General   ////
834 
//// Public License as published by the Free Software Foundation; ////
835 
//// either version 2.1 of the License, or (at your option) any   ////
836 
//// later version.                                               ////
837 
////                                                              ////
838 
//// This source is distributed in the hope that it will be       ////
839 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
840 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
841 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
842 
//// details.                                                     ////
843 
////                                                              ////
844 
//// You should have received a copy of the GNU Lesser General    ////
845 
//// Public License along with this source; if not, download it   ////
846 
//// from http://www.opencores.org/lgpl.shtml                     ////
847 
////                                                              ////
848 
//////////////////////////////////////////////////////////////////////
849 
// LFSR counter
850 18 unneback 
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
851 6 unneback 
   parameter length = 4;
852 
   input cke;
853 
   output reg zq;
854 
   input rst;
855 
   input clk;
856 
   parameter clear_value = 0;
857 
   parameter set_value = 1;
858 
   parameter wrap_value = 8;
859 
   parameter level1_value = 15;
860 
   reg  [length:1] qi;
861 
   reg lfsr_fb;
862 
   wire [length:1] q_next;
863 
   reg [32:1] polynom;
864 
   integer i;
865 
   always @ (qi)
866 
   begin
867 
        case (length)
868 
         2: polynom = 32'b11;                               // 0x3
869 
         3: polynom = 32'b110;                              // 0x6
870 
         4: polynom = 32'b1100;                             // 0xC
871 
         5: polynom = 32'b10100;                            // 0x14
872 
         6: polynom = 32'b110000;                           // 0x30
873 
         7: polynom = 32'b1100000;                          // 0x60
874 
         8: polynom = 32'b10111000;                         // 0xb8
875 
         9: polynom = 32'b100010000;                        // 0x110
876 
        10: polynom = 32'b1001000000;                       // 0x240
877 
        11: polynom = 32'b10100000000;                      // 0x500
878 
        12: polynom = 32'b100000101001;                     // 0x829
879 
        13: polynom = 32'b1000000001100;                    // 0x100C
880 
        14: polynom = 32'b10000000010101;                   // 0x2015
881 
        15: polynom = 32'b110000000000000;                  // 0x6000
882 
        16: polynom = 32'b1101000000001000;                 // 0xD008
883 
        17: polynom = 32'b10010000000000000;                // 0x12000
884 
        18: polynom = 32'b100000010000000000;               // 0x20400
885 
        19: polynom = 32'b1000000000000100011;              // 0x40023
886 
        20: polynom = 32'b10000010000000000000;             // 0x82000
887 
        21: polynom = 32'b101000000000000000000;            // 0x140000
888 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
889 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
890 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
891 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
892 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
893 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
894 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
895 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
896 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
897 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
898 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
899 
        default: polynom = 32'b0;
900 
        endcase
901 
        lfsr_fb = qi[length];
902 
        for (i=length-1; i>=1; i=i-1) begin
903 
            if (polynom[i])
904 
                lfsr_fb = lfsr_fb  ~^ qi[i];
905 
        end
906 
    end
907 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
908 
   always @ (posedge clk or posedge rst)
909 
     if (rst)
910 
       qi <= {length{1'b0}};
911 
     else
912 
     if (cke)
913 
       qi <= q_next;
914 
   always @ (posedge clk or posedge rst)
915 
     if (rst)
916 
       zq <= 1'b1;
917 
     else
918 
     if (cke)
919 
       zq <= q_next == {length{1'b0}};
920 
endmodule
921 
//////////////////////////////////////////////////////////////////////
922 
////                                                              ////
923 
////  Versatile counter                                           ////
924 
////                                                              ////
925 
////  Description                                                 ////
926 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
927 
////  counter                                                     ////
928 
////                                                              ////
929 
////  To Do:                                                      ////
930 
////   - add LFSR with more taps                                  ////
931 
////                                                              ////
932 
////  Author(s):                                                  ////
933 
////      - Michael Unneback, unneback@opencores.org              ////
934 
////        ORSoC AB                                              ////
935 
////                                                              ////
936 
//////////////////////////////////////////////////////////////////////
937 
////                                                              ////
938 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
939 
////                                                              ////
940 
//// This source file may be used and distributed without         ////
941 
//// restriction provided that this copyright statement is not    ////
942 
//// removed from the file and that any derivative work contains  ////
943 
//// the original copyright notice and the associated disclaimer. ////
944 
////                                                              ////
945 
//// This source file is free software; you can redistribute it   ////
946 
//// and/or modify it under the terms of the GNU Lesser General   ////
947 
//// Public License as published by the Free Software Foundation; ////
948 
//// either version 2.1 of the License, or (at your option) any   ////
949 
//// later version.                                               ////
950 
////                                                              ////
951 
//// This source is distributed in the hope that it will be       ////
952 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
953 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
954 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
955 
//// details.                                                     ////
956 
////                                                              ////
957 
//// You should have received a copy of the GNU Lesser General    ////
958 
//// Public License along with this source; if not, download it   ////
959 
//// from http://www.opencores.org/lgpl.shtml                     ////
960 
////                                                              ////
961 
//////////////////////////////////////////////////////////////////////
962 
// LFSR counter
963 18 unneback 
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
964 6 unneback 
   parameter length = 4;
965 
   input cke;
966 
   input rew;
967 
   output reg level1;
968 
   input rst;
969 
   input clk;
970 
   parameter clear_value = 0;
971 
   parameter set_value = 1;
972 
   parameter wrap_value = 8;
973 
   parameter level1_value = 15;
974 
   reg  [length:1] qi;
975 
   reg lfsr_fb, lfsr_fb_rew;
976 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
977 
   reg [32:1] polynom_rew;
978 
   integer j;
979 
   reg [32:1] polynom;
980 
   integer i;
981 
   always @ (qi)
982 
   begin
983 
        case (length)
984 
         2: polynom = 32'b11;                               // 0x3
985 
         3: polynom = 32'b110;                              // 0x6
986 
         4: polynom = 32'b1100;                             // 0xC
987 
         5: polynom = 32'b10100;                            // 0x14
988 
         6: polynom = 32'b110000;                           // 0x30
989 
         7: polynom = 32'b1100000;                          // 0x60
990 
         8: polynom = 32'b10111000;                         // 0xb8
991 
         9: polynom = 32'b100010000;                        // 0x110
992 
        10: polynom = 32'b1001000000;                       // 0x240
993 
        11: polynom = 32'b10100000000;                      // 0x500
994 
        12: polynom = 32'b100000101001;                     // 0x829
995 
        13: polynom = 32'b1000000001100;                    // 0x100C
996 
        14: polynom = 32'b10000000010101;                   // 0x2015
997 
        15: polynom = 32'b110000000000000;                  // 0x6000
998 
        16: polynom = 32'b1101000000001000;                 // 0xD008
999 
        17: polynom = 32'b10010000000000000;                // 0x12000
1000 
        18: polynom = 32'b100000010000000000;               // 0x20400
1001 
        19: polynom = 32'b1000000000000100011;              // 0x40023
1002 
        20: polynom = 32'b10000010000000000000;             // 0x82000
1003 
        21: polynom = 32'b101000000000000000000;            // 0x140000
1004 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1005 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1006 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1007 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1008 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1009 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1010 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1011 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1012 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1013 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1014 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1015 
        default: polynom = 32'b0;
1016 
        endcase
1017 
        lfsr_fb = qi[length];
1018 
        for (i=length-1; i>=1; i=i-1) begin
1019 
            if (polynom[i])
1020 
                lfsr_fb = lfsr_fb  ~^ qi[i];
1021 
        end
1022 
    end
1023 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1024 
   always @ (qi)
1025 
   begin
1026 
        case (length)
1027 
         2: polynom_rew = 32'b11;
1028 
         3: polynom_rew = 32'b110;
1029 
         4: polynom_rew = 32'b1100;
1030 
         5: polynom_rew = 32'b10100;
1031 
         6: polynom_rew = 32'b110000;
1032 
         7: polynom_rew = 32'b1100000;
1033 
         8: polynom_rew = 32'b10111000;
1034 
         9: polynom_rew = 32'b100010000;
1035 
        10: polynom_rew = 32'b1001000000;
1036 
        11: polynom_rew = 32'b10100000000;
1037 
        12: polynom_rew = 32'b100000101001;
1038 
        13: polynom_rew = 32'b1000000001100;
1039 
        14: polynom_rew = 32'b10000000010101;
1040 
        15: polynom_rew = 32'b110000000000000;
1041 
        16: polynom_rew = 32'b1101000000001000;
1042 
        17: polynom_rew = 32'b10010000000000000;
1043 
        18: polynom_rew = 32'b100000010000000000;
1044 
        19: polynom_rew = 32'b1000000000000100011;
1045 
        20: polynom_rew = 32'b10000010000000000000;
1046 
        21: polynom_rew = 32'b101000000000000000000;
1047 
        22: polynom_rew = 32'b1100000000000000000000;
1048 
        23: polynom_rew = 32'b10000100000000000000000;
1049 
        24: polynom_rew = 32'b111000010000000000000000;
1050 
        25: polynom_rew = 32'b1001000000000000000000000;
1051 
        26: polynom_rew = 32'b10000000000000000000100011;
1052 
        27: polynom_rew = 32'b100000000000000000000010011;
1053 
        28: polynom_rew = 32'b1100100000000000000000000000;
1054 
        29: polynom_rew = 32'b10100000000000000000000000000;
1055 
        30: polynom_rew = 32'b100000000000000000000000101001;
1056 
        31: polynom_rew = 32'b1001000000000000000000000000000;
1057 
        32: polynom_rew = 32'b10000000001000000000000000000011;
1058 
        default: polynom_rew = 32'b0;
1059 
        endcase
1060 
        // rotate left
1061 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1062 
        lfsr_fb_rew = qi[length];
1063 
        for (i=length-1; i>=1; i=i-1) begin
1064 
            if (polynom_rew[i])
1065 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1066 
        end
1067 
    end
1068 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1069 
   assign q_next = rew ? q_next_rew : q_next_fw;
1070 
   always @ (posedge clk or posedge rst)
1071 
     if (rst)
1072 
       qi <= {length{1'b0}};
1073 
     else
1074 
     if (cke)
1075 
       qi <= q_next;
1076 
    always @ (posedge clk or posedge rst)
1077 
    if (rst)
1078 
        level1 <= 1'b0;
1079 
    else
1080 
    if (cke)
1081 
    if (q_next == level1_value)
1082 
        level1 <= 1'b1;
1083 
    else if (qi == level1_value & rew)
1084 
        level1 <= 1'b0;
1085 
endmodule
1086 
//////////////////////////////////////////////////////////////////////
1087 
////                                                              ////
1088 
////  Versatile counter                                           ////
1089 
////                                                              ////
1090 
////  Description                                                 ////
1091 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1092 
////  counter                                                     ////
1093 
////                                                              ////
1094 
////  To Do:                                                      ////
1095 
////   - add LFSR with more taps                                  ////
1096 
////                                                              ////
1097 
////  Author(s):                                                  ////
1098 
////      - Michael Unneback, unneback@opencores.org              ////
1099 
////        ORSoC AB                                              ////
1100 
////                                                              ////
1101 
//////////////////////////////////////////////////////////////////////
1102 
////                                                              ////
1103 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1104 
////                                                              ////
1105 
//// This source file may be used and distributed without         ////
1106 
//// restriction provided that this copyright statement is not    ////
1107 
//// removed from the file and that any derivative work contains  ////
1108 
//// the original copyright notice and the associated disclaimer. ////
1109 
////                                                              ////
1110 
//// This source file is free software; you can redistribute it   ////
1111 
//// and/or modify it under the terms of the GNU Lesser General   ////
1112 
//// Public License as published by the Free Software Foundation; ////
1113 
//// either version 2.1 of the License, or (at your option) any   ////
1114 
//// later version.                                               ////
1115 
////                                                              ////
1116 
//// This source is distributed in the hope that it will be       ////
1117 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1118 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1119 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1120 
//// details.                                                     ////
1121 
////                                                              ////
1122 
//// You should have received a copy of the GNU Lesser General    ////
1123 
//// Public License along with this source; if not, download it   ////
1124 
//// from http://www.opencores.org/lgpl.shtml                     ////
1125 
////                                                              ////
1126 
//////////////////////////////////////////////////////////////////////
1127 
// GRAY counter
1128 18 unneback 
module vl_cnt_gray ( q, rst, clk);
1129 6 unneback 
   parameter length = 4;
1130 
   output reg [length:1] q;
1131 
   input rst;
1132 
   input clk;
1133 
   parameter clear_value = 0;
1134 
   parameter set_value = 1;
1135 
   parameter wrap_value = 8;
1136 
   parameter level1_value = 15;
1137 
   reg  [length:1] qi;
1138 
   wire [length:1] q_next;
1139 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1140 
   always @ (posedge clk or posedge rst)
1141 
     if (rst)
1142 
       qi <= {length{1'b0}};
1143 
     else
1144 
       qi <= q_next;
1145 
   always @ (posedge clk or posedge rst)
1146 
     if (rst)
1147 
       q <= {length{1'b0}};
1148 
     else
1149 
         q <= (q_next>>1) ^ q_next;
1150 
endmodule
1151 
//////////////////////////////////////////////////////////////////////
1152 
////                                                              ////
1153 
////  Versatile counter                                           ////
1154 
////                                                              ////
1155 
////  Description                                                 ////
1156 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1157 
////  counter                                                     ////
1158 
////                                                              ////
1159 
////  To Do:                                                      ////
1160 
////   - add LFSR with more taps                                  ////
1161 
////                                                              ////
1162 
////  Author(s):                                                  ////
1163 
////      - Michael Unneback, unneback@opencores.org              ////
1164 
////        ORSoC AB                                              ////
1165 
////                                                              ////
1166 
//////////////////////////////////////////////////////////////////////
1167 
////                                                              ////
1168 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1169 
////                                                              ////
1170 
//// This source file may be used and distributed without         ////
1171 
//// restriction provided that this copyright statement is not    ////
1172 
//// removed from the file and that any derivative work contains  ////
1173 
//// the original copyright notice and the associated disclaimer. ////
1174 
////                                                              ////
1175 
//// This source file is free software; you can redistribute it   ////
1176 
//// and/or modify it under the terms of the GNU Lesser General   ////
1177 
//// Public License as published by the Free Software Foundation; ////
1178 
//// either version 2.1 of the License, or (at your option) any   ////
1179 
//// later version.                                               ////
1180 
////                                                              ////
1181 
//// This source is distributed in the hope that it will be       ////
1182 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1183 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1184 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1185 
//// details.                                                     ////
1186 
////                                                              ////
1187 
//// You should have received a copy of the GNU Lesser General    ////
1188 
//// Public License along with this source; if not, download it   ////
1189 
//// from http://www.opencores.org/lgpl.shtml                     ////
1190 
////                                                              ////
1191 
//////////////////////////////////////////////////////////////////////
1192 
// GRAY counter
1193 18 unneback 
module vl_cnt_gray_ce ( cke, q, rst, clk);
1194 6 unneback 
   parameter length = 4;
1195 
   input cke;
1196 
   output reg [length:1] q;
1197 
   input rst;
1198 
   input clk;
1199 
   parameter clear_value = 0;
1200 
   parameter set_value = 1;
1201 
   parameter wrap_value = 8;
1202 
   parameter level1_value = 15;
1203 
   reg  [length:1] qi;
1204 
   wire [length:1] q_next;
1205 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1206 
   always @ (posedge clk or posedge rst)
1207 
     if (rst)
1208 
       qi <= {length{1'b0}};
1209 
     else
1210 
     if (cke)
1211 
       qi <= q_next;
1212 
   always @ (posedge clk or posedge rst)
1213 
     if (rst)
1214 
       q <= {length{1'b0}};
1215 
     else
1216 
       if (cke)
1217 
         q <= (q_next>>1) ^ q_next;
1218 
endmodule
1219 
//////////////////////////////////////////////////////////////////////
1220 
////                                                              ////
1221 
////  Versatile counter                                           ////
1222 
////                                                              ////
1223 
////  Description                                                 ////
1224 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1225 
////  counter                                                     ////
1226 
////                                                              ////
1227 
////  To Do:                                                      ////
1228 
////   - add LFSR with more taps                                  ////
1229 
////                                                              ////
1230 
////  Author(s):                                                  ////
1231 
////      - Michael Unneback, unneback@opencores.org              ////
1232 
////        ORSoC AB                                              ////
1233 
////                                                              ////
1234 
//////////////////////////////////////////////////////////////////////
1235 
////                                                              ////
1236 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1237 
////                                                              ////
1238 
//// This source file may be used and distributed without         ////
1239 
//// restriction provided that this copyright statement is not    ////
1240 
//// removed from the file and that any derivative work contains  ////
1241 
//// the original copyright notice and the associated disclaimer. ////
1242 
////                                                              ////
1243 
//// This source file is free software; you can redistribute it   ////
1244 
//// and/or modify it under the terms of the GNU Lesser General   ////
1245 
//// Public License as published by the Free Software Foundation; ////
1246 
//// either version 2.1 of the License, or (at your option) any   ////
1247 
//// later version.                                               ////
1248 
////                                                              ////
1249 
//// This source is distributed in the hope that it will be       ////
1250 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1251 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1252 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1253 
//// details.                                                     ////
1254 
////                                                              ////
1255 
//// You should have received a copy of the GNU Lesser General    ////
1256 
//// Public License along with this source; if not, download it   ////
1257 
//// from http://www.opencores.org/lgpl.shtml                     ////
1258 
////                                                              ////
1259 
//////////////////////////////////////////////////////////////////////
1260 
// GRAY counter
1261 18 unneback 
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1262 6 unneback 
   parameter length = 4;
1263 
   input cke;
1264 
   output reg [length:1] q;
1265 
   output [length:1] q_bin;
1266 
   input rst;
1267 
   input clk;
1268 
   parameter clear_value = 0;
1269 
   parameter set_value = 1;
1270 
   parameter wrap_value = 8;
1271 
   parameter level1_value = 15;
1272 
   reg  [length:1] qi;
1273 
   wire [length:1] q_next;
1274 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1275 
   always @ (posedge clk or posedge rst)
1276 
     if (rst)
1277 
       qi <= {length{1'b0}};
1278 
     else
1279 
     if (cke)
1280 
       qi <= q_next;
1281 
   always @ (posedge clk or posedge rst)
1282 
     if (rst)
1283 
       q <= {length{1'b0}};
1284 
     else
1285 
       if (cke)
1286 
         q <= (q_next>>1) ^ q_next;
1287 
   assign q_bin = qi;
1288 
endmodule
1289 
//////////////////////////////////////////////////////////////////////
1290 
////                                                              ////
1291 
////  Versatile library, counters                                 ////
1292 
////                                                              ////
1293 
////  Description                                                 ////
1294 
////  counters                                                    ////
1295 
////                                                              ////
1296 
////                                                              ////
1297 
////  To Do:                                                      ////
1298 
////   - add more counters                                        ////
1299 
////                                                              ////
1300 
////  Author(s):                                                  ////
1301 
////      - Michael Unneback, unneback@opencores.org              ////
1302 
////        ORSoC AB                                              ////
1303 
////                                                              ////
1304 
//////////////////////////////////////////////////////////////////////
1305 
////                                                              ////
1306 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1307 
////                                                              ////
1308 
//// This source file may be used and distributed without         ////
1309 
//// restriction provided that this copyright statement is not    ////
1310 
//// removed from the file and that any derivative work contains  ////
1311 
//// the original copyright notice and the associated disclaimer. ////
1312 
////                                                              ////
1313 
//// This source file is free software; you can redistribute it   ////
1314 
//// and/or modify it under the terms of the GNU Lesser General   ////
1315 
//// Public License as published by the Free Software Foundation; ////
1316 
//// either version 2.1 of the License, or (at your option) any   ////
1317 
//// later version.                                               ////
1318 
////                                                              ////
1319 
//// This source is distributed in the hope that it will be       ////
1320 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1321 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1322 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1323 
//// details.                                                     ////
1324 
////                                                              ////
1325 
//// You should have received a copy of the GNU Lesser General    ////
1326 
//// Public License along with this source; if not, download it   ////
1327 
//// from http://www.opencores.org/lgpl.shtml                     ////
1328 
////                                                              ////
1329 
//////////////////////////////////////////////////////////////////////
1330 18 unneback 
module vl_cnt_shreg_wrap ( q, rst, clk);
1331 6 unneback 
   parameter length = 4;
1332 
   output reg [0:length-1] q;
1333 
   input rst;
1334 
   input clk;
1335 
    always @ (posedge clk or posedge rst)
1336 
    if (rst)
1337 
        q <= {1'b1,{length-1{1'b0}}};
1338 
    else
1339 
        q <= {q[length-1],q[0:length-2]};
1340 
endmodule
1341 18 unneback 
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1342 6 unneback 
   parameter length = 4;
1343 
   input cke;
1344 
   output reg [0:length-1] q;
1345 
   input rst;
1346 
   input clk;
1347 
    always @ (posedge clk or posedge rst)
1348 
    if (rst)
1349 
        q <= {1'b1,{length-1{1'b0}}};
1350 
    else
1351 
        if (cke)
1352 
            q <= {q[length-1],q[0:length-2]};
1353 
endmodule
1354 18 unneback 
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1355 6 unneback 
   parameter length = 4;
1356 
   input cke, clear;
1357 
   output reg [0:length-1] q;
1358 
   input rst;
1359 
   input clk;
1360 
    always @ (posedge clk or posedge rst)
1361 
    if (rst)
1362 
        q <= {1'b1,{length-1{1'b0}}};
1363 
    else
1364 
        if (cke)
1365 
            if (clear)
1366 
                q <= {1'b1,{length-1{1'b0}}};
1367 
            else
1368 
                q <= q >> 1;
1369 
endmodule
1370 18 unneback 
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1371 6 unneback 
   parameter length = 4;
1372 
   input cke, clear;
1373 
   output reg [0:length-1] q;
1374 
   input rst;
1375 
   input clk;
1376 
    always @ (posedge clk or posedge rst)
1377 
    if (rst)
1378 
        q <= {1'b1,{length-1{1'b0}}};
1379 
    else
1380 
        if (cke)
1381 
            if (clear)
1382 
                q <= {1'b1,{length-1{1'b0}}};
1383 
            else
1384 
            q <= {q[length-1],q[0:length-2]};
1385 
endmodule
1386 
//////////////////////////////////////////////////////////////////////
1387 
////                                                              ////
1388 
////  Versatile library, memories                                 ////
1389 
////                                                              ////
1390 
////  Description                                                 ////
1391 
////  memories                                                    ////
1392 
////                                                              ////
1393 
////                                                              ////
1394 
////  To Do:                                                      ////
1395 
////   - add more memory types                                    ////
1396 
////                                                              ////
1397 
////  Author(s):                                                  ////
1398 
////      - Michael Unneback, unneback@opencores.org              ////
1399 
////        ORSoC AB                                              ////
1400 
////                                                              ////
1401 
//////////////////////////////////////////////////////////////////////
1402 
////                                                              ////
1403 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1404 
////                                                              ////
1405 
//// This source file may be used and distributed without         ////
1406 
//// restriction provided that this copyright statement is not    ////
1407 
//// removed from the file and that any derivative work contains  ////
1408 
//// the original copyright notice and the associated disclaimer. ////
1409 
////                                                              ////
1410 
//// This source file is free software; you can redistribute it   ////
1411 
//// and/or modify it under the terms of the GNU Lesser General   ////
1412 
//// Public License as published by the Free Software Foundation; ////
1413 
//// either version 2.1 of the License, or (at your option) any   ////
1414 
//// later version.                                               ////
1415 
////                                                              ////
1416 
//// This source is distributed in the hope that it will be       ////
1417 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1418 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1419 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1420 
//// details.                                                     ////
1421 
////                                                              ////
1422 
//// You should have received a copy of the GNU Lesser General    ////
1423 
//// Public License along with this source; if not, download it   ////
1424 
//// from http://www.opencores.org/lgpl.shtml                     ////
1425 
////                                                              ////
1426 
//////////////////////////////////////////////////////////////////////
1427 
/// ROM
1428 7 unneback 
module vl_rom_init ( adr, q, clk);
1429 
   parameter data_width = 32;
1430 
   parameter addr_width = 8;
1431 
   input [(addr_width-1):0]       adr;
1432 
   output reg [(data_width-1):0] q;
1433 
   input                         clk;
1434 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1435 
   parameter memory_file = "vl_rom.vmem";
1436 
   initial
1437 
     begin
1438 
        $readmemh(memory_file, rom);
1439 
     end
1440 
   always @ (posedge clk)
1441 
     q <= rom[adr];
1442 
endmodule
1443 14 unneback 
/*
1444 7 unneback 
module vl_rom ( adr, q, clk);
1445 6 unneback 
parameter data_width = 32;
1446 
parameter addr_width = 4;
1447 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1448 
    {32'h18000000},
1449 
    {32'hA8200000},
1450 
    {32'hA8200000},
1451 
    {32'hA8200000},
1452 
    {32'h44003000},
1453 
    {32'h15000000},
1454 
    {32'h15000000},
1455 
    {32'h15000000},
1456 
    {32'h15000000},
1457 
    {32'h15000000},
1458 
    {32'h15000000},
1459 
    {32'h15000000},
1460 
    {32'h15000000},
1461 
    {32'h15000000},
1462 
    {32'h15000000},
1463 
    {32'h15000000}};
1464 7 unneback 
input [addr_width-1:0] adr;
1465 6 unneback 
output reg [data_width-1:0] q;
1466 
input clk;
1467 
always @ (posedge clk)
1468 7 unneback 
    q <= data[adr];
1469 6 unneback 
endmodule
1470 14 unneback 
*/
1471 6 unneback 
// Single port RAM
1472 
module vl_ram ( d, adr, we, q, clk);
1473 
   parameter data_width = 32;
1474 
   parameter addr_width = 8;
1475 
   input [(data_width-1):0]      d;
1476 
   input [(addr_width-1):0]       adr;
1477 
   input                         we;
1478 7 unneback 
   output reg [(data_width-1):0] q;
1479 6 unneback 
   input                         clk;
1480 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1481 7 unneback 
   parameter init = 0;
1482 
   parameter memory_file = "vl_ram.vmem";
1483 
   generate if (init) begin : init_mem
1484 
   initial
1485 
     begin
1486 
        $readmemh(memory_file, ram);
1487 
     end
1488 
   end
1489 
   endgenerate
1490 6 unneback 
   always @ (posedge clk)
1491 
   begin
1492 
   if (we)
1493 
     ram[adr] <= d;
1494 
   q <= ram[adr];
1495 
   end
1496 
endmodule
1497 7 unneback 
module vl_ram_be ( d, adr, be, we, q, clk);
1498 
   parameter data_width = 32;
1499 
   parameter addr_width = 8;
1500 
   input [(data_width-1):0]      d;
1501 
   input [(addr_width-1):0]       adr;
1502 
   input [(addr_width/4)-1:0]    be;
1503 
   input                         we;
1504 
   output reg [(data_width-1):0] q;
1505 
   input                         clk;
1506 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1507 
   parameter init = 0;
1508 
   parameter memory_file = "vl_ram.vmem";
1509 
   generate if (init) begin : init_mem
1510 
   initial
1511 
     begin
1512 
        $readmemh(memory_file, ram);
1513 
     end
1514 
   end
1515 
   endgenerate
1516 
   genvar i;
1517 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1518 
      always @ (posedge clk)
1519 
      if (we & be[i])
1520 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1521 
   end
1522 
   endgenerate
1523 
   always @ (posedge clk)
1524 
      q <= ram[adr];
1525 
endmodule
1526 6 unneback 
// Dual port RAM
1527 
// ACTEL FPGA should not use logic to handle rw collision
1528 7 unneback 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1529 6 unneback 
   parameter data_width = 32;
1530 
   parameter addr_width = 8;
1531 
   input [(data_width-1):0]      d_a;
1532 
   input [(addr_width-1):0]       adr_a;
1533 
   input [(addr_width-1):0]       adr_b;
1534 
   input                         we_a;
1535 
   output [(data_width-1):0]      q_b;
1536 
   input                         clk_a, clk_b;
1537 
   reg [(addr_width-1):0]         adr_b_reg;
1538 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1539 7 unneback 
   parameter init = 0;
1540 
   parameter memory_file = "vl_ram.vmem";
1541 
   generate if (init) begin : init_mem
1542 
   initial
1543 
     begin
1544 
        $readmemh(memory_file, ram);
1545 
     end
1546 
   end
1547 
   endgenerate
1548 6 unneback 
   always @ (posedge clk_a)
1549 
   if (we_a)
1550 
     ram[adr_a] <= d_a;
1551 
   always @ (posedge clk_b)
1552 
   adr_b_reg <= adr_b;
1553 
   assign q_b = ram[adr_b_reg];
1554 
endmodule
1555 7 unneback 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1556 6 unneback 
   parameter data_width = 32;
1557 
   parameter addr_width = 8;
1558 
   input [(data_width-1):0]      d_a;
1559 
   input [(addr_width-1):0]       adr_a;
1560 
   input [(addr_width-1):0]       adr_b;
1561 
   input                         we_a;
1562 
   output [(data_width-1):0]      q_b;
1563 
   output reg [(data_width-1):0] q_a;
1564 
   input                         clk_a, clk_b;
1565 
   reg [(data_width-1):0]         q_b;
1566 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1567 7 unneback 
   parameter init = 0;
1568 
   parameter memory_file = "vl_ram.vmem";
1569 
   generate if (init) begin : init_mem
1570 
   initial
1571 
     begin
1572 
        $readmemh(memory_file, ram);
1573 
     end
1574 
   end
1575 
   endgenerate
1576 6 unneback 
   always @ (posedge clk_a)
1577 
     begin
1578 
        q_a <= ram[adr_a];
1579 
        if (we_a)
1580 
             ram[adr_a] <= d_a;
1581 
     end
1582 
   always @ (posedge clk_b)
1583 
          q_b <= ram[adr_b];
1584 
endmodule
1585 7 unneback 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1586 6 unneback 
   parameter data_width = 32;
1587 
   parameter addr_width = 8;
1588 
   input [(data_width-1):0]      d_a;
1589 
   input [(addr_width-1):0]       adr_a;
1590 
   input [(addr_width-1):0]       adr_b;
1591 
   input                         we_a;
1592 
   output [(data_width-1):0]      q_b;
1593 
   input [(data_width-1):0]       d_b;
1594 
   output reg [(data_width-1):0] q_a;
1595 
   input                         we_b;
1596 
   input                         clk_a, clk_b;
1597 
   reg [(data_width-1):0]         q_b;
1598 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1599 7 unneback 
   parameter init = 0;
1600 
   parameter memory_file = "vl_ram.vmem";
1601 
   generate if (init) begin : init_mem
1602 
   initial
1603 
     begin
1604 
        $readmemh(memory_file, ram);
1605 
     end
1606 
   end
1607 
   endgenerate
1608 6 unneback 
   always @ (posedge clk_a)
1609 
     begin
1610 
        q_a <= ram[adr_a];
1611 
        if (we_a)
1612 
             ram[adr_a] <= d_a;
1613 
     end
1614 
   always @ (posedge clk_b)
1615 
     begin
1616 
        q_b <= ram[adr_b];
1617 
        if (we_b)
1618 
          ram[adr_b] <= d_b;
1619 
     end
1620 
endmodule
1621 
// Content addresable memory, CAM
1622 
// FIFO
1623 
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1624 11 unneback 
   parameter addr_width = 4;
1625 
   parameter N = addr_width-1;
1626 6 unneback 
   parameter Q1 = 2'b00;
1627 
   parameter Q2 = 2'b01;
1628 
   parameter Q3 = 2'b11;
1629 
   parameter Q4 = 2'b10;
1630 
   parameter going_empty = 1'b0;
1631 
   parameter going_full  = 1'b1;
1632 
   input [N:0]  wptr, rptr;
1633 14 unneback 
   output       fifo_empty;
1634 6 unneback 
   output       fifo_full;
1635 
   input        wclk, rclk, rst;
1636 
   wire direction;
1637 
   reg  direction_set, direction_clr;
1638 
   wire async_empty, async_full;
1639 
   wire fifo_full2;
1640 14 unneback 
   wire fifo_empty2;
1641 6 unneback 
   // direction_set
1642 
   always @ (wptr[N:N-1] or rptr[N:N-1])
1643 
     case ({wptr[N:N-1],rptr[N:N-1]})
1644 
       {Q1,Q2} : direction_set <= 1'b1;
1645 
       {Q2,Q3} : direction_set <= 1'b1;
1646 
       {Q3,Q4} : direction_set <= 1'b1;
1647 
       {Q4,Q1} : direction_set <= 1'b1;
1648 
       default : direction_set <= 1'b0;
1649 
     endcase
1650 
   // direction_clear
1651 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1652 
     if (rst)
1653 
       direction_clr <= 1'b1;
1654 
     else
1655 
       case ({wptr[N:N-1],rptr[N:N-1]})
1656 
         {Q2,Q1} : direction_clr <= 1'b1;
1657 
         {Q3,Q2} : direction_clr <= 1'b1;
1658 
         {Q4,Q3} : direction_clr <= 1'b1;
1659 
         {Q1,Q4} : direction_clr <= 1'b1;
1660 
         default : direction_clr <= 1'b0;
1661 
       endcase
1662 18 unneback 
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1663 6 unneback 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1664 
   assign async_full  = (wptr == rptr) && (direction==going_full);
1665 18 unneback 
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1666 
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1667 6 unneback 
/*
1668 
   always @ (posedge wclk or posedge rst or posedge async_full)
1669 
     if (rst)
1670 
       {fifo_full, fifo_full2} <= 2'b00;
1671 
     else if (async_full)
1672 
       {fifo_full, fifo_full2} <= 2'b11;
1673 
     else
1674 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1675 
*/
1676 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
1677 6 unneback 
     if (async_empty)
1678 
       {fifo_empty, fifo_empty2} <= 2'b11;
1679 
     else
1680 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1681 18 unneback 
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1682 
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1683 6 unneback 
endmodule // async_comp
1684 
module vl_fifo_1r1w_async (
1685 
    d, wr, fifo_full, wr_clk, wr_rst,
1686 
    q, rd, fifo_empty, rd_clk, rd_rst
1687 
    );
1688 
parameter data_width = 18;
1689 
parameter addr_width = 4;
1690 
// write side
1691 
input  [data_width-1:0] d;
1692 
input                   wr;
1693 
output                  fifo_full;
1694 
input                   wr_clk;
1695 
input                   wr_rst;
1696 
// read side
1697 
output [data_width-1:0] q;
1698 
input                   rd;
1699 
output                  fifo_empty;
1700 
input                   rd_clk;
1701 
input                   rd_rst;
1702 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1703 
vl_fifo_1r1w_async (
1704 
    d, wr, fifo_full, wr_clk, wr_rst,
1705 
    q, rd, fifo_empty, rd_clk, rd_rst
1706 
    );
1707 18 unneback 
vl_cnt_gray_ce_bin
1708 6 unneback 
    # ( .length(addr_width))
1709 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1710 18 unneback 
vl_cnt_gray_ce_bin
1711 6 unneback 
    # (.length(addr_width))
1712 
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1713 7 unneback 
vl_dpram_1r1w
1714 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
1715 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1716 
vl_fifo_cmp_async
1717 
    # (.addr_width(addr_width))
1718 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1719 
endmodule
1720 8 unneback 
module vl_fifo_2r2w_async (
1721 6 unneback 
    // a side
1722 
    a_d, a_wr, a_fifo_full,
1723 
    a_q, a_rd, a_fifo_empty,
1724 
    a_clk, a_rst,
1725 
    // b side
1726 
    b_d, b_wr, b_fifo_full,
1727 
    b_q, b_rd, b_fifo_empty,
1728 
    b_clk, b_rst
1729 
    );
1730 
parameter data_width = 18;
1731 
parameter addr_width = 4;
1732 
// a side
1733 
input  [data_width-1:0] a_d;
1734 
input                   a_wr;
1735 
output                  a_fifo_full;
1736 
output [data_width-1:0] a_q;
1737 
input                   a_rd;
1738 
output                  a_fifo_empty;
1739 
input                   a_clk;
1740 
input                   a_rst;
1741 
// b side
1742 
input  [data_width-1:0] b_d;
1743 
input                   b_wr;
1744 
output                  b_fifo_full;
1745 
output [data_width-1:0] b_q;
1746 
input                   b_rd;
1747 
output                  b_fifo_empty;
1748 
input                   b_clk;
1749 
input                   b_rst;
1750 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1751 
vl_fifo_1r1w_async_a (
1752 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1753 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1754 
    );
1755 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1756 
vl_fifo_1r1w_async_b (
1757 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1758 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1759 
    );
1760 
endmodule
1761 8 unneback 
module vl_fifo_2r2w_async_simplex (
1762 6 unneback 
    // a side
1763 
    a_d, a_wr, a_fifo_full,
1764 
    a_q, a_rd, a_fifo_empty,
1765 
    a_clk, a_rst,
1766 
    // b side
1767 
    b_d, b_wr, b_fifo_full,
1768 
    b_q, b_rd, b_fifo_empty,
1769 
    b_clk, b_rst
1770 
    );
1771 
parameter data_width = 18;
1772 
parameter addr_width = 4;
1773 
// a side
1774 
input  [data_width-1:0] a_d;
1775 
input                   a_wr;
1776 
output                  a_fifo_full;
1777 
output [data_width-1:0] a_q;
1778 
input                   a_rd;
1779 
output                  a_fifo_empty;
1780 
input                   a_clk;
1781 
input                   a_rst;
1782 
// b side
1783 
input  [data_width-1:0] b_d;
1784 
input                   b_wr;
1785 
output                  b_fifo_full;
1786 
output [data_width-1:0] b_q;
1787 
input                   b_rd;
1788 
output                  b_fifo_empty;
1789 
input                   b_clk;
1790 
input                   b_rst;
1791 
// adr_gen
1792 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1793 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1794 
// dpram
1795 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1796 18 unneback 
vl_cnt_gray_ce_bin
1797 6 unneback 
    # ( .length(addr_width))
1798 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1799 18 unneback 
vl_cnt_gray_ce_bin
1800 6 unneback 
    # (.length(addr_width))
1801 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1802 18 unneback 
vl_cnt_gray_ce_bin
1803 6 unneback 
    # ( .length(addr_width))
1804 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1805 18 unneback 
vl_cnt_gray_ce_bin
1806 6 unneback 
    # (.length(addr_width))
1807 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1808 
// mux read or write adr to DPRAM
1809 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1810 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1811 11 unneback 
vl_dpram_2r2w
1812 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
1813 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1814 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1815 11 unneback 
vl_fifo_cmp_async
1816 6 unneback 
    # (.addr_width(addr_width))
1817 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1818 11 unneback 
vl_fifo_cmp_async
1819 6 unneback 
    # (.addr_width(addr_width))
1820 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1821 
endmodule
1822 12 unneback 
//////////////////////////////////////////////////////////////////////
1823 
////                                                              ////
1824 
////  Versatile library, wishbone stuff                           ////
1825 
////                                                              ////
1826 
////  Description                                                 ////
1827 
////  Wishbone compliant modules                                  ////
1828 
////                                                              ////
1829 
////                                                              ////
1830 
////  To Do:                                                      ////
1831 
////   -                                                          ////
1832 
////                                                              ////
1833 
////  Author(s):                                                  ////
1834 
////      - Michael Unneback, unneback@opencores.org              ////
1835 
////        ORSoC AB                                              ////
1836 
////                                                              ////
1837 
//////////////////////////////////////////////////////////////////////
1838 
////                                                              ////
1839 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1840 
////                                                              ////
1841 
//// This source file may be used and distributed without         ////
1842 
//// restriction provided that this copyright statement is not    ////
1843 
//// removed from the file and that any derivative work contains  ////
1844 
//// the original copyright notice and the associated disclaimer. ////
1845 
////                                                              ////
1846 
//// This source file is free software; you can redistribute it   ////
1847 
//// and/or modify it under the terms of the GNU Lesser General   ////
1848 
//// Public License as published by the Free Software Foundation; ////
1849 
//// either version 2.1 of the License, or (at your option) any   ////
1850 
//// later version.                                               ////
1851 
////                                                              ////
1852 
//// This source is distributed in the hope that it will be       ////
1853 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1854 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1855 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1856 
//// details.                                                     ////
1857 
////                                                              ////
1858 
//// You should have received a copy of the GNU Lesser General    ////
1859 
//// Public License along with this source; if not, download it   ////
1860 
//// from http://www.opencores.org/lgpl.shtml                     ////
1861 
////                                                              ////
1862 
//////////////////////////////////////////////////////////////////////
1863 
// async wb3 - wb3 bridge
1864 
`timescale 1ns/1ns
1865 18 unneback 
module vl_wb3wb3_bridge (
1866 12 unneback 
        // wishbone slave side
1867 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1868 
        // wishbone master side
1869 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1870 
input [31:0] wbs_dat_i;
1871 
input [31:2] wbs_adr_i;
1872 
input [3:0]  wbs_sel_i;
1873 
input [1:0]  wbs_bte_i;
1874 
input [2:0]  wbs_cti_i;
1875 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1876 
output [31:0] wbs_dat_o;
1877 14 unneback 
output wbs_ack_o;
1878 12 unneback 
input wbs_clk, wbs_rst;
1879 
output [31:0] wbm_dat_o;
1880 
output reg [31:2] wbm_adr_o;
1881 
output [3:0]  wbm_sel_o;
1882 
output reg [1:0]  wbm_bte_o;
1883 
output reg [2:0]  wbm_cti_o;
1884 14 unneback 
output reg wbm_we_o;
1885 
output wbm_cyc_o;
1886 12 unneback 
output wbm_stb_o;
1887 
input [31:0]  wbm_dat_i;
1888 
input wbm_ack_i;
1889 
input wbm_clk, wbm_rst;
1890 
parameter addr_width = 4;
1891 
// bte
1892 
parameter linear       = 2'b00;
1893 
parameter wrap4        = 2'b01;
1894 
parameter wrap8        = 2'b10;
1895 
parameter wrap16       = 2'b11;
1896 
// cti
1897 
parameter classic      = 3'b000;
1898 
parameter incburst     = 3'b010;
1899 
parameter endofburst   = 3'b111;
1900 
parameter wbs_adr  = 1'b0;
1901 
parameter wbs_data = 1'b1;
1902 
parameter wbm_adr0 = 2'b00;
1903 
parameter wbm_adr1 = 2'b01;
1904 
parameter wbm_data = 2'b10;
1905 
reg [1:0] wbs_bte_reg;
1906 
reg wbs;
1907 
wire wbs_eoc_alert, wbm_eoc_alert;
1908 
reg wbs_eoc, wbm_eoc;
1909 
reg [1:0] wbm;
1910 14 unneback 
wire [1:16] wbs_count, wbm_count;
1911 12 unneback 
wire [35:0] a_d, a_q, b_d, b_q;
1912 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1913 
reg a_rd_reg;
1914 
wire b_rd_adr, b_rd_data;
1915 14 unneback 
wire b_rd_data_reg;
1916 
wire [35:0] temp;
1917 12 unneback 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1918 
always @ (posedge wbs_clk or posedge wbs_rst)
1919 
if (wbs_rst)
1920 
        wbs_eoc <= 1'b0;
1921 
else
1922 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1923 
                wbs_eoc <= wbs_bte_i==linear;
1924 
        else if (wbs_eoc_alert & (a_rd | a_wr))
1925 
                wbs_eoc <= 1'b1;
1926 18 unneback 
vl_cnt_shreg_ce_clear # ( .length(16))
1927 12 unneback 
    cnt0 (
1928 
        .cke(wbs_ack_o),
1929 
        .clear(wbs_eoc),
1930 
        .q(wbs_count),
1931 
        .rst(wbs_rst),
1932 
        .clk(wbs_clk));
1933 
always @ (posedge wbs_clk or posedge wbs_rst)
1934 
if (wbs_rst)
1935 
        wbs <= wbs_adr;
1936 
else
1937 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1938 
                wbs <= wbs_data;
1939 
        else if (wbs_eoc & wbs_ack_o)
1940 
                wbs <= wbs_adr;
1941 
// wbs FIFO
1942 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1943 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1944 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1945 
              1'b0;
1946 
assign a_rd = !a_fifo_empty;
1947 
always @ (posedge wbs_clk or posedge wbs_rst)
1948 
if (wbs_rst)
1949 
        a_rd_reg <= 1'b0;
1950 
else
1951 
        a_rd_reg <= a_rd;
1952 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1953 
assign wbs_dat_o = a_q[35:4];
1954 
always @ (posedge wbs_clk or posedge wbs_rst)
1955 
if (wbs_rst)
1956 13 unneback 
        wbs_bte_reg <= 2'b00;
1957 12 unneback 
else
1958 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
1959 12 unneback 
// wbm FIFO
1960 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1961 
always @ (posedge wbm_clk or posedge wbm_rst)
1962 
if (wbm_rst)
1963 
        wbm_eoc <= 1'b0;
1964 
else
1965 
        if (wbm==wbm_adr0 & !b_fifo_empty)
1966 
                wbm_eoc <= b_q[4:3] == linear;
1967 
        else if (wbm_eoc_alert & wbm_ack_i)
1968 
                wbm_eoc <= 1'b1;
1969 
always @ (posedge wbm_clk or posedge wbm_rst)
1970 
if (wbm_rst)
1971 
        wbm <= wbm_adr0;
1972 
else
1973 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1974 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1975 
        (wbm==wbm_adr1 & !wbm_we_o) |
1976 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1977 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1978 
assign b_d = {wbm_dat_i,4'b1111};
1979 
assign b_wr = !wbm_we_o & wbm_ack_i;
1980 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1981 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1982 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1983 
                   1'b0;
1984 
assign b_rd = b_rd_adr | b_rd_data;
1985 18 unneback 
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1986 
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1987 12 unneback 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1988 18 unneback 
vl_cnt_shreg_ce_clear # ( .length(16))
1989 12 unneback 
    cnt1 (
1990 
        .cke(wbm_ack_i),
1991 
        .clear(wbm_eoc),
1992 
        .q(wbm_count),
1993 
        .rst(wbm_rst),
1994 
        .clk(wbm_clk));
1995 
assign wbm_cyc_o = wbm==wbm_data;
1996 
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
1997 
                   (wbm==wbm_data) ? 1'b1 :
1998 
                   1'b0;
1999 
always @ (posedge wbm_clk or posedge wbm_rst)
2000 
if (wbm_rst)
2001 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2002 
else begin
2003 
        if (wbm==wbm_adr0 & !b_fifo_empty)
2004 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2005 
        else if (wbm_eoc_alert & wbm_ack_i)
2006 
                wbm_cti_o <= endofburst;
2007 
end
2008 
//async_fifo_dw_simplex_top
2009 
vl_fifo_2r2w_async_simplex
2010 
# ( .data_width(36), .addr_width(addr_width))
2011 
fifo (
2012 
    // a side
2013 
    .a_d(a_d),
2014 
    .a_wr(a_wr),
2015 
    .a_fifo_full(a_fifo_full),
2016 
    .a_q(a_q),
2017 
    .a_rd(a_rd),
2018 
    .a_fifo_empty(a_fifo_empty),
2019 
    .a_clk(wbs_clk),
2020 
    .a_rst(wbs_rst),
2021 
    // b side
2022 
    .b_d(b_d),
2023 
    .b_wr(b_wr),
2024 
    .b_fifo_full(b_fifo_full),
2025 
    .b_q(b_q),
2026 
    .b_rd(b_rd),
2027 
    .b_fifo_empty(b_fifo_empty),
2028 
    .b_clk(wbm_clk),
2029 
    .b_rst(wbm_rst)
2030 
    );
2031 
endmodule
2032 17 unneback 
// WB ROM
2033 18 unneback 
module vl_wb_boot_rom (
2034 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
2035 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2036 
    parameter adr_hi = 31;
2037 
    parameter adr_lo = 28;
2038 
    parameter adr_sel = 4'hf;
2039 
    parameter addr_width = 5;
2040 17 unneback 
//E2_ifndef BOOT_ROM
2041 
//E2_define BOOT_ROM "boot_rom.v"
2042 
//E2_endif
2043 18 unneback 
    input [adr_hi:2]    wb_adr_i;
2044 
    input               wb_stb_i;
2045 
    input               wb_cyc_i;
2046 
    output [31:0]        wb_dat_o;
2047 
    output              wb_ack_o;
2048 
    output              hit_o;
2049 
    input               wb_clk;
2050 
    input               wb_rst;
2051 
    wire hit;
2052 
    reg [31:0] wb_dat;
2053 
    reg wb_ack;
2054 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2055 17 unneback 
always @ (posedge wb_clk or posedge wb_rst)
2056 
    if (wb_rst)
2057 18 unneback 
        wb_dat <= 32'h15000000;
2058 17 unneback 
    else
2059 18 unneback 
         case (wb_adr_i[addr_width-1:2])
2060 17 unneback 
//E2_include `BOOT_ROM
2061 
           /*
2062 
            // Zero r0 and jump to 0x00000100
2063 18 unneback 
 
2064 
            1 : wb_dat <= 32'hA8200000;
2065 
            2 : wb_dat <= 32'hA8C00100;
2066 
            3 : wb_dat <= 32'h44003000;
2067 
            4 : wb_dat <= 32'h15000000;
2068 17 unneback 
            */
2069 
           default:
2070 18 unneback 
             wb_dat <= 32'h00000000;
2071 17 unneback 
         endcase // case (wb_adr_i)
2072 
always @ (posedge wb_clk or posedge wb_rst)
2073 
    if (wb_rst)
2074 18 unneback 
        wb_ack <= 1'b0;
2075 17 unneback 
    else
2076 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2077 
assign hit_o = hit;
2078 
assign wb_dat_o = wb_dat & {32{wb_ack}};
2079 
assign wb_ack_o = wb_ack;
2080 17 unneback 
endmodule
2081 18 unneback 
//////////////////////////////////////////////////////////////////////
2082 
////                                                              ////
2083 
////  Arithmetic functions                                        ////
2084 
////                                                              ////
2085 
////  Description                                                 ////
2086 
////  Arithmetic functions for ALU and DSP                        ////
2087 
////                                                              ////
2088 
////                                                              ////
2089 
////  To Do:                                                      ////
2090 
////   -                                                          ////
2091 
////                                                              ////
2092 
////  Author(s):                                                  ////
2093 
////      - Michael Unneback, unneback@opencores.org              ////
2094 
////        ORSoC AB                                              ////
2095 
////                                                              ////
2096 
//////////////////////////////////////////////////////////////////////
2097 
////                                                              ////
2098 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2099 
////                                                              ////
2100 
//// This source file may be used and distributed without         ////
2101 
//// restriction provided that this copyright statement is not    ////
2102 
//// removed from the file and that any derivative work contains  ////
2103 
//// the original copyright notice and the associated disclaimer. ////
2104 
////                                                              ////
2105 
//// This source file is free software; you can redistribute it   ////
2106 
//// and/or modify it under the terms of the GNU Lesser General   ////
2107 
//// Public License as published by the Free Software Foundation; ////
2108 
//// either version 2.1 of the License, or (at your option) any   ////
2109 
//// later version.                                               ////
2110 
////                                                              ////
2111 
//// This source is distributed in the hope that it will be       ////
2112 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2113 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2114 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2115 
//// details.                                                     ////
2116 
////                                                              ////
2117 
//// You should have received a copy of the GNU Lesser General    ////
2118 
//// Public License along with this source; if not, download it   ////
2119 
//// from http://www.opencores.org/lgpl.shtml                     ////
2120 
////                                                              ////
2121 
//////////////////////////////////////////////////////////////////////
2122 
// signed multiplication
2123 
module vl_mults (a,b,p);
2124 
parameter operand_a_width = 18;
2125 
parameter operand_b_width = 18;
2126 
parameter result_hi = 35;
2127 
parameter result_lo = 0;
2128 
input [operand_a_width-1:0] a;
2129 
input [operand_b_width-1:0] b;
2130 
output [result_hi:result_lo] p;
2131 
wire signed [operand_a_width-1:0] ai;
2132 
wire signed [operand_b_width-1:0] bi;
2133 
wire signed [operand_a_width+operand_b_width-1:0] result;
2134 
    assign ai = a;
2135 
    assign bi = b;
2136 
    assign result = ai * bi;
2137 
    assign p = result[result_hi:result_lo];
2138 
endmodule
2139 
module vl_mults18x18 (a,b,p);
2140 
input [17:0] a,b;
2141 
output [35:0] p;
2142 
vl_mult
2143 
    # (.operand_a_width(18), .operand_b_width(18))
2144 
    mult0 (.a(a), .b(b), .p(p));
2145 
endmodule
2146 
// unsigned multiplication
2147 
module vl_mult (a,b,p);
2148 
parameter operand_a_width = 18;
2149 
parameter operand_b_width = 18;
2150 
parameter result_hi = 35;
2151 
parameter result_lo = 0;
2152 
input [operand_a_width-1:0] a;
2153 
input [operand_b_width-1:0] b;
2154 
output [result_hi:result_hi] p;
2155 
wire [operand_a_width+operand_b_width-1:0] result;
2156 
    assign result = a * b;
2157 
    assign p = result[result_hi:result_lo];
2158 
endmodule
2159 
// shift unit
2160 
// supporting the following shift functions
2161 
//   SLL
2162 
//   SRL
2163 
//   SRA
2164 
module vl_shift_unit_32( din, s, dout, opcode);
2165 
input [31:0] din; // data in operand
2166 
input [4:0] s; // shift operand
2167 
input [1:0] opcode;
2168 
output [31:0] dout;
2169 
parameter opcode_sll = 2'b00;
2170 
//parameter opcode_srl = 2'b01;
2171 
parameter opcode_sra = 2'b10;
2172 
//parameter opcode_ror = 2'b11;
2173 
wire sll, sra;
2174 
assign sll = opcode == opcode_sll;
2175 
assign sra = opcode == opcode_sra;
2176 
wire [15:1] s1;
2177 
wire [3:0] sign;
2178 
wire [7:0] tmp [0:3];
2179 
// first stage is multiplier based
2180 
// shift operand as fractional 8.7
2181 
assign s1[15] = sll & s[2:0]==3'd7;
2182 
assign s1[14] = sll & s[2:0]==3'd6;
2183 
assign s1[13] = sll & s[2:0]==3'd5;
2184 
assign s1[12] = sll & s[2:0]==3'd4;
2185 
assign s1[11] = sll & s[2:0]==3'd3;
2186 
assign s1[10] = sll & s[2:0]==3'd2;
2187 
assign s1[ 9] = sll & s[2:0]==3'd1;
2188 
assign s1[ 8] = s[2:0]==3'd0;
2189 
assign s1[ 7] = !sll & s[2:0]==3'd1;
2190 
assign s1[ 6] = !sll & s[2:0]==3'd2;
2191 
assign s1[ 5] = !sll & s[2:0]==3'd3;
2192 
assign s1[ 4] = !sll & s[2:0]==3'd4;
2193 
assign s1[ 3] = !sll & s[2:0]==3'd5;
2194 
assign s1[ 2] = !sll & s[2:0]==3'd6;
2195 
assign s1[ 1] = !sll & s[2:0]==3'd7;
2196 
assign sign[3] = din[31] & sra;
2197 
assign sign[2] = sign[3] & (&din[31:24]);
2198 
assign sign[1] = sign[2] & (&din[23:16]);
2199 
assign sign[0] = sign[1] & (&din[15:8]);
2200 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2201 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2202 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2203 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2204 
// second stage is multiplexer based
2205 
// shift on byte level
2206 
// mux byte 3
2207 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2208 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2209 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2210 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2211 
                     {8{sign[3]}};
2212 
// mux byte 2
2213 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2214 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2215 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2216 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2217 
                     (s[4:3]==2'b01) ? tmp[3] :
2218 
                     {8{sign[3]}};
2219 
// mux byte 1
2220 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2221 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2222 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2223 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2224 
                     (s[4:3]==2'b01) ? tmp[2] :
2225 
                     (s[4:3]==2'b10) ? tmp[3] :
2226 
                     {8{sign[3]}};
2227 
// mux byte 0
2228 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2229 
                     (sll) ?  {8{1'b0}}:
2230 
                     (s[4:3]==2'b01) ? tmp[1] :
2231 
                     (s[4:3]==2'b10) ? tmp[2] :
2232 
                     tmp[3];
2233 
endmodule
2234 
// logic unit
2235 
// supporting the following logic functions
2236 
//    a and b
2237 
//    a or  b
2238 
//    a xor b
2239 
//    not b
2240 
module vl_logic_unit( a, b, result, opcode);
2241 
parameter width = 32;
2242 
parameter opcode_and = 2'b00;
2243 
parameter opcode_or  = 2'b01;
2244 
parameter opcode_xor = 2'b10;
2245 
input [width-1:0] a,b;
2246 
output [width-1:0] result;
2247 
input [1:0] opcode;
2248 
assign result = (opcode==opcode_and) ? a & b :
2249 
                (opcode==opcode_or)  ? a | b :
2250 
                (opcode==opcode_xor) ? a ^ b :
2251 
                b;
2252 
endmodule
2253 
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2254 
parameter width = 32;
2255 
parameter opcode_add = 1'b0;
2256 
parameter opcode_sub = 1'b1;
2257 
input [width-1:0] a,b;
2258 
input c_in, add_sub, sign;
2259 
output [width-1:0] result;
2260 
output c_out, z, ovfl;
2261 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2262 
assign z = (result=={width{1'b0}});
2263 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2264 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2265 
endmodule

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