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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Versatile library, wishbone stuff ////
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//// ////
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//// Description ////
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//// Wishbone compliant modules ////
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//// ////
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//// ////
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//// To Do: ////
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//// - ////
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//// ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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unneback |
`ifdef WB_ADR_INC
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`timescale 1ns/1ns
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`define MODULE wb_adr_inc
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unneback |
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
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unneback |
`undef MODULE
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83 |
unneback |
parameter adr_width = 10;
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parameter max_burst_width = 4;
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unneback |
input cyc_i, stb_i, we_i;
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input [2:0] cti_i;
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input [1:0] bte_i;
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input [adr_width-1:0] adr_i;
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output [adr_width-1:0] adr_o;
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output ack_o;
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input clk, rst;
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unneback |
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reg [adr_width-1:0] adr;
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unneback |
wire [max_burst_width-1:0] to_adr;
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unneback |
reg [max_burst_width-1:0] last_adr;
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unneback |
reg last_cycle;
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localparam idle_or_eoc = 1'b0;
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localparam cyc_or_ws = 1'b1;
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90 |
unneback |
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unneback |
always @ (posedge clk or posedge rst)
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if (rst)
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last_adr <= {max_burst_width{1'b0}};
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else
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if (stb_i)
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unneback |
last_adr <=adr_o[max_burst_width-1:0];
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91 |
unneback |
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83 |
unneback |
generate
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if (max_burst_width==0) begin : inst_0
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unneback |
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reg ack_o;
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assign adr_o = adr_i;
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always @ (posedge clk or posedge rst)
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if (rst)
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ack_o <= 1'b0;
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else
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ack_o <= cyc_i & stb_i & !ack_o;
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unneback |
end else begin
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always @ (posedge clk or posedge rst)
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if (rst)
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last_cycle <= idle_or_eoc;
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unneback |
else
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unneback |
last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
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(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
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(cyc_i & !stb_i) ? cyc_or_ws : //ws
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cyc_or_ws; // cyc
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assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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unneback |
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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unneback |
(!stb_i) ? last_adr :
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unneback |
(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
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unneback |
adr[max_burst_width-1:0];
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unneback |
assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
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unneback |
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unneback |
end
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endgenerate
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generate
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if (max_burst_width==2) begin : inst_2
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always @ (posedge clk or posedge rst)
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if (rst)
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adr <= 2'h0;
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else
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if (cyc_i & stb_i)
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adr[1:0] <= to_adr[1:0] + 2'd1;
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else
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unneback |
adr <= to_adr[1:0];
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end
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endgenerate
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generate
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if (max_burst_width==3) begin : inst_3
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always @ (posedge clk or posedge rst)
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if (rst)
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adr <= 3'h0;
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else
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if (cyc_i & stb_i)
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case (bte_i)
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2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
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default: adr[3:0] <= to_adr[2:0] + 3'd1;
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unneback |
endcase
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unneback |
else
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adr <= to_adr[2:0];
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end
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endgenerate
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generate
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if (max_burst_width==4) begin : inst_4
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always @ (posedge clk or posedge rst)
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if (rst)
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adr <= 4'h0;
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else
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unneback |
if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
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83 |
unneback |
case (bte_i)
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2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
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2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
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default: adr[3:0] <= to_adr + 4'd1;
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endcase
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else
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adr <= to_adr[3:0];
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end
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endgenerate
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generate
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if (adr_width > max_burst_width) begin : pass_through
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assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
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end
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endgenerate
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endmodule
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unneback |
`endif
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104 |
unneback |
`ifdef WB_B4_EOC
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`define MODULE wb_b4_eoc
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module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
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`undef MODULE
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input cyc_i, stb_i, ack_o;
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output busy, eoc;
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input clk, rst;
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`define MODULE cnt_bin_ce_rew_zq_l1
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`BASE`MODULE # ( .length(4), level1_value(1))
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cnt0 (
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.cke(), .rew(), .zq(), .level1(), .rst(), clk);
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`undef MODULE
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endmodule
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`endif
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40 |
unneback |
`ifdef WB3WB3_BRIDGE
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unneback |
// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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unneback |
`define MODULE wb3wb3_bridge
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module `BASE`MODULE (
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`undef MODULE
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181 |
12 |
unneback |
// wishbone slave side
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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// wishbone master side
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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186 |
94 |
unneback |
parameter style = "FIFO"; // valid: simple, FIFO
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187 |
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parameter addr_width = 4;
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189 |
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unneback |
input [31:0] wbs_dat_i;
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input [31:2] wbs_adr_i;
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191 |
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input [3:0] wbs_sel_i;
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192 |
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input [1:0] wbs_bte_i;
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input [2:0] wbs_cti_i;
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194 |
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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output [31:0] wbs_dat_o;
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196 |
14 |
unneback |
output wbs_ack_o;
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197 |
12 |
unneback |
input wbs_clk, wbs_rst;
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198 |
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199 |
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output [31:0] wbm_dat_o;
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200 |
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output reg [31:2] wbm_adr_o;
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output [3:0] wbm_sel_o;
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output reg [1:0] wbm_bte_o;
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203 |
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output reg [2:0] wbm_cti_o;
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204 |
14 |
unneback |
output reg wbm_we_o;
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205 |
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output wbm_cyc_o;
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206 |
12 |
unneback |
output wbm_stb_o;
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207 |
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input [31:0] wbm_dat_i;
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208 |
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input wbm_ack_i;
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209 |
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input wbm_clk, wbm_rst;
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210 |
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211 |
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// bte
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212 |
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parameter linear = 2'b00;
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213 |
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parameter wrap4 = 2'b01;
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214 |
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parameter wrap8 = 2'b10;
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parameter wrap16 = 2'b11;
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216 |
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// cti
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217 |
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parameter classic = 3'b000;
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218 |
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parameter incburst = 3'b010;
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219 |
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parameter endofburst = 3'b111;
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220 |
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221 |
94 |
unneback |
localparam wbs_adr = 1'b0;
|
222 |
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localparam wbs_data = 1'b1;
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223 |
12 |
unneback |
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224 |
94 |
unneback |
localparam wbm_adr0 = 2'b00;
|
225 |
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localparam wbm_adr1 = 2'b01;
|
226 |
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localparam wbm_data = 2'b10;
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227 |
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localparam wbm_data_wait = 2'b11;
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228 |
12 |
unneback |
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229 |
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reg [1:0] wbs_bte_reg;
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230 |
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reg wbs;
|
231 |
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wire wbs_eoc_alert, wbm_eoc_alert;
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232 |
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reg wbs_eoc, wbm_eoc;
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233 |
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reg [1:0] wbm;
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234 |
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235 |
14 |
unneback |
wire [1:16] wbs_count, wbm_count;
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236 |
12 |
unneback |
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237 |
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wire [35:0] a_d, a_q, b_d, b_q;
|
238 |
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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239 |
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reg a_rd_reg;
|
240 |
|
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wire b_rd_adr, b_rd_data;
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241 |
14 |
unneback |
wire b_rd_data_reg;
|
242 |
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wire [35:0] temp;
|
243 |
12 |
unneback |
|
244 |
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`define WE 5
|
245 |
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`define BTE 4:3
|
246 |
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`define CTI 2:0
|
247 |
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|
248 |
|
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assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
249 |
|
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always @ (posedge wbs_clk or posedge wbs_rst)
|
250 |
|
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if (wbs_rst)
|
251 |
|
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wbs_eoc <= 1'b0;
|
252 |
|
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else
|
253 |
|
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
254 |
78 |
unneback |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
|
255 |
12 |
unneback |
else if (wbs_eoc_alert & (a_rd | a_wr))
|
256 |
|
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wbs_eoc <= 1'b1;
|
257 |
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|
258 |
40 |
unneback |
`define MODULE cnt_shreg_ce_clear
|
259 |
|
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`BASE`MODULE # ( .length(16))
|
260 |
|
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`undef MODULE
|
261 |
12 |
unneback |
cnt0 (
|
262 |
|
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.cke(wbs_ack_o),
|
263 |
|
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.clear(wbs_eoc),
|
264 |
|
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.q(wbs_count),
|
265 |
|
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.rst(wbs_rst),
|
266 |
|
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.clk(wbs_clk));
|
267 |
|
|
|
268 |
|
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always @ (posedge wbs_clk or posedge wbs_rst)
|
269 |
|
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if (wbs_rst)
|
270 |
|
|
wbs <= wbs_adr;
|
271 |
|
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else
|
272 |
75 |
unneback |
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
|
273 |
12 |
unneback |
wbs <= wbs_data;
|
274 |
|
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else if (wbs_eoc & wbs_ack_o)
|
275 |
|
|
wbs <= wbs_adr;
|
276 |
|
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|
277 |
|
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// wbs FIFO
|
278 |
75 |
unneback |
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
|
279 |
|
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
|
280 |
12 |
unneback |
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
281 |
|
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1'b0;
|
282 |
|
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assign a_rd = !a_fifo_empty;
|
283 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
284 |
|
|
if (wbs_rst)
|
285 |
|
|
a_rd_reg <= 1'b0;
|
286 |
|
|
else
|
287 |
|
|
a_rd_reg <= a_rd;
|
288 |
|
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
289 |
|
|
|
290 |
|
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assign wbs_dat_o = a_q[35:4];
|
291 |
|
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|
292 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
293 |
|
|
if (wbs_rst)
|
294 |
13 |
unneback |
wbs_bte_reg <= 2'b00;
|
295 |
12 |
unneback |
else
|
296 |
13 |
unneback |
wbs_bte_reg <= wbs_bte_i;
|
297 |
12 |
unneback |
|
298 |
|
|
// wbm FIFO
|
299 |
|
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
300 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
301 |
|
|
if (wbm_rst)
|
302 |
|
|
wbm_eoc <= 1'b0;
|
303 |
|
|
else
|
304 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
305 |
|
|
wbm_eoc <= b_q[`BTE] == linear;
|
306 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
307 |
|
|
wbm_eoc <= 1'b1;
|
308 |
|
|
|
309 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
310 |
|
|
if (wbm_rst)
|
311 |
|
|
wbm <= wbm_adr0;
|
312 |
|
|
else
|
313 |
33 |
unneback |
/*
|
314 |
12 |
unneback |
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
315 |
|
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
316 |
|
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
317 |
|
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
318 |
|
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
319 |
33 |
unneback |
*/
|
320 |
|
|
case (wbm)
|
321 |
|
|
wbm_adr0:
|
322 |
|
|
if (!b_fifo_empty)
|
323 |
|
|
wbm <= wbm_adr1;
|
324 |
|
|
wbm_adr1:
|
325 |
|
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
326 |
|
|
wbm <= wbm_data;
|
327 |
|
|
wbm_data:
|
328 |
|
|
if (wbm_ack_i & wbm_eoc)
|
329 |
|
|
wbm <= wbm_adr0;
|
330 |
|
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
331 |
|
|
wbm <= wbm_data_wait;
|
332 |
|
|
wbm_data_wait:
|
333 |
|
|
if (!b_fifo_empty)
|
334 |
|
|
wbm <= wbm_data;
|
335 |
|
|
endcase
|
336 |
12 |
unneback |
|
337 |
|
|
assign b_d = {wbm_dat_i,4'b1111};
|
338 |
|
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
339 |
|
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
340 |
|
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
341 |
|
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
342 |
33 |
unneback |
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
343 |
12 |
unneback |
1'b0;
|
344 |
|
|
assign b_rd = b_rd_adr | b_rd_data;
|
345 |
|
|
|
346 |
40 |
unneback |
`define MODULE dff
|
347 |
|
|
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
348 |
|
|
`undef MODULE
|
349 |
|
|
`define MODULE dff_ce
|
350 |
|
|
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
351 |
|
|
`undef MODULE
|
352 |
12 |
unneback |
|
353 |
|
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
354 |
|
|
|
355 |
40 |
unneback |
`define MODULE cnt_shreg_ce_clear
|
356 |
42 |
unneback |
`BASE`MODULE # ( .length(16))
|
357 |
40 |
unneback |
`undef MODULE
|
358 |
12 |
unneback |
cnt1 (
|
359 |
|
|
.cke(wbm_ack_i),
|
360 |
|
|
.clear(wbm_eoc),
|
361 |
|
|
.q(wbm_count),
|
362 |
|
|
.rst(wbm_rst),
|
363 |
|
|
.clk(wbm_clk));
|
364 |
|
|
|
365 |
33 |
unneback |
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
366 |
|
|
assign wbm_stb_o = (wbm==wbm_data);
|
367 |
12 |
unneback |
|
368 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
369 |
|
|
if (wbm_rst)
|
370 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
371 |
|
|
else begin
|
372 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
373 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
374 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
375 |
|
|
wbm_cti_o <= endofburst;
|
376 |
|
|
end
|
377 |
|
|
|
378 |
|
|
//async_fifo_dw_simplex_top
|
379 |
40 |
unneback |
`define MODULE fifo_2r2w_async_simplex
|
380 |
|
|
`BASE`MODULE
|
381 |
|
|
`undef MODULE
|
382 |
12 |
unneback |
# ( .data_width(36), .addr_width(addr_width))
|
383 |
|
|
fifo (
|
384 |
|
|
// a side
|
385 |
|
|
.a_d(a_d),
|
386 |
|
|
.a_wr(a_wr),
|
387 |
|
|
.a_fifo_full(a_fifo_full),
|
388 |
|
|
.a_q(a_q),
|
389 |
|
|
.a_rd(a_rd),
|
390 |
|
|
.a_fifo_empty(a_fifo_empty),
|
391 |
|
|
.a_clk(wbs_clk),
|
392 |
|
|
.a_rst(wbs_rst),
|
393 |
|
|
// b side
|
394 |
|
|
.b_d(b_d),
|
395 |
|
|
.b_wr(b_wr),
|
396 |
|
|
.b_fifo_full(b_fifo_full),
|
397 |
|
|
.b_q(b_q),
|
398 |
|
|
.b_rd(b_rd),
|
399 |
|
|
.b_fifo_empty(b_fifo_empty),
|
400 |
|
|
.b_clk(wbm_clk),
|
401 |
|
|
.b_rst(wbm_rst)
|
402 |
|
|
);
|
403 |
|
|
|
404 |
|
|
endmodule
|
405 |
40 |
unneback |
`undef WE
|
406 |
|
|
`undef BTE
|
407 |
|
|
`undef CTI
|
408 |
|
|
`endif
|
409 |
17 |
unneback |
|
410 |
75 |
unneback |
`ifdef WB3AVALON_BRIDGE
|
411 |
|
|
`define MODULE wb3avalon_bridge
|
412 |
|
|
module `BASE`MODULE (
|
413 |
|
|
`undef MODULE
|
414 |
|
|
// wishbone slave side
|
415 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
416 |
77 |
unneback |
// avalon master side
|
417 |
75 |
unneback |
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
418 |
|
|
|
419 |
84 |
unneback |
parameter linewrapburst = 1'b0;
|
420 |
|
|
|
421 |
75 |
unneback |
input [31:0] wbs_dat_i;
|
422 |
|
|
input [31:2] wbs_adr_i;
|
423 |
|
|
input [3:0] wbs_sel_i;
|
424 |
|
|
input [1:0] wbs_bte_i;
|
425 |
|
|
input [2:0] wbs_cti_i;
|
426 |
83 |
unneback |
input wbs_we_i;
|
427 |
|
|
input wbs_cyc_i;
|
428 |
|
|
input wbs_stb_i;
|
429 |
75 |
unneback |
output [31:0] wbs_dat_o;
|
430 |
|
|
output wbs_ack_o;
|
431 |
|
|
input wbs_clk, wbs_rst;
|
432 |
|
|
|
433 |
|
|
input [31:0] readdata;
|
434 |
|
|
output [31:0] writedata;
|
435 |
|
|
output [31:2] address;
|
436 |
|
|
output [3:0] be;
|
437 |
|
|
output write;
|
438 |
81 |
unneback |
output read;
|
439 |
75 |
unneback |
output beginbursttransfer;
|
440 |
|
|
output [3:0] burstcount;
|
441 |
|
|
input readdatavalid;
|
442 |
|
|
input waitrequest;
|
443 |
|
|
input clk;
|
444 |
|
|
input rst;
|
445 |
|
|
|
446 |
|
|
wire [1:0] wbm_bte_o;
|
447 |
|
|
wire [2:0] wbm_cti_o;
|
448 |
|
|
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
|
449 |
|
|
reg last_cyc;
|
450 |
79 |
unneback |
reg [3:0] counter;
|
451 |
82 |
unneback |
reg read_busy;
|
452 |
75 |
unneback |
|
453 |
|
|
always @ (posedge clk or posedge rst)
|
454 |
|
|
if (rst)
|
455 |
|
|
last_cyc <= 1'b0;
|
456 |
|
|
else
|
457 |
|
|
last_cyc <= wbm_cyc_o;
|
458 |
|
|
|
459 |
79 |
unneback |
always @ (posedge clk or posedge rst)
|
460 |
|
|
if (rst)
|
461 |
82 |
unneback |
read_busy <= 1'b0;
|
462 |
79 |
unneback |
else
|
463 |
82 |
unneback |
if (read & !waitrequest)
|
464 |
|
|
read_busy <= 1'b1;
|
465 |
|
|
else if (wbm_ack_i & wbm_cti_o!=3'b010)
|
466 |
|
|
read_busy <= 1'b0;
|
467 |
|
|
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
|
468 |
81 |
unneback |
|
469 |
75 |
unneback |
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
|
470 |
|
|
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
|
471 |
|
|
(wbm_bte_o==2'b10) ? 4'd8 :
|
472 |
78 |
unneback |
(wbm_bte_o==2'b11) ? 4'd16:
|
473 |
|
|
4'd1;
|
474 |
82 |
unneback |
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
|
475 |
75 |
unneback |
|
476 |
79 |
unneback |
always @ (posedge clk or posedge rst)
|
477 |
|
|
if (rst) begin
|
478 |
|
|
counter <= 4'd0;
|
479 |
|
|
end else
|
480 |
80 |
unneback |
if (wbm_we_o) begin
|
481 |
|
|
if (!waitrequest & !last_cyc & wbm_cyc_o) begin
|
482 |
84 |
unneback |
counter <= burstcount -4'd1;
|
483 |
80 |
unneback |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
|
484 |
|
|
counter <= burstcount;
|
485 |
|
|
end else if (!waitrequest & wbm_stb_o) begin
|
486 |
|
|
counter <= counter - 4'd1;
|
487 |
|
|
end
|
488 |
82 |
unneback |
end
|
489 |
81 |
unneback |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
|
490 |
79 |
unneback |
|
491 |
75 |
unneback |
`define MODULE wb3wb3_bridge
|
492 |
77 |
unneback |
`BASE`MODULE wbwb3inst (
|
493 |
75 |
unneback |
`undef MODULE
|
494 |
|
|
// wishbone slave side
|
495 |
|
|
.wbs_dat_i(wbs_dat_i),
|
496 |
|
|
.wbs_adr_i(wbs_adr_i),
|
497 |
|
|
.wbs_sel_i(wbs_sel_i),
|
498 |
|
|
.wbs_bte_i(wbs_bte_i),
|
499 |
|
|
.wbs_cti_i(wbs_cti_i),
|
500 |
|
|
.wbs_we_i(wbs_we_i),
|
501 |
|
|
.wbs_cyc_i(wbs_cyc_i),
|
502 |
|
|
.wbs_stb_i(wbs_stb_i),
|
503 |
|
|
.wbs_dat_o(wbs_dat_o),
|
504 |
|
|
.wbs_ack_o(wbs_ack_o),
|
505 |
|
|
.wbs_clk(wbs_clk),
|
506 |
|
|
.wbs_rst(wbs_rst),
|
507 |
|
|
// wishbone master side
|
508 |
|
|
.wbm_dat_o(writedata),
|
509 |
78 |
unneback |
.wbm_adr_o(address),
|
510 |
75 |
unneback |
.wbm_sel_o(be),
|
511 |
|
|
.wbm_bte_o(wbm_bte_o),
|
512 |
|
|
.wbm_cti_o(wbm_cti_o),
|
513 |
|
|
.wbm_we_o(wbm_we_o),
|
514 |
|
|
.wbm_cyc_o(wbm_cyc_o),
|
515 |
|
|
.wbm_stb_o(wbm_stb_o),
|
516 |
|
|
.wbm_dat_i(readdata),
|
517 |
|
|
.wbm_ack_i(wbm_ack_i),
|
518 |
|
|
.wbm_clk(clk),
|
519 |
|
|
.wbm_rst(rst));
|
520 |
|
|
|
521 |
|
|
|
522 |
|
|
endmodule
|
523 |
|
|
`endif
|
524 |
|
|
|
525 |
105 |
unneback |
`ifdef WB_ARBITER
|
526 |
|
|
`define MODULE wb_arbiter
|
527 |
42 |
unneback |
module `BASE`MODULE (
|
528 |
40 |
unneback |
`undef MODULE
|
529 |
39 |
unneback |
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
530 |
105 |
unneback |
wbm_dat_i, wbm_stall_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
531 |
39 |
unneback |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
532 |
105 |
unneback |
wbs_dat_o, wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
533 |
39 |
unneback |
wb_clk, wb_rst
|
534 |
|
|
);
|
535 |
|
|
|
536 |
|
|
parameter nr_of_ports = 3;
|
537 |
|
|
parameter adr_size = 26;
|
538 |
|
|
parameter adr_lo = 2;
|
539 |
|
|
parameter dat_size = 32;
|
540 |
|
|
parameter sel_size = dat_size/8;
|
541 |
|
|
|
542 |
|
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
543 |
|
|
localparam dw = dat_size * nr_of_ports;
|
544 |
|
|
localparam sw = sel_size * nr_of_ports;
|
545 |
|
|
localparam cw = 3 * nr_of_ports;
|
546 |
|
|
localparam bw = 2 * nr_of_ports;
|
547 |
|
|
|
548 |
|
|
input [dw-1:0] wbm_dat_o;
|
549 |
|
|
input [aw-1:0] wbm_adr_o;
|
550 |
|
|
input [sw-1:0] wbm_sel_o;
|
551 |
|
|
input [cw-1:0] wbm_cti_o;
|
552 |
|
|
input [bw-1:0] wbm_bte_o;
|
553 |
|
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
554 |
|
|
output [dw-1:0] wbm_dat_i;
|
555 |
105 |
unneback |
output [nr_of_ports-1:0] wbm_stall_o, wbm_ack_i, wbm_err_i, wbm_rty_i;
|
556 |
39 |
unneback |
|
557 |
|
|
output [dat_size-1:0] wbs_dat_i;
|
558 |
|
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
559 |
|
|
output [sel_size-1:0] wbs_sel_i;
|
560 |
|
|
output [2:0] wbs_cti_i;
|
561 |
|
|
output [1:0] wbs_bte_i;
|
562 |
|
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
563 |
|
|
input [dat_size-1:0] wbs_dat_o;
|
564 |
105 |
unneback |
input wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o;
|
565 |
39 |
unneback |
|
566 |
|
|
input wb_clk, wb_rst;
|
567 |
|
|
|
568 |
44 |
unneback |
reg [nr_of_ports-1:0] select;
|
569 |
39 |
unneback |
wire [nr_of_ports-1:0] state;
|
570 |
|
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
571 |
|
|
wire [nr_of_ports-1:0] sel;
|
572 |
|
|
wire idle;
|
573 |
|
|
|
574 |
|
|
genvar i;
|
575 |
|
|
|
576 |
|
|
assign idle = !(|state);
|
577 |
|
|
|
578 |
|
|
generate
|
579 |
|
|
if (nr_of_ports == 2) begin
|
580 |
|
|
|
581 |
|
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
582 |
|
|
|
583 |
|
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
584 |
|
|
|
585 |
44 |
unneback |
//assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
586 |
|
|
|
587 |
|
|
always @ (idle or wbm_cyc_o)
|
588 |
|
|
if (idle)
|
589 |
|
|
casex (wbm_cyc_o)
|
590 |
|
|
2'b1x : select = 2'b10;
|
591 |
|
|
2'b01 : select = 2'b01;
|
592 |
|
|
default : select = {nr_of_ports{1'b0}};
|
593 |
|
|
endcase
|
594 |
|
|
else
|
595 |
|
|
select = {nr_of_ports{1'b0}};
|
596 |
|
|
|
597 |
39 |
unneback |
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
598 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
599 |
|
|
|
600 |
|
|
end
|
601 |
|
|
endgenerate
|
602 |
|
|
|
603 |
|
|
generate
|
604 |
|
|
if (nr_of_ports == 3) begin
|
605 |
|
|
|
606 |
|
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
607 |
|
|
|
608 |
|
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
609 |
|
|
|
610 |
44 |
unneback |
always @ (idle or wbm_cyc_o)
|
611 |
|
|
if (idle)
|
612 |
|
|
casex (wbm_cyc_o)
|
613 |
|
|
3'b1xx : select = 3'b100;
|
614 |
|
|
3'b01x : select = 3'b010;
|
615 |
|
|
3'b001 : select = 3'b001;
|
616 |
|
|
default : select = {nr_of_ports{1'b0}};
|
617 |
|
|
endcase
|
618 |
|
|
else
|
619 |
|
|
select = {nr_of_ports{1'b0}};
|
620 |
|
|
|
621 |
|
|
// assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
622 |
39 |
unneback |
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
623 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
624 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
625 |
|
|
|
626 |
|
|
end
|
627 |
|
|
endgenerate
|
628 |
|
|
|
629 |
|
|
generate
|
630 |
44 |
unneback |
if (nr_of_ports == 4) begin
|
631 |
|
|
|
632 |
|
|
wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
633 |
|
|
|
634 |
|
|
assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
635 |
|
|
|
636 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
637 |
|
|
|
638 |
|
|
always @ (idle or wbm_cyc_o)
|
639 |
|
|
if (idle)
|
640 |
|
|
casex (wbm_cyc_o)
|
641 |
|
|
4'b1xxx : select = 4'b1000;
|
642 |
|
|
4'b01xx : select = 4'b0100;
|
643 |
|
|
4'b001x : select = 4'b0010;
|
644 |
|
|
4'b0001 : select = 4'b0001;
|
645 |
|
|
default : select = {nr_of_ports{1'b0}};
|
646 |
|
|
endcase
|
647 |
|
|
else
|
648 |
|
|
select = {nr_of_ports{1'b0}};
|
649 |
|
|
|
650 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
651 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
652 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
653 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
654 |
|
|
|
655 |
|
|
end
|
656 |
|
|
endgenerate
|
657 |
|
|
|
658 |
|
|
generate
|
659 |
|
|
if (nr_of_ports == 5) begin
|
660 |
|
|
|
661 |
|
|
wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
662 |
|
|
|
663 |
|
|
assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
664 |
|
|
|
665 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
666 |
|
|
|
667 |
|
|
always @ (idle or wbm_cyc_o)
|
668 |
|
|
if (idle)
|
669 |
|
|
casex (wbm_cyc_o)
|
670 |
|
|
5'b1xxxx : select = 5'b10000;
|
671 |
|
|
5'b01xxx : select = 5'b01000;
|
672 |
|
|
5'b001xx : select = 5'b00100;
|
673 |
|
|
5'b0001x : select = 5'b00010;
|
674 |
|
|
5'b00001 : select = 5'b00001;
|
675 |
|
|
default : select = {nr_of_ports{1'b0}};
|
676 |
|
|
endcase
|
677 |
|
|
else
|
678 |
|
|
select = {nr_of_ports{1'b0}};
|
679 |
|
|
|
680 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
681 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
682 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
683 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
684 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
685 |
|
|
|
686 |
|
|
end
|
687 |
|
|
endgenerate
|
688 |
|
|
|
689 |
|
|
generate
|
690 |
67 |
unneback |
if (nr_of_ports == 6) begin
|
691 |
|
|
|
692 |
|
|
wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
693 |
|
|
|
694 |
|
|
assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
695 |
|
|
|
696 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
697 |
|
|
|
698 |
|
|
always @ (idle or wbm_cyc_o)
|
699 |
|
|
if (idle)
|
700 |
|
|
casex (wbm_cyc_o)
|
701 |
|
|
6'b1xxxxx : select = 6'b100000;
|
702 |
|
|
6'b01xxxx : select = 6'b010000;
|
703 |
|
|
6'b001xxx : select = 6'b001000;
|
704 |
|
|
6'b0001xx : select = 6'b000100;
|
705 |
|
|
6'b00001x : select = 6'b000010;
|
706 |
|
|
6'b000001 : select = 6'b000001;
|
707 |
|
|
default : select = {nr_of_ports{1'b0}};
|
708 |
|
|
endcase
|
709 |
|
|
else
|
710 |
|
|
select = {nr_of_ports{1'b0}};
|
711 |
|
|
|
712 |
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
713 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
714 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
715 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
716 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
717 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
718 |
|
|
|
719 |
|
|
end
|
720 |
|
|
endgenerate
|
721 |
|
|
|
722 |
|
|
generate
|
723 |
|
|
if (nr_of_ports == 7) begin
|
724 |
|
|
|
725 |
|
|
wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
726 |
|
|
|
727 |
|
|
assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
728 |
|
|
|
729 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
730 |
|
|
|
731 |
|
|
always @ (idle or wbm_cyc_o)
|
732 |
|
|
if (idle)
|
733 |
|
|
casex (wbm_cyc_o)
|
734 |
|
|
7'b1xxxxxx : select = 7'b1000000;
|
735 |
|
|
7'b01xxxxx : select = 7'b0100000;
|
736 |
|
|
7'b001xxxx : select = 7'b0010000;
|
737 |
|
|
7'b0001xxx : select = 7'b0001000;
|
738 |
|
|
7'b00001xx : select = 7'b0000100;
|
739 |
|
|
7'b000001x : select = 7'b0000010;
|
740 |
|
|
7'b0000001 : select = 7'b0000001;
|
741 |
|
|
default : select = {nr_of_ports{1'b0}};
|
742 |
|
|
endcase
|
743 |
|
|
else
|
744 |
|
|
select = {nr_of_ports{1'b0}};
|
745 |
|
|
|
746 |
|
|
assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
|
747 |
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
748 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
749 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
750 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
751 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
752 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
753 |
|
|
|
754 |
|
|
end
|
755 |
|
|
endgenerate
|
756 |
|
|
|
757 |
|
|
generate
|
758 |
|
|
if (nr_of_ports == 8) begin
|
759 |
|
|
|
760 |
|
|
wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
761 |
|
|
|
762 |
|
|
assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
763 |
|
|
|
764 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
765 |
|
|
|
766 |
|
|
always @ (idle or wbm_cyc_o)
|
767 |
|
|
if (idle)
|
768 |
|
|
casex (wbm_cyc_o)
|
769 |
|
|
8'b1xxxxxxx : select = 8'b10000000;
|
770 |
|
|
8'b01xxxxxx : select = 8'b01000000;
|
771 |
|
|
8'b001xxxxx : select = 8'b00100000;
|
772 |
|
|
8'b0001xxxx : select = 8'b00010000;
|
773 |
|
|
8'b00001xxx : select = 8'b00001000;
|
774 |
|
|
8'b000001xx : select = 8'b00000100;
|
775 |
|
|
8'b0000001x : select = 8'b00000010;
|
776 |
|
|
8'b00000001 : select = 8'b00000001;
|
777 |
|
|
default : select = {nr_of_ports{1'b0}};
|
778 |
|
|
endcase
|
779 |
|
|
else
|
780 |
|
|
select = {nr_of_ports{1'b0}};
|
781 |
|
|
|
782 |
|
|
assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
|
783 |
|
|
assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
|
784 |
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
785 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
786 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
787 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
788 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
789 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
790 |
|
|
|
791 |
|
|
end
|
792 |
|
|
endgenerate
|
793 |
|
|
|
794 |
|
|
generate
|
795 |
63 |
unneback |
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
|
796 |
42 |
unneback |
`define MODULE spr
|
797 |
|
|
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
798 |
|
|
`undef MODULE
|
799 |
39 |
unneback |
end
|
800 |
|
|
endgenerate
|
801 |
|
|
|
802 |
|
|
assign sel = select | state;
|
803 |
|
|
|
804 |
40 |
unneback |
`define MODULE mux_andor
|
805 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
|
806 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
|
807 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
|
808 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
|
809 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
|
810 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
|
811 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
|
812 |
|
|
`undef MODULE
|
813 |
39 |
unneback |
assign wbs_cyc_i = |sel;
|
814 |
|
|
|
815 |
|
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
|
816 |
|
|
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
|
817 |
|
|
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
|
818 |
|
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
819 |
|
|
|
820 |
|
|
endmodule
|
821 |
40 |
unneback |
`endif
|
822 |
39 |
unneback |
|
823 |
101 |
unneback |
`ifdef WB_RAM
|
824 |
49 |
unneback |
// WB RAM with byte enable
|
825 |
101 |
unneback |
`define MODULE wb_ram
|
826 |
59 |
unneback |
module `BASE`MODULE (
|
827 |
|
|
`undef MODULE
|
828 |
69 |
unneback |
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
829 |
101 |
unneback |
wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
|
830 |
59 |
unneback |
|
831 |
101 |
unneback |
parameter adr_width = 16;
|
832 |
|
|
parameter mem_size = 1<<adr_width;
|
833 |
|
|
parameter dat_width = 32;
|
834 |
|
|
parameter max_burst_width = 4; // only used for B3
|
835 |
|
|
parameter mode = "B3"; // valid options: B3, B4
|
836 |
60 |
unneback |
parameter memory_init = 1;
|
837 |
|
|
parameter memory_file = "vl_ram.vmem";
|
838 |
59 |
unneback |
|
839 |
101 |
unneback |
input [dat_width-1:0] wbs_dat_i;
|
840 |
|
|
input [adr_width-1:0] wbs_adr_i;
|
841 |
|
|
input [2:0] wbs_cti_i;
|
842 |
|
|
input [1:0] wbs_bte_i;
|
843 |
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
844 |
70 |
unneback |
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
845 |
101 |
unneback |
output [dat_width-1:0] wbs_dat_o;
|
846 |
70 |
unneback |
output wbs_ack_o;
|
847 |
101 |
unneback |
output wbs_stall_o;
|
848 |
71 |
unneback |
input wb_clk, wb_rst;
|
849 |
59 |
unneback |
|
850 |
101 |
unneback |
wire [adr_width-1:0] adr;
|
851 |
|
|
wire we;
|
852 |
59 |
unneback |
|
853 |
101 |
unneback |
generate
|
854 |
|
|
if (mode=="B3") begin : B3_inst
|
855 |
83 |
unneback |
`define MODULE wb_adr_inc
|
856 |
101 |
unneback |
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
|
857 |
83 |
unneback |
.cyc_i(wbs_cyc_i),
|
858 |
|
|
.stb_i(wbs_stb_i),
|
859 |
|
|
.cti_i(wbs_cti_i),
|
860 |
|
|
.bte_i(wbs_bte_i),
|
861 |
|
|
.adr_i(wbs_adr_i),
|
862 |
84 |
unneback |
.we_i(wbs_we_i),
|
863 |
83 |
unneback |
.ack_o(wbs_ack_o),
|
864 |
|
|
.adr_o(adr),
|
865 |
|
|
.clk(wb_clk),
|
866 |
|
|
.rst(wb_rst));
|
867 |
|
|
`undef MODULE
|
868 |
101 |
unneback |
assign we = wbs_we_i & wbs_ack_o;
|
869 |
|
|
end else if (mode=="B4") begin : B4_inst
|
870 |
|
|
reg wbs_ack_o_reg;
|
871 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
872 |
|
|
if (wb_rst)
|
873 |
|
|
wbs_ack_o_reg <= 1'b0;
|
874 |
|
|
else
|
875 |
|
|
wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
|
876 |
|
|
assign wbs_ack_o = wbs_ack_o_reg;
|
877 |
|
|
assign wbs_stall_o = 1'b0;
|
878 |
|
|
assign adr = wbs_adr_i;
|
879 |
|
|
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
|
880 |
|
|
end
|
881 |
|
|
endgenerate
|
882 |
60 |
unneback |
|
883 |
100 |
unneback |
`define MODULE ram_be
|
884 |
|
|
`BASE`MODULE # (
|
885 |
|
|
.data_width(dat_width),
|
886 |
|
|
.addr_width(adr_width),
|
887 |
|
|
.mem_size(mem_size),
|
888 |
|
|
.memory_init(memory_init),
|
889 |
|
|
.memory_file(memory_file))
|
890 |
|
|
ram0(
|
891 |
|
|
`undef MODULE
|
892 |
101 |
unneback |
.d(wbs_dat_i),
|
893 |
|
|
.adr(adr),
|
894 |
|
|
.be(wbs_sel_i),
|
895 |
|
|
.we(we),
|
896 |
|
|
.q(wbs_dat_o),
|
897 |
100 |
unneback |
.clk(wb_clk)
|
898 |
|
|
);
|
899 |
49 |
unneback |
|
900 |
|
|
endmodule
|
901 |
|
|
`endif
|
902 |
|
|
|
903 |
103 |
unneback |
`ifdef WB_SHADOW_RAM
|
904 |
|
|
// A wishbone compliant RAM module that can be placed in front of other memory controllers
|
905 |
|
|
`define MODULE wb_shadow_ram
|
906 |
|
|
module `BASE`MODULE (
|
907 |
|
|
`undef MODULE
|
908 |
|
|
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
909 |
|
|
wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
910 |
|
|
wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
911 |
|
|
wbm_dat_i, wbm_ack_i, wbm_stall_i,
|
912 |
|
|
wb_clk, wb_rst);
|
913 |
|
|
|
914 |
|
|
parameter dat_width = 32;
|
915 |
|
|
parameter mode = "B4";
|
916 |
|
|
parameter max_burst_width = 4; // only used for B3
|
917 |
|
|
|
918 |
|
|
parameter shadow_mem_adr_width = 10;
|
919 |
|
|
parameter shadow_mem_size = 1024;
|
920 |
|
|
parameter shadow_mem_init = 2;
|
921 |
|
|
parameter shadow_mem_file = "vl_ram.v";
|
922 |
|
|
|
923 |
|
|
parameter main_mem_adr_width = 24;
|
924 |
|
|
|
925 |
|
|
input [dat_width-1:0] wbs_dat_i;
|
926 |
|
|
input [main_mem_adr_width-1:0] wbs_adr_i;
|
927 |
|
|
input [2:0] wbs_cti_i;
|
928 |
|
|
input [1:0] wbs_bte_i;
|
929 |
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
930 |
|
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
931 |
|
|
output [dat_width-1:0] wbs_dat_o;
|
932 |
|
|
output wbs_ack_o;
|
933 |
|
|
output wbs_stall_o;
|
934 |
|
|
|
935 |
|
|
output [dat_width-1:0] wbm_dat_o;
|
936 |
|
|
output [main_mem_adr_width-1:0] wbm_adr_o;
|
937 |
|
|
output [2:0] wbm_cti_o;
|
938 |
|
|
output [1:0] wbm_bte_o;
|
939 |
|
|
output [dat_width/8-1:0] wbm_sel_o;
|
940 |
|
|
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
941 |
|
|
input [dat_width-1:0] wbm_dat_i;
|
942 |
|
|
input wbm_ack_i, wbm_stall_i;
|
943 |
|
|
|
944 |
|
|
input wb_clk, wb_rst;
|
945 |
|
|
|
946 |
|
|
generate
|
947 |
|
|
if (shadow_mem_size>0) begin : shadow_ram_inst
|
948 |
|
|
|
949 |
|
|
wire cyc;
|
950 |
|
|
wire [dat_width-1:0] dat;
|
951 |
|
|
wire stall, ack;
|
952 |
|
|
|
953 |
|
|
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
|
954 |
|
|
`define MODULE wb_ram
|
955 |
|
|
`BASE`MODULE # (
|
956 |
|
|
.dat_width(dat_width),
|
957 |
|
|
.adr_width(shadow_mem_adr_width),
|
958 |
|
|
.mem_size(shadow_mem_size),
|
959 |
|
|
.memory_init(shadow_mem_init),
|
960 |
117 |
unneback |
.memory_file(shadow_mem_file),
|
961 |
103 |
unneback |
.mode(mode))
|
962 |
|
|
shadow_mem0 (
|
963 |
|
|
.wbs_dat_i(wbs_dat_i),
|
964 |
|
|
.wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
|
965 |
|
|
.wbs_sel_i(wbs_sel_i),
|
966 |
|
|
.wbs_we_i (wbs_we_i),
|
967 |
|
|
.wbs_bte_i(wbs_bte_i),
|
968 |
|
|
.wbs_cti_i(wbs_cti_i),
|
969 |
|
|
.wbs_stb_i(wbs_stb_i),
|
970 |
|
|
.wbs_cyc_i(cyc),
|
971 |
|
|
.wbs_dat_o(dat),
|
972 |
|
|
.wbs_stall_o(stall),
|
973 |
|
|
.wbs_ack_o(ack),
|
974 |
|
|
.wb_clk(wb_clk),
|
975 |
|
|
.wb_rst(wb_rst));
|
976 |
|
|
`undef MODULE
|
977 |
|
|
|
978 |
|
|
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
|
979 |
|
|
{wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
|
980 |
|
|
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
|
981 |
|
|
|
982 |
|
|
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
|
983 |
|
|
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
|
984 |
|
|
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
|
985 |
|
|
|
986 |
|
|
end else begin : no_shadow_ram_inst
|
987 |
|
|
|
988 |
|
|
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
|
989 |
|
|
{wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
|
990 |
|
|
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
|
991 |
|
|
|
992 |
|
|
end
|
993 |
|
|
endgenerate
|
994 |
|
|
|
995 |
|
|
endmodule
|
996 |
|
|
`endif
|
997 |
|
|
|
998 |
48 |
unneback |
`ifdef WB_B4_ROM
|
999 |
|
|
// WB ROM
|
1000 |
|
|
`define MODULE wb_b4_rom
|
1001 |
|
|
module `BASE`MODULE (
|
1002 |
|
|
`undef MODULE
|
1003 |
|
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
1004 |
|
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
1005 |
|
|
|
1006 |
|
|
parameter dat_width = 32;
|
1007 |
|
|
parameter dat_default = 32'h15000000;
|
1008 |
|
|
parameter adr_width = 32;
|
1009 |
|
|
|
1010 |
|
|
/*
|
1011 |
|
|
//E2_ifndef ROM
|
1012 |
|
|
//E2_define ROM "rom.v"
|
1013 |
|
|
//E2_endif
|
1014 |
|
|
*/
|
1015 |
|
|
input [adr_width-1:2] wb_adr_i;
|
1016 |
|
|
input wb_stb_i;
|
1017 |
|
|
input wb_cyc_i;
|
1018 |
|
|
output [dat_width-1:0] wb_dat_o;
|
1019 |
|
|
reg [dat_width-1:0] wb_dat_o;
|
1020 |
|
|
output wb_ack_o;
|
1021 |
|
|
reg wb_ack_o;
|
1022 |
|
|
output stall_o;
|
1023 |
|
|
input wb_clk;
|
1024 |
|
|
input wb_rst;
|
1025 |
|
|
|
1026 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
1027 |
|
|
if (wb_rst)
|
1028 |
|
|
wb_dat_o <= {dat_width{1'b0}};
|
1029 |
|
|
else
|
1030 |
|
|
case (wb_adr_i[adr_width-1:2])
|
1031 |
|
|
//E2_ifdef ROM
|
1032 |
|
|
//E2_include `ROM
|
1033 |
|
|
//E2_endif
|
1034 |
|
|
default:
|
1035 |
|
|
wb_dat_o <= dat_default;
|
1036 |
|
|
|
1037 |
|
|
endcase // case (wb_adr_i)
|
1038 |
|
|
|
1039 |
|
|
|
1040 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
1041 |
|
|
if (wb_rst)
|
1042 |
|
|
wb_ack_o <= 1'b0;
|
1043 |
|
|
else
|
1044 |
|
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
1045 |
|
|
|
1046 |
|
|
assign stall_o = 1'b0;
|
1047 |
|
|
|
1048 |
|
|
endmodule
|
1049 |
|
|
`endif
|
1050 |
|
|
|
1051 |
|
|
|
1052 |
40 |
unneback |
`ifdef WB_BOOT_ROM
|
1053 |
17 |
unneback |
// WB ROM
|
1054 |
40 |
unneback |
`define MODULE wb_boot_rom
|
1055 |
|
|
module `BASE`MODULE (
|
1056 |
|
|
`undef MODULE
|
1057 |
17 |
unneback |
wb_adr_i, wb_stb_i, wb_cyc_i,
|
1058 |
18 |
unneback |
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
1059 |
17 |
unneback |
|
1060 |
18 |
unneback |
parameter adr_hi = 31;
|
1061 |
|
|
parameter adr_lo = 28;
|
1062 |
|
|
parameter adr_sel = 4'hf;
|
1063 |
|
|
parameter addr_width = 5;
|
1064 |
33 |
unneback |
/*
|
1065 |
17 |
unneback |
//E2_ifndef BOOT_ROM
|
1066 |
|
|
//E2_define BOOT_ROM "boot_rom.v"
|
1067 |
|
|
//E2_endif
|
1068 |
33 |
unneback |
*/
|
1069 |
18 |
unneback |
input [adr_hi:2] wb_adr_i;
|
1070 |
|
|
input wb_stb_i;
|
1071 |
|
|
input wb_cyc_i;
|
1072 |
|
|
output [31:0] wb_dat_o;
|
1073 |
|
|
output wb_ack_o;
|
1074 |
|
|
output hit_o;
|
1075 |
|
|
input wb_clk;
|
1076 |
|
|
input wb_rst;
|
1077 |
|
|
|
1078 |
|
|
wire hit;
|
1079 |
|
|
reg [31:0] wb_dat;
|
1080 |
|
|
reg wb_ack;
|
1081 |
|
|
|
1082 |
|
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
1083 |
17 |
unneback |
|
1084 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
1085 |
|
|
if (wb_rst)
|
1086 |
18 |
unneback |
wb_dat <= 32'h15000000;
|
1087 |
17 |
unneback |
else
|
1088 |
18 |
unneback |
case (wb_adr_i[addr_width-1:2])
|
1089 |
33 |
unneback |
//E2_ifdef BOOT_ROM
|
1090 |
17 |
unneback |
//E2_include `BOOT_ROM
|
1091 |
33 |
unneback |
//E2_endif
|
1092 |
17 |
unneback |
/*
|
1093 |
|
|
// Zero r0 and jump to 0x00000100
|
1094 |
18 |
unneback |
|
1095 |
|
|
1 : wb_dat <= 32'hA8200000;
|
1096 |
|
|
2 : wb_dat <= 32'hA8C00100;
|
1097 |
|
|
3 : wb_dat <= 32'h44003000;
|
1098 |
|
|
4 : wb_dat <= 32'h15000000;
|
1099 |
17 |
unneback |
*/
|
1100 |
|
|
default:
|
1101 |
18 |
unneback |
wb_dat <= 32'h00000000;
|
1102 |
17 |
unneback |
|
1103 |
|
|
endcase // case (wb_adr_i)
|
1104 |
|
|
|
1105 |
|
|
|
1106 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
1107 |
|
|
if (wb_rst)
|
1108 |
18 |
unneback |
wb_ack <= 1'b0;
|
1109 |
17 |
unneback |
else
|
1110 |
18 |
unneback |
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
1111 |
17 |
unneback |
|
1112 |
18 |
unneback |
assign hit_o = hit;
|
1113 |
|
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
1114 |
|
|
assign wb_ack_o = wb_ack;
|
1115 |
|
|
|
1116 |
17 |
unneback |
endmodule
|
1117 |
40 |
unneback |
`endif
|
1118 |
32 |
unneback |
|
1119 |
106 |
unneback |
`ifdef WB_DPRAM
|
1120 |
|
|
`define MODULE wb_dpram
|
1121 |
40 |
unneback |
module `BASE`MODULE (
|
1122 |
|
|
`undef MODULE
|
1123 |
32 |
unneback |
// wishbone slave side a
|
1124 |
106 |
unneback |
wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
|
1125 |
32 |
unneback |
wbsa_clk, wbsa_rst,
|
1126 |
92 |
unneback |
// wishbone slave side b
|
1127 |
106 |
unneback |
wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
|
1128 |
32 |
unneback |
wbsb_clk, wbsb_rst);
|
1129 |
|
|
|
1130 |
92 |
unneback |
parameter data_width_a = 32;
|
1131 |
|
|
parameter data_width_b = data_width_a;
|
1132 |
|
|
parameter addr_width_a = 8;
|
1133 |
|
|
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
|
1134 |
101 |
unneback |
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
|
1135 |
92 |
unneback |
parameter max_burst_width_a = 4;
|
1136 |
|
|
parameter max_burst_width_b = max_burst_width_a;
|
1137 |
101 |
unneback |
parameter mode = "B3";
|
1138 |
109 |
unneback |
parameter memory_init = 0;
|
1139 |
|
|
parameter memory_file = "vl_ram.v";
|
1140 |
92 |
unneback |
input [data_width_a-1:0] wbsa_dat_i;
|
1141 |
|
|
input [addr_width_a-1:0] wbsa_adr_i;
|
1142 |
|
|
input [data_width_a/8-1:0] wbsa_sel_i;
|
1143 |
|
|
input [2:0] wbsa_cti_i;
|
1144 |
|
|
input [1:0] wbsa_bte_i;
|
1145 |
32 |
unneback |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
1146 |
92 |
unneback |
output [data_width_a-1:0] wbsa_dat_o;
|
1147 |
109 |
unneback |
output wbsa_ack_o;
|
1148 |
106 |
unneback |
output wbsa_stall_o;
|
1149 |
32 |
unneback |
input wbsa_clk, wbsa_rst;
|
1150 |
|
|
|
1151 |
92 |
unneback |
input [data_width_b-1:0] wbsb_dat_i;
|
1152 |
|
|
input [addr_width_b-1:0] wbsb_adr_i;
|
1153 |
|
|
input [data_width_b/8-1:0] wbsb_sel_i;
|
1154 |
|
|
input [2:0] wbsb_cti_i;
|
1155 |
|
|
input [1:0] wbsb_bte_i;
|
1156 |
32 |
unneback |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
1157 |
92 |
unneback |
output [data_width_b-1:0] wbsb_dat_o;
|
1158 |
109 |
unneback |
output wbsb_ack_o;
|
1159 |
106 |
unneback |
output wbsb_stall_o;
|
1160 |
32 |
unneback |
input wbsb_clk, wbsb_rst;
|
1161 |
|
|
|
1162 |
92 |
unneback |
wire [addr_width_a-1:0] adr_a;
|
1163 |
|
|
wire [addr_width_b-1:0] adr_b;
|
1164 |
101 |
unneback |
wire we_a, we_b;
|
1165 |
|
|
generate
|
1166 |
|
|
if (mode=="B3") begin : b3_inst
|
1167 |
92 |
unneback |
`define MODULE wb_adr_inc
|
1168 |
|
|
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
|
1169 |
|
|
.cyc_i(wbsa_cyc_i),
|
1170 |
|
|
.stb_i(wbsa_stb_i),
|
1171 |
|
|
.cti_i(wbsa_cti_i),
|
1172 |
|
|
.bte_i(wbsa_bte_i),
|
1173 |
|
|
.adr_i(wbsa_adr_i),
|
1174 |
|
|
.we_i(wbsa_we_i),
|
1175 |
|
|
.ack_o(wbsa_ack_o),
|
1176 |
|
|
.adr_o(adr_a),
|
1177 |
|
|
.clk(wbsa_clk),
|
1178 |
|
|
.rst(wbsa_rst));
|
1179 |
101 |
unneback |
assign we_a = wbsa_we_i & wbsa_ack_o;
|
1180 |
92 |
unneback |
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
|
1181 |
|
|
.cyc_i(wbsb_cyc_i),
|
1182 |
|
|
.stb_i(wbsb_stb_i),
|
1183 |
|
|
.cti_i(wbsb_cti_i),
|
1184 |
|
|
.bte_i(wbsb_bte_i),
|
1185 |
|
|
.adr_i(wbsb_adr_i),
|
1186 |
|
|
.we_i(wbsb_we_i),
|
1187 |
|
|
.ack_o(wbsb_ack_o),
|
1188 |
|
|
.adr_o(adr_b),
|
1189 |
|
|
.clk(wbsb_clk),
|
1190 |
|
|
.rst(wbsb_rst));
|
1191 |
40 |
unneback |
`undef MODULE
|
1192 |
101 |
unneback |
assign we_b = wbsb_we_i & wbsb_ack_o;
|
1193 |
|
|
end else if (mode=="B4") begin : b4_inst
|
1194 |
109 |
unneback |
`define MODULE dff
|
1195 |
|
|
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
1196 |
101 |
unneback |
assign wbsa_stall_o = 1'b0;
|
1197 |
|
|
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
|
1198 |
109 |
unneback |
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
1199 |
|
|
`undef MODULE
|
1200 |
101 |
unneback |
assign wbsb_stall_o = 1'b0;
|
1201 |
|
|
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
|
1202 |
|
|
end
|
1203 |
|
|
endgenerate
|
1204 |
92 |
unneback |
|
1205 |
|
|
`define MODULE dpram_be_2r2w
|
1206 |
109 |
unneback |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
|
1207 |
110 |
unneback |
.b_data_width(data_width_b),
|
1208 |
109 |
unneback |
.memory_init(memory_init), .memory_file(memory_file))
|
1209 |
92 |
unneback |
`undef MODULE
|
1210 |
|
|
ram_i (
|
1211 |
32 |
unneback |
.d_a(wbsa_dat_i),
|
1212 |
92 |
unneback |
.q_a(wbsa_dat_o),
|
1213 |
|
|
.adr_a(adr_a),
|
1214 |
|
|
.be_a(wbsa_sel_i),
|
1215 |
101 |
unneback |
.we_a(we_a),
|
1216 |
32 |
unneback |
.clk_a(wbsa_clk),
|
1217 |
|
|
.d_b(wbsb_dat_i),
|
1218 |
92 |
unneback |
.q_b(wbsb_dat_o),
|
1219 |
|
|
.adr_b(adr_b),
|
1220 |
|
|
.be_b(wbsb_sel_i),
|
1221 |
101 |
unneback |
.we_b(we_b),
|
1222 |
32 |
unneback |
.clk_b(wbsb_clk) );
|
1223 |
|
|
|
1224 |
|
|
endmodule
|
1225 |
40 |
unneback |
`endif
|
1226 |
94 |
unneback |
|
1227 |
101 |
unneback |
`ifdef WB_CACHE
|
1228 |
|
|
`define MODULE wb_cache
|
1229 |
96 |
unneback |
module `BASE`MODULE (
|
1230 |
103 |
unneback |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
|
1231 |
98 |
unneback |
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
1232 |
96 |
unneback |
);
|
1233 |
|
|
`undef MODULE
|
1234 |
|
|
|
1235 |
|
|
parameter dw_s = 32;
|
1236 |
|
|
parameter aw_s = 24;
|
1237 |
|
|
parameter dw_m = dw_s;
|
1238 |
124 |
unneback |
//localparam aw_m = dw_s * aw_s / dw_m;
|
1239 |
|
|
localparam aw_m =
|
1240 |
126 |
unneback |
(dw_s==dw_m) ? aw_s :
|
1241 |
|
|
(dw_s==dw_m*2) ? aw_s+1 :
|
1242 |
|
|
(dw_s==dw_m*4) ? aw_s+2 :
|
1243 |
|
|
(dw_s==dw_m*8) ? aw_s+3 :
|
1244 |
|
|
(dw_s==dw_m*16) ? aw_s+4 :
|
1245 |
|
|
(dw_s==dw_m*32) ? aw_s+5 :
|
1246 |
|
|
(dw_s==dw_m/2) ? aw_s-1 :
|
1247 |
127 |
unneback |
(dw_s==dw_m/4) ? aw_s-2 :
|
1248 |
126 |
unneback |
(dw_s==dw_m/8) ? aw_s-3 :
|
1249 |
|
|
(dw_s==dw_m/16) ? aw_s-4 :
|
1250 |
|
|
(dw_s==dw_m/32) ? aw_s-5 : 0;
|
1251 |
124 |
unneback |
|
1252 |
100 |
unneback |
parameter wbs_max_burst_width = 4;
|
1253 |
103 |
unneback |
parameter wbs_mode = "B3";
|
1254 |
96 |
unneback |
|
1255 |
97 |
unneback |
parameter async = 1; // wbs_clk != wbm_clk
|
1256 |
|
|
|
1257 |
96 |
unneback |
parameter nr_of_ways = 1;
|
1258 |
97 |
unneback |
parameter aw_offset = 4; // 4 => 16 words per cache line
|
1259 |
|
|
parameter aw_slot = 10;
|
1260 |
100 |
unneback |
|
1261 |
|
|
parameter valid_mem = 0;
|
1262 |
|
|
parameter debug = 0;
|
1263 |
|
|
|
1264 |
|
|
localparam aw_b_offset = aw_offset * dw_s / dw_m;
|
1265 |
98 |
unneback |
localparam aw_tag = aw_s - aw_slot - aw_offset;
|
1266 |
97 |
unneback |
parameter wbm_burst_size = 4; // valid options 4,8,16
|
1267 |
98 |
unneback |
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
|
1268 |
97 |
unneback |
`define SIZE2WIDTH wbm_burst_size
|
1269 |
|
|
localparam wbm_burst_width `SIZE2WIDTH_EXPR
|
1270 |
|
|
`undef SIZE2WIDTH
|
1271 |
|
|
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
|
1272 |
|
|
`define SIZE2WIDTH nr_of_wbm_burst
|
1273 |
|
|
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
|
1274 |
|
|
`undef SIZE2WIDTH
|
1275 |
100 |
unneback |
|
1276 |
96 |
unneback |
input [dw_s-1:0] wbs_dat_i;
|
1277 |
|
|
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
|
1278 |
98 |
unneback |
input [dw_s/8-1:0] wbs_sel_i;
|
1279 |
96 |
unneback |
input [2:0] wbs_cti_i;
|
1280 |
|
|
input [1:0] wbs_bte_i;
|
1281 |
98 |
unneback |
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
1282 |
96 |
unneback |
output [dw_s-1:0] wbs_dat_o;
|
1283 |
|
|
output wbs_ack_o;
|
1284 |
103 |
unneback |
output wbs_stall_o;
|
1285 |
96 |
unneback |
input wbs_clk, wbs_rst;
|
1286 |
|
|
|
1287 |
|
|
output [dw_m-1:0] wbm_dat_o;
|
1288 |
|
|
output [aw_m-1:0] wbm_adr_o;
|
1289 |
|
|
output [dw_m/8-1:0] wbm_sel_o;
|
1290 |
|
|
output [2:0] wbm_cti_o;
|
1291 |
|
|
output [1:0] wbm_bte_o;
|
1292 |
98 |
unneback |
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
|
1293 |
96 |
unneback |
input [dw_m-1:0] wbm_dat_i;
|
1294 |
|
|
input wbm_ack_i;
|
1295 |
|
|
input wbm_stall_i;
|
1296 |
|
|
input wbm_clk, wbm_rst;
|
1297 |
|
|
|
1298 |
100 |
unneback |
wire valid, dirty, hit;
|
1299 |
97 |
unneback |
wire [aw_tag-1:0] tag;
|
1300 |
|
|
wire tag_mem_we;
|
1301 |
|
|
wire [aw_tag-1:0] wbs_adr_tag;
|
1302 |
|
|
wire [aw_slot-1:0] wbs_adr_slot;
|
1303 |
98 |
unneback |
wire [aw_offset-1:0] wbs_adr_word;
|
1304 |
|
|
wire [aw_s-1:0] wbs_adr;
|
1305 |
96 |
unneback |
|
1306 |
97 |
unneback |
reg [1:0] state;
|
1307 |
|
|
localparam idle = 2'h0;
|
1308 |
|
|
localparam rdwr = 2'h1;
|
1309 |
|
|
localparam push = 2'h2;
|
1310 |
|
|
localparam pull = 2'h3;
|
1311 |
|
|
wire eoc;
|
1312 |
103 |
unneback |
wire we;
|
1313 |
97 |
unneback |
|
1314 |
|
|
// cdc
|
1315 |
|
|
wire done, mem_alert, mem_done;
|
1316 |
|
|
|
1317 |
98 |
unneback |
// wbm side
|
1318 |
|
|
reg [aw_m-1:0] wbm_radr;
|
1319 |
|
|
reg [aw_m-1:0] wbm_wadr;
|
1320 |
100 |
unneback |
wire [aw_slot-1:0] wbm_adr;
|
1321 |
98 |
unneback |
wire wbm_radr_cke, wbm_wadr_cke;
|
1322 |
|
|
|
1323 |
100 |
unneback |
reg [2:0] phase;
|
1324 |
|
|
// phase = {we,stb,cyc}
|
1325 |
|
|
localparam wbm_wait = 3'b000;
|
1326 |
|
|
localparam wbm_wr = 3'b111;
|
1327 |
|
|
localparam wbm_wr_drain = 3'b101;
|
1328 |
|
|
localparam wbm_rd = 3'b011;
|
1329 |
|
|
localparam wbm_rd_drain = 3'b001;
|
1330 |
98 |
unneback |
|
1331 |
97 |
unneback |
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
1332 |
|
|
|
1333 |
100 |
unneback |
generate
|
1334 |
|
|
if (valid_mem==0) begin : no_valid_mem
|
1335 |
|
|
assign valid = 1'b1;
|
1336 |
|
|
end else begin : valid_mem_inst
|
1337 |
|
|
`define MODULE dpram_1r1w
|
1338 |
97 |
unneback |
`BASE`MODULE
|
1339 |
100 |
unneback |
# ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
|
1340 |
|
|
valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
|
1341 |
|
|
.q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
|
1342 |
97 |
unneback |
`undef MODULE
|
1343 |
100 |
unneback |
end
|
1344 |
|
|
endgenerate
|
1345 |
97 |
unneback |
|
1346 |
100 |
unneback |
`define MODULE dpram_1r1w
|
1347 |
|
|
`BASE`MODULE
|
1348 |
|
|
# ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
|
1349 |
|
|
tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
|
1350 |
|
|
.q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
|
1351 |
|
|
assign hit = wbs_adr_tag == tag;
|
1352 |
|
|
`undef MODULE
|
1353 |
|
|
|
1354 |
|
|
`define MODULE dpram_1r2w
|
1355 |
|
|
`BASE`MODULE
|
1356 |
|
|
# ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
|
1357 |
|
|
dirty_mem (
|
1358 |
|
|
.d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
|
1359 |
|
|
.d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
|
1360 |
|
|
`undef MODULE
|
1361 |
|
|
|
1362 |
103 |
unneback |
generate
|
1363 |
|
|
if (wbs_mode=="B3") begin : inst_b3
|
1364 |
96 |
unneback |
`define MODULE wb_adr_inc
|
1365 |
100 |
unneback |
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
|
1366 |
|
|
.cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
|
1367 |
|
|
.stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
|
1368 |
96 |
unneback |
.cti_i(wbs_cti_i),
|
1369 |
|
|
.bte_i(wbs_bte_i),
|
1370 |
|
|
.adr_i(wbs_adr_i),
|
1371 |
97 |
unneback |
.we_i (wbs_we_i),
|
1372 |
96 |
unneback |
.ack_o(wbs_ack_o),
|
1373 |
97 |
unneback |
.adr_o(wbs_adr),
|
1374 |
100 |
unneback |
.clk(wbs_clk),
|
1375 |
|
|
.rst(wbs_rst));
|
1376 |
96 |
unneback |
`undef MODULE
|
1377 |
103 |
unneback |
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
1378 |
|
|
assign we = wbs_cyc_i & wbs_we_i & wbs_ack_o;
|
1379 |
|
|
end else if (wbs_mode=="B4") begin : inst_b4
|
1380 |
|
|
end
|
1381 |
96 |
unneback |
|
1382 |
103 |
unneback |
endgenerate
|
1383 |
|
|
|
1384 |
97 |
unneback |
`define MODULE dpram_be_2r2w
|
1385 |
|
|
`BASE`MODULE
|
1386 |
100 |
unneback |
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
|
1387 |
103 |
unneback |
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
1388 |
100 |
unneback |
.d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
1389 |
97 |
unneback |
`undef MODULE
|
1390 |
|
|
|
1391 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
1392 |
|
|
if (wbs_rst)
|
1393 |
98 |
unneback |
state <= idle;
|
1394 |
97 |
unneback |
else
|
1395 |
|
|
case (state)
|
1396 |
|
|
idle:
|
1397 |
|
|
if (wbs_cyc_i)
|
1398 |
|
|
state <= rdwr;
|
1399 |
|
|
rdwr:
|
1400 |
100 |
unneback |
casex ({valid, hit, dirty, eoc})
|
1401 |
|
|
4'b0xxx: state <= pull;
|
1402 |
|
|
4'b11x1: state <= idle;
|
1403 |
|
|
4'b101x: state <= push;
|
1404 |
|
|
4'b100x: state <= pull;
|
1405 |
|
|
endcase
|
1406 |
97 |
unneback |
push:
|
1407 |
|
|
if (done)
|
1408 |
|
|
state <= rdwr;
|
1409 |
|
|
pull:
|
1410 |
|
|
if (done)
|
1411 |
|
|
state <= rdwr;
|
1412 |
|
|
default: state <= idle;
|
1413 |
|
|
endcase
|
1414 |
|
|
|
1415 |
|
|
// cdc
|
1416 |
|
|
generate
|
1417 |
|
|
if (async==1) begin : cdc0
|
1418 |
|
|
`define MODULE cdc
|
1419 |
100 |
unneback |
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
|
1420 |
97 |
unneback |
`undef MODULE
|
1421 |
|
|
end
|
1422 |
|
|
else begin : nocdc
|
1423 |
100 |
unneback |
assign mem_alert = state==rdwr & (!valid | !hit);
|
1424 |
97 |
unneback |
assign done = mem_done;
|
1425 |
|
|
end
|
1426 |
|
|
endgenerate
|
1427 |
|
|
|
1428 |
|
|
// FSM generating a number of burts 4 cycles
|
1429 |
|
|
// actual number depends on data width ratio
|
1430 |
|
|
// nr_of_wbm_burst
|
1431 |
101 |
unneback |
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt_rw, cnt_ack;
|
1432 |
97 |
unneback |
|
1433 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
1434 |
|
|
if (wbm_rst)
|
1435 |
100 |
unneback |
cnt_rw <= {wbm_burst_width{1'b0}};
|
1436 |
97 |
unneback |
else
|
1437 |
100 |
unneback |
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
1438 |
|
|
cnt_rw <= cnt_rw + 1;
|
1439 |
97 |
unneback |
|
1440 |
98 |
unneback |
always @ (posedge wbm_clk or posedge wbm_rst)
|
1441 |
|
|
if (wbm_rst)
|
1442 |
100 |
unneback |
cnt_ack <= {wbm_burst_width{1'b0}};
|
1443 |
98 |
unneback |
else
|
1444 |
100 |
unneback |
if (wbm_ack_i)
|
1445 |
|
|
cnt_ack <= cnt_ack + 1;
|
1446 |
97 |
unneback |
|
1447 |
100 |
unneback |
generate
|
1448 |
101 |
unneback |
if (nr_of_wbm_burst==1) begin : one_burst
|
1449 |
100 |
unneback |
|
1450 |
98 |
unneback |
always @ (posedge wbm_clk or posedge wbm_rst)
|
1451 |
|
|
if (wbm_rst)
|
1452 |
|
|
phase <= wbm_wait;
|
1453 |
|
|
else
|
1454 |
|
|
case (phase)
|
1455 |
|
|
wbm_wait:
|
1456 |
|
|
if (mem_alert)
|
1457 |
100 |
unneback |
if (state==push)
|
1458 |
|
|
phase <= wbm_wr;
|
1459 |
|
|
else
|
1460 |
|
|
phase <= wbm_rd;
|
1461 |
98 |
unneback |
wbm_wr:
|
1462 |
100 |
unneback |
if (&cnt_rw)
|
1463 |
|
|
phase <= wbm_wr_drain;
|
1464 |
|
|
wbm_wr_drain:
|
1465 |
|
|
if (&cnt_ack)
|
1466 |
98 |
unneback |
phase <= wbm_rd;
|
1467 |
|
|
wbm_rd:
|
1468 |
100 |
unneback |
if (&cnt_rw)
|
1469 |
|
|
phase <= wbm_rd_drain;
|
1470 |
|
|
wbm_rd_drain:
|
1471 |
|
|
if (&cnt_ack)
|
1472 |
|
|
phase <= wbm_wait;
|
1473 |
98 |
unneback |
default: phase <= wbm_wait;
|
1474 |
|
|
endcase
|
1475 |
|
|
|
1476 |
100 |
unneback |
end else begin : multiple_burst
|
1477 |
|
|
|
1478 |
101 |
unneback |
always @ (posedge wbm_clk or posedge wbm_rst)
|
1479 |
|
|
if (wbm_rst)
|
1480 |
|
|
phase <= wbm_wait;
|
1481 |
|
|
else
|
1482 |
|
|
case (phase)
|
1483 |
|
|
wbm_wait:
|
1484 |
|
|
if (mem_alert)
|
1485 |
|
|
if (state==push)
|
1486 |
|
|
phase <= wbm_wr;
|
1487 |
|
|
else
|
1488 |
|
|
phase <= wbm_rd;
|
1489 |
|
|
wbm_wr:
|
1490 |
|
|
if (&cnt_rw[wbm_burst_width-1:0])
|
1491 |
|
|
phase <= wbm_wr_drain;
|
1492 |
|
|
wbm_wr_drain:
|
1493 |
|
|
if (&cnt_ack)
|
1494 |
|
|
phase <= wbm_rd;
|
1495 |
|
|
else if (&cnt_ack[wbm_burst_width-1:0])
|
1496 |
|
|
phase <= wbm_wr;
|
1497 |
|
|
wbm_rd:
|
1498 |
|
|
if (&cnt_rw[wbm_burst_width-1:0])
|
1499 |
|
|
phase <= wbm_rd_drain;
|
1500 |
|
|
wbm_rd_drain:
|
1501 |
|
|
if (&cnt_ack)
|
1502 |
|
|
phase <= wbm_wait;
|
1503 |
|
|
else if (&cnt_ack[wbm_burst_width-1:0])
|
1504 |
|
|
phase <= wbm_rd;
|
1505 |
|
|
default: phase <= wbm_wait;
|
1506 |
|
|
endcase
|
1507 |
100 |
unneback |
|
1508 |
101 |
unneback |
|
1509 |
100 |
unneback |
end
|
1510 |
|
|
endgenerate
|
1511 |
|
|
|
1512 |
101 |
unneback |
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
|
1513 |
100 |
unneback |
|
1514 |
|
|
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
|
1515 |
|
|
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
|
1516 |
|
|
assign wbm_sel_o = {dw_m/8{1'b1}};
|
1517 |
|
|
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
|
1518 |
98 |
unneback |
assign wbm_bte_o = bte;
|
1519 |
100 |
unneback |
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
|
1520 |
98 |
unneback |
|
1521 |
96 |
unneback |
endmodule
|
1522 |
|
|
`endif
|
1523 |
103 |
unneback |
|
1524 |
|
|
`ifdef WB_AVALON_BRIDGE
|
1525 |
|
|
// Wishbone to avalon bridge supporting one type of burst transfer only
|
1526 |
|
|
// intended use is together with cache above
|
1527 |
|
|
// WB B4 -> pipelined avalon
|
1528 |
|
|
`define MODULE wb_avalon_bridge
|
1529 |
|
|
module `BASE`MODULE (
|
1530 |
|
|
`undef MODULE
|
1531 |
|
|
// wishbone slave side
|
1532 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
1533 |
|
|
// avalon master side
|
1534 |
|
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
|
1535 |
|
|
// common
|
1536 |
|
|
clk, rst);
|
1537 |
|
|
|
1538 |
|
|
parameter adr_width = 30;
|
1539 |
|
|
parameter dat_width = 32;
|
1540 |
|
|
parameter burst_size = 4;
|
1541 |
|
|
|
1542 |
|
|
input [dat_width-1:0] wbs_dat_i;
|
1543 |
|
|
input [adr_width-1:0] wbs_adr_i;
|
1544 |
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
1545 |
|
|
input [1:0] wbs_bte_i;
|
1546 |
|
|
input [2:0] wbs_cti_i;
|
1547 |
|
|
input wbs_we_i;
|
1548 |
|
|
input wbs_cyc_i;
|
1549 |
|
|
input wbs_stb_i;
|
1550 |
|
|
output [dat_width:0] wbs_dat_o;
|
1551 |
|
|
output wbs_ack_o;
|
1552 |
|
|
output wbs_stall_o;
|
1553 |
|
|
|
1554 |
|
|
input [dat_width-1:0] readdata;
|
1555 |
|
|
input readdatavalid;
|
1556 |
|
|
output [dat_width-1:0] writedata;
|
1557 |
|
|
output [adr_width-1:0] address;
|
1558 |
|
|
output [dat_width/8-1:0] be;
|
1559 |
|
|
output write;
|
1560 |
|
|
output read;
|
1561 |
|
|
output beginbursttransfer;
|
1562 |
|
|
output [3:0] burstcount;
|
1563 |
|
|
input waitrequest;
|
1564 |
|
|
input clk, rst;
|
1565 |
|
|
|
1566 |
|
|
reg last_cyc_idle_or_eoc;
|
1567 |
|
|
|
1568 |
|
|
reg [3:0] cnt;
|
1569 |
|
|
always @ (posedge clk or posedge rst)
|
1570 |
|
|
if (rst)
|
1571 |
|
|
cnt <= 4'h0;
|
1572 |
|
|
else
|
1573 |
|
|
if (beginbursttransfer & waitrequest)
|
1574 |
|
|
cnt <= burst_size - 1;
|
1575 |
|
|
else if (beginbursttransfer & !waitrequest)
|
1576 |
|
|
cnt <= burst_size - 2;
|
1577 |
|
|
else if (wbs_ack_o)
|
1578 |
|
|
cnt <= cnt - 1;
|
1579 |
|
|
|
1580 |
|
|
reg wr_ack;
|
1581 |
|
|
always @ (posedge clk or posedge rst)
|
1582 |
|
|
if (rst)
|
1583 |
|
|
wr_ack <= 1'b0;
|
1584 |
|
|
else
|
1585 |
|
|
wr_ack <= (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
|
1586 |
|
|
|
1587 |
|
|
// to avalon
|
1588 |
|
|
assign writedata = wbs_dat_i;
|
1589 |
|
|
assign address = wbs_adr_i;
|
1590 |
|
|
assign be = wbs_sel_i;
|
1591 |
|
|
assign write = cnt==(burst_size-1) & wbs_cyc_i & wbs_we_i;
|
1592 |
|
|
assign read = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
|
1593 |
|
|
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
|
1594 |
|
|
assign burstcount = burst_size;
|
1595 |
|
|
|
1596 |
|
|
// to wishbone
|
1597 |
|
|
assign wbs_dat_o = readdata;
|
1598 |
|
|
assign wbs_ack_o = wr_ack | readdatavalid;
|
1599 |
|
|
assign wbs_stall_o = waitrequest;
|
1600 |
|
|
|
1601 |
|
|
endmodule
|
1602 |
|
|
`endif
|
1603 |
|
|
|
1604 |
|
|
`ifdef WB_AVALON_MEM_CACHE
|
1605 |
|
|
`define MODULE wb_avalon_mem_cache
|
1606 |
|
|
module `BASE`MODULE (
|
1607 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
|
1608 |
|
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
|
1609 |
|
|
);
|
1610 |
|
|
`undef MODULE
|
1611 |
|
|
|
1612 |
|
|
// wishbone
|
1613 |
|
|
parameter wb_dat_width = 32;
|
1614 |
|
|
parameter wb_adr_width = 22;
|
1615 |
|
|
parameter wb_max_burst_width = 4;
|
1616 |
|
|
parameter wb_mode = "B4";
|
1617 |
|
|
// avalon
|
1618 |
|
|
parameter avalon_dat_width = 32;
|
1619 |
121 |
unneback |
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
|
1620 |
122 |
unneback |
localparam avalon_adr_width =
|
1621 |
|
|
(wb_dat_width==avalon_dat_width) ? wb_adr_width :
|
1622 |
|
|
(wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
|
1623 |
|
|
(wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
|
1624 |
|
|
(wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
|
1625 |
|
|
(wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
|
1626 |
|
|
(wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
|
1627 |
|
|
(wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
|
1628 |
|
|
(wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
|
1629 |
|
|
(wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
|
1630 |
|
|
(wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
|
1631 |
123 |
unneback |
(wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
|
1632 |
103 |
unneback |
parameter avalon_burst_size = 4;
|
1633 |
|
|
// cache
|
1634 |
|
|
parameter async = 1;
|
1635 |
|
|
parameter nr_of_ways = 1;
|
1636 |
|
|
parameter aw_offset = 4;
|
1637 |
|
|
parameter aw_slot = 10;
|
1638 |
|
|
parameter valid_mem = 1;
|
1639 |
|
|
// shadow RAM
|
1640 |
|
|
parameter shadow_ram = 0;
|
1641 |
|
|
parameter shadow_ram_adr_width = 10;
|
1642 |
|
|
parameter shadow_ram_size = 1024;
|
1643 |
|
|
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
|
1644 |
|
|
parameter shadow_ram_file = "vl_ram.v";
|
1645 |
|
|
|
1646 |
|
|
input [wb_dat_width-1:0] wbs_dat_i;
|
1647 |
|
|
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
|
1648 |
|
|
input [wb_dat_width/8-1:0] wbs_sel_i;
|
1649 |
|
|
input [2:0] wbs_cti_i;
|
1650 |
|
|
input [1:0] wbs_bte_i;
|
1651 |
|
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
1652 |
|
|
output [wb_dat_width-1:0] wbs_dat_o;
|
1653 |
|
|
output wbs_ack_o;
|
1654 |
|
|
output wbs_stall_o;
|
1655 |
|
|
input wbs_clk, wbs_rst;
|
1656 |
|
|
|
1657 |
|
|
input [avalon_dat_width-1:0] readdata;
|
1658 |
|
|
input readdatavalid;
|
1659 |
|
|
output [avalon_dat_width-1:0] writedata;
|
1660 |
|
|
output [avalon_adr_width-1:0] address;
|
1661 |
|
|
output [avalon_dat_width/8-1:0] be;
|
1662 |
|
|
output write;
|
1663 |
|
|
output read;
|
1664 |
|
|
output beginbursttransfer;
|
1665 |
|
|
output [3:0] burstcount;
|
1666 |
|
|
input waitrequest;
|
1667 |
|
|
input clk, rst;
|
1668 |
|
|
|
1669 |
|
|
`define DAT_WIDTH wb_dat_width
|
1670 |
|
|
`define ADR_WIDTH wb_adr_width
|
1671 |
|
|
`define WB wb1
|
1672 |
|
|
`include "wb_wires.v"
|
1673 |
|
|
`define WB wb2
|
1674 |
|
|
`include "wb_wires.v"
|
1675 |
|
|
`undef DAT_WIDTH
|
1676 |
|
|
`undef ADR_WIDTH
|
1677 |
|
|
|
1678 |
|
|
`define MODULE wb_shadow_ram
|
1679 |
|
|
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
|
1680 |
120 |
unneback |
.shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
|
1681 |
103 |
unneback |
.main_mem_adr_width(wb_adr_width))
|
1682 |
|
|
shadow_ram0 (
|
1683 |
|
|
.wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
|
1684 |
|
|
.wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
|
1685 |
|
|
.wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
|
1686 |
|
|
.wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
|
1687 |
|
|
.wb_clk(wbs_clk), .wb_rst(wbs_rst));
|
1688 |
|
|
`undef MODULE
|
1689 |
|
|
|
1690 |
|
|
`define MODULE wb_cache
|
1691 |
|
|
`BASE`MODULE
|
1692 |
|
|
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
|
1693 |
|
|
cache0 (
|
1694 |
|
|
.wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
|
1695 |
|
|
.wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
|
1696 |
|
|
.wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
|
1697 |
|
|
.wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
|
1698 |
|
|
`undef MODULE
|
1699 |
|
|
|
1700 |
|
|
`define MODULE wb_avalon_bridge
|
1701 |
|
|
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
|
1702 |
|
|
bridge0 (
|
1703 |
|
|
// wishbone slave side
|
1704 |
|
|
.wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
|
1705 |
|
|
.wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
|
1706 |
|
|
// avalon master side
|
1707 |
|
|
.readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
|
1708 |
|
|
// common
|
1709 |
|
|
.clk(clk), .rst(rst));
|
1710 |
|
|
`undef MODULE
|
1711 |
|
|
|
1712 |
|
|
endmodule
|
1713 |
|
|
`endif
|
1714 |
104 |
unneback |
|
1715 |
|
|
`ifdef WB_SDR_SDRAM
|
1716 |
|
|
`define MODULE wb_sdr_sdram
|
1717 |
|
|
module `BASE`MODULE (
|
1718 |
|
|
`undef MODULE
|
1719 |
|
|
// wisbone i/f
|
1720 |
|
|
dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o
|
1721 |
|
|
// SDR SDRAM
|
1722 |
|
|
ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
|
1723 |
|
|
// system
|
1724 |
|
|
clk, rst);
|
1725 |
|
|
|
1726 |
|
|
// external data bus size
|
1727 |
|
|
parameter dat_size = 16;
|
1728 |
|
|
// memory geometry parameters
|
1729 |
|
|
parameter ba_size = `SDR_BA_SIZE;
|
1730 |
|
|
parameter row_size = `SDR_ROW_SIZE;
|
1731 |
|
|
parameter col_size = `SDR_COL_SIZE;
|
1732 |
|
|
parameter cl = 2;
|
1733 |
|
|
// memory timing parameters
|
1734 |
|
|
parameter tRFC = 9;
|
1735 |
|
|
parameter tRP = 2;
|
1736 |
|
|
parameter tRCD = 2;
|
1737 |
|
|
parameter tMRD = 2;
|
1738 |
|
|
|
1739 |
|
|
// LMR
|
1740 |
|
|
// [12:10] reserved
|
1741 |
|
|
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
|
1742 |
|
|
// [8:7] OP Mode, 2'b00
|
1743 |
|
|
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
|
1744 |
|
|
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
|
1745 |
|
|
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
|
1746 |
|
|
localparam init_wb = 1'b1;
|
1747 |
|
|
localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
|
1748 |
|
|
localparam init_bt = 1'b0;
|
1749 |
|
|
localparam init_bl = 3'b000;
|
1750 |
|
|
|
1751 |
|
|
input [dat_size:0] dat_i;
|
1752 |
|
|
input [ba_size+col_size+row_size-1:0] adr_i;
|
1753 |
|
|
input [dat_size/8-1:0] sel_i;
|
1754 |
|
|
input we_i, cyc_i, stb_i;
|
1755 |
|
|
output [dat_size-1:0] dat_o;
|
1756 |
|
|
output ack_o;
|
1757 |
|
|
output reg stall_o;
|
1758 |
|
|
|
1759 |
|
|
output [ba_size-1:0] ba;
|
1760 |
|
|
output reg [12:0] a;
|
1761 |
|
|
output reg [2:0] cmd; // {ras,cas,we}
|
1762 |
|
|
output cke, cs_n;
|
1763 |
|
|
output reg [dat_size/8-1:0] dqm;
|
1764 |
|
|
output [dat_size-1:0] dq_o;
|
1765 |
|
|
output reg dq_oe;
|
1766 |
|
|
input [dat_size-1:0] dq_i;
|
1767 |
|
|
|
1768 |
|
|
input clk, rst;
|
1769 |
|
|
|
1770 |
|
|
wire [ba_size-1:0] bank;
|
1771 |
|
|
wire [row_size-1:0] row;
|
1772 |
|
|
wire [col_size-1:0] col;
|
1773 |
|
|
wire [0:31] shreg;
|
1774 |
|
|
wire ref_cnt_zero;
|
1775 |
|
|
reg refresh_req;
|
1776 |
|
|
|
1777 |
|
|
wire ack_rd, rd_ack_emptyflag;
|
1778 |
|
|
wire ack_wr;
|
1779 |
|
|
|
1780 |
|
|
// to keep track of open rows per bank
|
1781 |
|
|
reg [row_size-1:0] open_row[0:3];
|
1782 |
|
|
reg [0:3] open_ba;
|
1783 |
|
|
reg current_bank_closed, current_row_open;
|
1784 |
|
|
|
1785 |
|
|
parameter rfr_length = 10;
|
1786 |
|
|
parameter rfr_wrap_value = 1010;
|
1787 |
|
|
|
1788 |
|
|
parameter [2:0] cmd_nop = 3'b111,
|
1789 |
|
|
cmd_act = 3'b011,
|
1790 |
|
|
cmd_rd = 3'b101,
|
1791 |
|
|
cmd_wr = 3'b100,
|
1792 |
|
|
cmd_pch = 3'b010,
|
1793 |
|
|
cmd_rfr = 3'b001,
|
1794 |
|
|
cmd_lmr = 3'b000;
|
1795 |
|
|
|
1796 |
|
|
// ctrl FSM
|
1797 |
|
|
`define FSM_INIT 3'b000
|
1798 |
|
|
`define FSM_IDLE 3'b001
|
1799 |
|
|
`define FSM_RFR 3'b010
|
1800 |
|
|
`define FSM_ADR 3'b011
|
1801 |
|
|
`define FSM_PCH 3'b100
|
1802 |
|
|
`define FSM_ACT 3'b101
|
1803 |
|
|
`define FSM_RW 3'b111
|
1804 |
|
|
|
1805 |
|
|
assign cke = 1'b1;
|
1806 |
|
|
assign cs_n = 1'b0;
|
1807 |
|
|
|
1808 |
|
|
reg [2:0] state, next;
|
1809 |
|
|
|
1810 |
|
|
function [12:0] a10_fix;
|
1811 |
|
|
input [col_size-1:0] a;
|
1812 |
|
|
integer i;
|
1813 |
|
|
begin
|
1814 |
|
|
for (i=0;i<13;i=i+1) begin
|
1815 |
|
|
if (i<10)
|
1816 |
|
|
if (i<col_size)
|
1817 |
|
|
a10_fix[i] = a[i];
|
1818 |
|
|
else
|
1819 |
|
|
a10_fix[i] = 1'b0;
|
1820 |
|
|
else if (i==10)
|
1821 |
|
|
a10_fix[i] = 1'b0;
|
1822 |
|
|
else
|
1823 |
|
|
if (i<col_size)
|
1824 |
|
|
a10_fix[i] = a[i-1];
|
1825 |
|
|
else
|
1826 |
|
|
a10_fix[i] = 1'b0;
|
1827 |
|
|
end
|
1828 |
|
|
end
|
1829 |
|
|
endfunction
|
1830 |
|
|
|
1831 |
|
|
assign {bank,row,col} = adr_i;
|
1832 |
|
|
|
1833 |
|
|
always @ (posedge clk or posedge rst)
|
1834 |
|
|
if (rst)
|
1835 |
|
|
state <= `FSM_INIT;
|
1836 |
|
|
else
|
1837 |
|
|
state <= next;
|
1838 |
|
|
|
1839 |
|
|
always @*
|
1840 |
|
|
begin
|
1841 |
|
|
next = state;
|
1842 |
|
|
case (state)
|
1843 |
|
|
`FSM_INIT:
|
1844 |
|
|
if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
|
1845 |
|
|
`FSM_IDLE:
|
1846 |
|
|
if (refresh_req) next = `FSM_RFR;
|
1847 |
|
|
else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
|
1848 |
|
|
`FSM_RFR:
|
1849 |
|
|
if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
|
1850 |
|
|
`FSM_ADR:
|
1851 |
|
|
if (current_bank_closed) next = `FSM_ACT;
|
1852 |
|
|
else if (current_row_open) next = `FSM_RW;
|
1853 |
|
|
else next = `FSM_PCH;
|
1854 |
|
|
`FSM_PCH:
|
1855 |
|
|
if (shreg[tRP]) next = `FSM_ACT;
|
1856 |
|
|
`FSM_ACT:
|
1857 |
|
|
if (shreg[tRCD]) next = `FSM_RW;
|
1858 |
|
|
`FSM_RW:
|
1859 |
|
|
if (!stb_i) next = `FSM_IDLE;
|
1860 |
|
|
endcase
|
1861 |
|
|
end
|
1862 |
|
|
|
1863 |
|
|
// counter
|
1864 |
|
|
`define MODULE cnt_shreg_ce_clear
|
1865 |
|
|
`VLBASE`MODULE # ( .length(32))
|
1866 |
|
|
`undef MODULE
|
1867 |
|
|
cnt0 (
|
1868 |
|
|
.clear(state!=next),
|
1869 |
|
|
.q(shreg),
|
1870 |
|
|
.rst(rst),
|
1871 |
|
|
.clk(clk));
|
1872 |
|
|
|
1873 |
|
|
// ba, a, cmd
|
1874 |
|
|
// outputs dependent on state vector
|
1875 |
|
|
always @ (*)
|
1876 |
|
|
begin
|
1877 |
|
|
{a,cmd} = {13'd0,cmd_nop};
|
1878 |
|
|
dqm = 2'b11;
|
1879 |
|
|
dq_oe = 1'b0;
|
1880 |
|
|
stall_o = 1'b1;
|
1881 |
|
|
case (state)
|
1882 |
|
|
`FSM_INIT:
|
1883 |
|
|
if (shreg[3]) begin
|
1884 |
|
|
{a,cmd} = {13'b0010000000000, cmd_pch};
|
1885 |
|
|
end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
|
1886 |
|
|
{a,cmd} = {13'd0, cmd_rfr};
|
1887 |
|
|
else if (shreg[3+tRP+tRFC+tRFC])
|
1888 |
|
|
{a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
|
1889 |
|
|
`FSM_RFR:
|
1890 |
|
|
if (shreg[0])
|
1891 |
|
|
{a,cmd} = {13'b0010000000000, cmd_pch};
|
1892 |
|
|
else if (shreg[tRP])
|
1893 |
|
|
{a,cmd} = {13'd0, cmd_rfr};
|
1894 |
|
|
`FSM_PCH:
|
1895 |
|
|
if (shreg[0])
|
1896 |
|
|
{a,cmd} = {13'd0,cmd_pch};
|
1897 |
|
|
`FSM_ACT:
|
1898 |
|
|
if (shreg[0])
|
1899 |
|
|
{a[row_size-1:0],cmd} = {row,cmd_act};
|
1900 |
|
|
`FSM_RW:
|
1901 |
|
|
begin
|
1902 |
|
|
if (we_i)
|
1903 |
|
|
cmd = cmd_wr;
|
1904 |
|
|
else
|
1905 |
|
|
cmd = cmd_rd;
|
1906 |
|
|
if (we_i)
|
1907 |
|
|
dqm = ~sel_i;
|
1908 |
|
|
else
|
1909 |
|
|
dqm = 2'b00;
|
1910 |
|
|
if (we_i)
|
1911 |
|
|
dq_oe = 1'b1;
|
1912 |
|
|
a = a10_fix(col);
|
1913 |
|
|
stall_o = 1'b1;
|
1914 |
|
|
end
|
1915 |
|
|
endcase
|
1916 |
|
|
end
|
1917 |
|
|
|
1918 |
|
|
assign ba = bank;
|
1919 |
|
|
|
1920 |
|
|
// precharge individual bank A10=0
|
1921 |
|
|
// precharge all bank A10=1
|
1922 |
|
|
genvar i;
|
1923 |
|
|
generate
|
1924 |
|
|
for (i=0;i<2<<ba_size-1;i=i+1) begin
|
1925 |
|
|
|
1926 |
|
|
always @ (posedge clk or posedge rst)
|
1927 |
|
|
if (rst)
|
1928 |
|
|
{open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
|
1929 |
|
|
else
|
1930 |
|
|
if (cmd==cmd_pch & (a[10] | bank==i))
|
1931 |
|
|
open_ba[i] <= 1'b0;
|
1932 |
|
|
else if (cmd==cmd_act & bank==i)
|
1933 |
|
|
{open_ba[i],open_row[i]} <= {1'b1,row};
|
1934 |
|
|
|
1935 |
|
|
end
|
1936 |
|
|
endgenerate
|
1937 |
|
|
|
1938 |
|
|
// bank and row open ?
|
1939 |
|
|
always @ (posedge clk or posedge rst)
|
1940 |
|
|
if (rst)
|
1941 |
|
|
{current_bank_closed, current_row_open} <= {1'b1, 1'b0};
|
1942 |
|
|
else
|
1943 |
|
|
{current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
|
1944 |
|
|
|
1945 |
|
|
// refresh counter
|
1946 |
|
|
`define MODULE cnt_lfsr_zq
|
1947 |
|
|
`VLBASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
|
1948 |
|
|
`undef MODULE
|
1949 |
|
|
|
1950 |
|
|
always @ (posedge clk or posedge rst)
|
1951 |
|
|
if (rst)
|
1952 |
|
|
refresh_req <= 1'b0;
|
1953 |
|
|
else
|
1954 |
|
|
if (ref_cnt_zero)
|
1955 |
|
|
refresh_req <= 1'b1;
|
1956 |
|
|
else if (state==`FSM_RFR)
|
1957 |
|
|
refresh_req <= 1'b0;
|
1958 |
|
|
|
1959 |
|
|
assign dat_o = dq_i;
|
1960 |
|
|
|
1961 |
|
|
assign ack_wr = (state==`FSM_RW & count0 & we_i);
|
1962 |
|
|
`define MODULE delay_emptyflag
|
1963 |
|
|
`VLBASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
|
1964 |
|
|
`undef MODULE
|
1965 |
|
|
assign ack_o = ack_rd | ack_wr;
|
1966 |
|
|
|
1967 |
|
|
assign dq_o = dat_i;
|
1968 |
|
|
|
1969 |
|
|
endmodule
|
1970 |
|
|
`endif
|