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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb_wires.v] - Blame information for rev 144

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`define DAT_O _dat_o
`define ADR_O _adr_o
`define SEL_O _sel_o
`define CTI_O _cti_o
`define BTE_O _bte_o
`define WE_O _we_o
`define STB_O _stb_o
`define CYC_O _cyc_o
`define STALL_I _stall_i
`define DAT_I _dat_i
`define ACK_I _ack_i
`ifndef DAT_WIDTH
`define DAT_WIDTH 32
`endif
`ifndef ADR_WIDTH
`define ADR_WIDTH 30
`endif
wire [`DAT_WIDTH-1:0] `WB`DAT_O;
wire [`ADR_WIDTH-1:0] `WB`ADR_O;
wire [`DAT_WIDTH/8-1:0] `WB`SEL_O;
wire [2:0] `WB`CTI_O;
wire [1:0] `WB`BTE_O;
wire `WB`WE_O;
wire `WB`STB_O;
wire `WB`CYC_O;
wire `WB`STALL_I;
wire [`DAT_WIDTH-1:0] `WB`DAT_I;
wire `WB`ACK_I;
`undef WB
`undef DAT_O
`undef ADR_O
`undef SEL_O
`undef CTI_O
`undef BTE_O
`undef WE_O
`undef STB_O
`undef CYC_O
`undef STALL_I
`undef DAT_I
`undef ACK_I

Line No.	Rev	Author	Line
1	103	unneback	`define DAT_O _dat_o
2			`define ADR_O _adr_o
3			`define SEL_O _sel_o
4			`define CTI_O _cti_o
5			`define BTE_O _bte_o
6			`define WE_O _we_o
7			`define STB_O _stb_o
8			`define CYC_O _cyc_o
9			`define STALL_I _stall_i
10			`define DAT_I _dat_i
11			`define ACK_I _ack_i
12			`ifndef DAT_WIDTH
13			`define DAT_WIDTH 32
14			`endif
15			`ifndef ADR_WIDTH
16			`define ADR_WIDTH 30
17			`endif
18			wire [`DAT_WIDTH-1:0] `WB`DAT_O;
19			wire [`ADR_WIDTH-1:0] `WB`ADR_O;
20			wire [`DAT_WIDTH/8-1:0] `WB`SEL_O;
21			wire [2:0] `WB`CTI_O;
22			wire [1:0] `WB`BTE_O;
23			wire `WB`WE_O;
24			wire `WB`STB_O;
25			wire `WB`CYC_O;
26			wire `WB`STALL_I;
27			wire [`DAT_WIDTH-1:0] `WB`DAT_I;
28			wire `WB`ACK_I;
29			`undef WB
30			`undef DAT_O
31			`undef ADR_O
32			`undef SEL_O
33			`undef CTI_O
34			`undef BTE_O
35			`undef WE_O
36			`undef STB_O
37			`undef CYC_O
38			`undef STALL_I
39			`undef DAT_I
40			`undef ACK_I

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb_wires.v] - Blame information for rev 144