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[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench/] [wb1.v] - Blame information for rev 89

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1 9 unneback
 
2
module wb1 (
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  output reg [31:0] adr,
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  output reg [1:0] bte,
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  output reg [2:0] cti,
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  output reg cyc,
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  output reg [31:0] dat,
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  output reg [3:0] sel,
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  output reg stb,
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  output reg we,
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  input wire ack,
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  input wire clk,
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  input wire [31:0] dat_i,
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  input wire reset
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);
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  // state bits
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  parameter
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  state0 = 4'b0000,
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  state1 = 4'b0001,
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  state2 = 4'b0010,
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  state3 = 4'b0011,
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  state4 = 4'b0100,
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  state5 = 4'b0101,
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  state6 = 4'b0110,
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  state7 = 4'b0111,
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  state8 = 4'b1000;
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  reg [3:0] state;
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  reg [3:0] nextstate;
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  // comb always block
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  always @* begin
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    nextstate = state; // default to hold value because implied_loopback is set
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    adr[31:0] = 32'h0; // default
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    bte[1:0] = 2'b00; // default
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    cti[2:0] = 3'b000; // default
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    cyc = 1'b0; // default
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    dat[31:0] = 32'h0; // default
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    sel[3:0] = 4'b1111; // default
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    stb = 1'b0; // default
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    we = 1'b0; // default
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    case (state)
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      state0: begin
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        begin
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          nextstate = state1;
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        end
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      end
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      state1: begin
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        adr[31:0] = 32'h1000;
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        cyc = 1'b1;
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        dat[31:0] = 32'h12345678;
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        stb = 1'b1;
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        we = 1'b1;
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        if (ack) begin
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          nextstate = state2;
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        end
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      end
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      state2: begin
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        adr[31:0] = 32'h1000;
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        cyc = 1'b1;
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        stb = 1'b1;
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        if (ack) begin
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          nextstate = state3;
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        end
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      end
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      state3: begin
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        begin
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          nextstate = state4;
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        end
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      end
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      state4: begin
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        adr[31:0] = 32'h1000;
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        bte[1:0] = 2'b01;
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        cti[2:0] = 3'b010;
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        cyc = 1'b1;
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        stb = 1'b1;
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        if (ack) begin
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          nextstate = state5;
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        end
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      end
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      state5: begin
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        bte[1:0] = 2'b01;
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        cti[2:0] = 3'b010;
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        cyc = 1'b1;
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        stb = 1'b1;
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        if (ack) begin
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          nextstate = state6;
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        end
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      end
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      state6: begin
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        bte[1:0] = 2'b01;
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        cti[2:0] = 3'b010;
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        cyc = 1'b1;
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        stb = 1'b1;
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        if (ack) begin
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          nextstate = state7;
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        end
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      end
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      state7: begin
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        bte[1:0] = 2'b01;
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        cti[2:0] = 3'b111;
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        cyc = 1'b1;
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        stb = 1'b1;
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        if (ack) begin
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          nextstate = state8;
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        end
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      end
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      state8: begin
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      end
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    endcase
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  end
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  // Assign reg'd outputs to state bits
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  // sequential always block
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  always @(posedge clk or posedge reset) begin
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    if (reset)
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      state <= state0;
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    else
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      state <= nextstate;
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  end
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  // This code allows you to see state names in simulation
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  `ifndef SYNTHESIS
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  reg [47:0] statename;
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  always @* begin
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    case (state)
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      state0:
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        statename = "state0";
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      state1:
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        statename = "state1";
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      state2:
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        statename = "state2";
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      state3:
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        statename = "state3";
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      state4:
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        statename = "state4";
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      state5:
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        statename = "state5";
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      state6:
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        statename = "state6";
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      state7:
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        statename = "state7";
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      state8:
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        statename = "state8";
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      default:
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        statename = "XXXXXX";
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    endcase
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  end
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  `endif
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endmodule
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