OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [bench/] [ddr/] [ddr2_parameters.vh] - Blame information for rev 109

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 mikaeljf 
/****************************************************************************************
2 
*
3 
*   Disclaimer   This software code and all associated documentation, comments or other
4 
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
5 
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
6 
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
7 
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
8 
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
9 
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
10 
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
11 
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
12 
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
13 
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
14 
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
15 
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
16 
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
17 
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
18 
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
19 
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
20 
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
21 
*                limitation of liability for consequential or incidental damages, the
22 
*                above limitation may not apply to you.
23 
*
24 
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
25 
*
26 
****************************************************************************************/
27 
 
28 
    // Parameters current with 512Mb datasheet rev N
29 
 
30 
    // Timing parameters based on Speed Grade
31 
 
32 
                                          // SYMBOL UNITS DESCRIPTION
33 
                                          // ------ ----- -----------
34 
`ifdef sg187E
35 
    parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
36 
    parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
37 
    parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
38 
    parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
39 
    parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
40 
    parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
41 
    parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
42 
    parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
43 
    parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
44 
    parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
45 
    parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
46 
    parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
47 
    parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
48 
    parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
49 
    parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
50 
    parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
51 
    parameter TIS              =     125; // tIS    ps    Input Setup Time
52 
    parameter TIH              =     200; // tIH    ps    Input Hold Time
53 
    parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
54 
    parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
55 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
56 
    parameter TRP              =   13125; // tRP    ps    Precharge command period
57 
    parameter TRPA             =   13125; // tRPA   ps    Precharge All period
58 
    parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
59 
    parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
60 
    parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
61 
    parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
62 
    parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
63 
    parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
64 
`else `ifdef sg25E
65 
    parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
66 
    parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
67 
    parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
68 
    parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
69 
    parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
70 
    parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
71 
    parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
72 
    parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
73 
    parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
74 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
75 
    parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
76 
    parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
77 
    parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
78 
    parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
79 
    parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
80 
    parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
81 
    parameter TIS              =     175; // tIS    ps    Input Setup Time
82 
    parameter TIH              =     250; // tIH    ps    Input Hold Time
83 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
84 
    parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
85 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
86 
    parameter TRP              =   12500; // tRP    ps    Precharge command period
87 
    parameter TRPA             =   12500; // tRPA   ps    Precharge All period
88 
    parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
89 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
90 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
91 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
92 
    parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
93 
    parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
94 
`else `ifdef sg25
95 
    parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
96 
    parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
97 
    parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
98 
    parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
99 
    parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
100 
    parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
101 
    parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
102 
    parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
103 
    parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
104 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
105 
    parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
106 
    parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
107 
    parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
108 
    parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
109 
    parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
110 
    parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
111 
    parameter TIS              =     175; // tIS    ps    Input Setup Time
112 
    parameter TIH              =     250; // tIH    ps    Input Hold Time
113 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
114 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
115 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
116 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
117 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
118 
    parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
119 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
120 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
121 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
122 
    parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
123 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
124 
`else `ifdef sg3E
125 
    parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
126 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
127 
    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
128 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
129 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
130 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
131 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
132 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
133 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
134 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
135 
    parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
136 
    parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
137 
    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
138 
    parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
139 
    parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
140 
    parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
141 
    parameter TIS              =     200; // tIS    ps    Input Setup Time
142 
    parameter TIH              =     275; // tIH    ps    Input Hold Time
143 
    parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
144 
    parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
145 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
146 
    parameter TRP              =   12000; // tRP    ps    Precharge command period
147 
    parameter TRPA             =   12000; // tRPA   ps    Precharge All period
148 
    parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
149 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
150 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
151 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
152 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
153 
    parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
154 
`else `ifdef sg3
155 
    parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
156 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
157 
    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
158 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
159 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
160 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
161 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
162 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
163 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
164 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
165 
    parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
166 
    parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
167 
    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
168 
    parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
169 
    parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
170 
    parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
171 
    parameter TIS              =     200; // tIS    ps    Input Setup Time
172 
    parameter TIH              =     275; // tIH    ps    Input Hold Time
173 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
174 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
175 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
176 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
177 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
178 
    parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
179 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
180 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
181 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
182 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
183 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
184 
`else `ifdef sg37E
185 
    parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
186 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
187 
    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
188 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
189 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
190 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
191 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
192 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
193 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
194 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
195 
    parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
196 
    parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
197 
    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
198 
    parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
199 
    parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
200 
    parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
201 
    parameter TIS              =     250; // tIS    ps    Input Setup Time
202 
    parameter TIH              =     375; // tIH    ps    Input Hold Time
203 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
204 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
205 
    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
206 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
207 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
208 
    parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
209 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
210 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
211 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
212 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
213 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
214 
`else `define sg5E
215 
    parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
216 
    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
217 
    parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
218 
    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
219 
    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
220 
    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
221 
    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
222 
    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
223 
    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
224 
    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
225 
    parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
226 
    parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
227 
    parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
228 
    parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
229 
    parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
230 
    parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
231 
    parameter TIS              =     350; // tIS    ps    Input Setup Time
232 
    parameter TIH              =     475; // tIH    ps    Input Hold Time
233 
    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
234 
    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
235 
    parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
236 
    parameter TRP              =   15000; // tRP    ps    Precharge command period
237 
    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
238 
    parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
239 
    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
240 
    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
241 
    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
242 
    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
243 
    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
244 
`endif `endif `endif `endif `endif `endif
245 
 
246 
`ifdef x16
247 
  `ifdef sg187E
248 
    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
249 
  `else `ifdef sg25E
250 
    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
251 
  `else `ifdef sg25
252 
    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
253 
  `else // sg3E, sg3, sg37E, sg5E
254 
    parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
255 
  `endif `endif `endif
256 
`else // x4, x8
257 
  `ifdef sg187E
258 
    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
259 
  `else `ifdef sg25E
260 
    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
261 
  `else `ifdef sg25
262 
    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
263 
  `else // sg3E, sg3, sg37E, sg5E
264 
    parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
265 
  `endif `endif `endif
266 
`endif
267 
 
268 
    // Timing Parameters
269 
 
270 
    // Mode Register
271 
    parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
272 
    parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
273 
    parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
274 
    parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
275 
    parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
276 
    parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
277 
    parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
278 
    parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
279 
    // Clock
280 
    parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
281 
    parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
282 
    parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
283 
    parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
284 
    parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
285 
    // Data
286 
    parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
287 
    parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
288 
    parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
289 
    // Data Strobe
290 
    parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
291 
    parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
292 
    parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
293 
    parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
294 
    parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
295 
    parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
296 
    parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
297 
    // Command and Address
298 
    parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
299 
    parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
300 
    parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
301 
    parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
302 
    parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
303 
    parameter TWR              =   15000; // tWR    ps    Write recovery time
304 
    parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
305 
    parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
306 
    // Refresh
307 
    parameter TRFC_MIN         =  105000; // tRFC   ps    Refresh to Refresh Command interval minimum value
308 
    parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
309 
    // Self Refresh
310 
    parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
311 
    parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
312 
    parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
313 
    // ODT
314 
    parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
315 
    parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
316 
    parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
317 
    parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
318 
    parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
319 
    // Power Down
320 
    parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
321 
 
322 
    // Size Parameters based on Part Width
323 
 
324 
`ifdef x4
325 
    parameter ADDR_BITS        =      14; // Address Bits
326 
    parameter ROW_BITS         =      14; // Number of Address bits
327 
    parameter COL_BITS         =      11; // Number of Column bits
328 
    parameter DM_BITS          =       1; // Number of Data Mask bits
329 
    parameter DQ_BITS          =       4; // Number of Data bits
330 
    parameter DQS_BITS         =       1; // Number of Dqs bits
331 
    parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
332 
`else `ifdef x8
333 
    parameter ADDR_BITS        =      14; // Address Bits
334 
    parameter ROW_BITS         =      14; // Number of Address bits
335 
    parameter COL_BITS         =      10; // Number of Column bits
336 
    parameter DM_BITS          =       1; // Number of Data Mask bits
337 
    parameter DQ_BITS          =       8; // Number of Data bits
338 
    parameter DQS_BITS         =       1; // Number of Dqs bits
339 
    parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
340 
`else `define x16
341 
    parameter ADDR_BITS        =      13; // Address Bits
342 
    parameter ROW_BITS         =      13; // Number of Address bits
343 
    parameter COL_BITS         =      10; // Number of Column bits
344 
    parameter DM_BITS          =       2; // Number of Data Mask bits
345 
    parameter DQ_BITS          =      16; // Number of Data bits
346 
    parameter DQS_BITS         =       2; // Number of Dqs bits
347 
    parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
348 
`endif `endif
349 
 
350 
`ifdef QUAD_RANK
351 
    `define DUAL_RANK // also define DUAL_RANK
352 
    parameter CS_BITS          =       4; // Number of Chip Select Bits
353 
    parameter RANKS            =       4; // Number of Chip Select Bits
354 
`else `ifdef DUAL_RANK
355 
    parameter CS_BITS          =       2; // Number of Chip Select Bits
356 
    parameter RANKS            =       2; // Number of Chip Select Bits
357 
`else
358 
    parameter CS_BITS          =       2; // Number of Chip Select Bits
359 
    parameter RANKS            =       1; // Number of Chip Select Bits
360 
`endif `endif
361 
 
362 
    // Size Parameters
363 
    parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits
364 
    parameter MEM_BITS         =      10; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
365 
    parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
366 
    parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
367 
    parameter BO_BITS          =       2; // the number of Burst Order Bits
368 
 
369 
    // Simulation parameters
370 
    parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
371 
    parameter DEBUG            =       1; // Turn on Debug messages
372 
    parameter BUS_DELAY        =       0; // delay in nanoseconds
373 
    parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
374 
    parameter RANDOM_SEED      = 711689044; //seed value for random generator.
375 
 
376 
    parameter RDQSEN_PRE       =       2; // DQS driving time prior to first read strobe
377 
    parameter RDQSEN_PST       =       1; // DQS driving time after last read strobe
378 
    parameter RDQS_PRE         =       2; // DQS low time prior to first read strobe
379 
    parameter RDQS_PST         =       1; // DQS low time after last valid read strobe
380 
    parameter RDQEN_PRE        =       0; // DQ/DM driving time prior to first read data
381 
    parameter RDQEN_PST        =       0; // DQ/DM driving time after last read data
382 
    parameter WDQS_PRE         =       1; // DQS half clock periods prior to first write strobe
383 
    parameter WDQS_PST         =       1; // DQS half clock periods after last valid write strobe

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.