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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [backend/] [ACTEL/] [TwoPortRAM_256x36/] [TwoPortRAM_256x36.log] - Blame information for rev 8

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 ** Message System Log
 ** Database:
 ** Date:   Thu Jun 25 17:18:45 2009
 
 
****************
Macro Parameters
****************
 
Name                            : TwoPortRAM_256x36
Family                          : ProASIC3
Output Format                   : VERILOG
Type                            : RAM
Write Enable                    : Active High
Read Enable                     : Active High
Reset                           : None
LP                              : None
FF                              : None
Read Clock                      : Rising
Write Clock                     : Rising
Write Depth                     : 256
Write Width                     : 36
Read Depth                      : 256
Read Width                      : 36
RAM Type                        : Two Port
Clocks                          : Independent Read and Write Clocks
Write Mode A                    : Hold Data
Write Mode B                    : Hold Data
Read Pipeline A                 : No
Read Pipeline B                 : No
Optimized for                   : Speed
Portname DataIn                 : WD
Portname DataOut                : RD
Portname Write En               : WEN
Portname Read En                : REN
Portname WClock                 : WCLK
Portname RClock                 : RCLK
Portname WAddress               : WADDR
Portname RAddress               : RADDR
Portname Reset                  :
Portname Clock                  :
Portname DataAIn                :
Portname DataBIn                :
Portname DataAOut               :
Portname DataBOut               :
Portname AddressA               :
Portname AddressB               :
Portname CLKA                   :
Portname CLKB                   :
Portname RWA                    :
Portname RWB                    :
Portname BLKA                   :
Portname BLKB                   :
Portname LP                     :
Portname FF                     :
Initialize RAM                  : False
 
Cascade Configuration:
     Write Port configuration   : 256x18
     Read Port configuration    : 256x18
     Number of blocks depth wise: 1
     Number of blocks width wise: 2
 
**************
Compile Report
**************
 
 
Netlist Resource Report
=======================
 
    CORE                     Used:      2  Total:  24576   (0.01%)
    IO (W/ clocks)           Used:      0  Total:    154   (0.00%)
    Differential IO          Used:      0  Total:     35   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      0  Total:     18   (0.00%)
    PLL                      Used:      0  Total:      1   (0.00%)
    RAM/FIFO                 Used:      2  Total:     32   (6.25%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)
 
Wrote Verilog netlist to
L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36\Two\
PortRAM_256x36.v.
 
 ** Log Ended:   Thu Jun 25 17:18:46 2009
 

Line No.	Rev	Author	Line
1	8	unneback	`** Message System Log`
2			`** Database:`
3			`** Date: Thu Jun 25 17:18:45 2009`
4
5
6			`****************`
7			`Macro Parameters`
8			`****************`
9
10			`Name : TwoPortRAM_256x36`
11			`Family : ProASIC3`
12			`Output Format : VERILOG`
13			`Type : RAM`
14			`Write Enable : Active High`
15			`Read Enable : Active High`
16			`Reset : None`
17			`LP : None`
18			`FF : None`
19			`Read Clock : Rising`
20			`Write Clock : Rising`
21			`Write Depth : 256`
22			`Write Width : 36`
23			`Read Depth : 256`
24			`Read Width : 36`
25			`RAM Type : Two Port`
26			`Clocks : Independent Read and Write Clocks`
27			`Write Mode A : Hold Data`
28			`Write Mode B : Hold Data`
29			`Read Pipeline A : No`
30			`Read Pipeline B : No`
31			`Optimized for : Speed`
32			`Portname DataIn : WD`
33			`Portname DataOut : RD`
34			`Portname Write En : WEN`
35			`Portname Read En : REN`
36			`Portname WClock : WCLK`
37			`Portname RClock : RCLK`
38			`Portname WAddress : WADDR`
39			`Portname RAddress : RADDR`
40			`Portname Reset :`
41			`Portname Clock :`
42			`Portname DataAIn :`
43			`Portname DataBIn :`
44			`Portname DataAOut :`
45			`Portname DataBOut :`
46			`Portname AddressA :`
47			`Portname AddressB :`
48			`Portname CLKA :`
49			`Portname CLKB :`
50			`Portname RWA :`
51			`Portname RWB :`
52			`Portname BLKA :`
53			`Portname BLKB :`
54			`Portname LP :`
55			`Portname FF :`
56			`Initialize RAM : False`
57
58			`Cascade Configuration:`
59			`Write Port configuration : 256x18`
60			`Read Port configuration : 256x18`
61			`Number of blocks depth wise: 1`
62			`Number of blocks width wise: 2`
63
64			`**************`
65			`Compile Report`
66			`**************`
67
68
69			`Netlist Resource Report`
70			`=======================`
71
72			`CORE Used: 2 Total: 24576 (0.01%)`
73			`IO (W/ clocks) Used: 0 Total: 154 (0.00%)`
74			`Differential IO Used: 0 Total: 35 (0.00%)`
75			`GLOBAL (Chip+Quadrant) Used: 0 Total: 18 (0.00%)`
76			`PLL Used: 0 Total: 1 (0.00%)`
77			`RAM/FIFO Used: 2 Total: 32 (6.25%)`
78			`Low Static ICC Used: 0 Total: 1 (0.00%)`
79			`FlashROM Used: 0 Total: 1 (0.00%)`
80			`User JTAG Used: 0 Total: 1 (0.00%)`
81
82			`Wrote Verilog netlist to`
83			`L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36\Two\`
84			`PortRAM_256x36.v.`
85
86			`** Log Ended: Thu Jun 25 17:18:46 2009`
87

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [backend/] [ACTEL/] [TwoPortRAM_256x36/] [TwoPortRAM_256x36.log] - Blame information for rev 8