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[/] [versatile_mem_ctrl/] [trunk/] [bench/] [ddr/] [subtest.vh] - Blame information for rev 74

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/****************************************************************************************
*
*    File Name:  subtest.vh
*
*  Description:  Micron SDRAM DDR2 (Double Data Rate 2)
*                This file is included by tb.v
*
*   Disclaimer   This software code and all associated documentation, comments or other
*  of Warranty:  information (collectively "Software") is provided "AS IS" without
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
*                DAMAGES. Because some jurisdictions prohibit the exclusion or
*                limitation of liability for consequential or incidental damages, the
*                above limitation may not apply to you.
*
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
 
    initial begin : test
        cke     <=  1'b0;
        cs_n    <=  1'b1;
        ras_n   <=  1'b1;
        cas_n   <=  1'b1;
        we_n    <=  1'b1;
        ba      <=  {BA_BITS{1'bz}};
        a       <=  {ADDR_BITS{1'bz}};
        odt     <=  1'b0;
        dq_en   <=  1'b0;
        dqs_en  <=  1'b0;
 
        cke     <=  1'b1;
 
        // POWERUP SECTION 
        power_up;
 
        // INITIALIZE SECTION
        precharge       (0, 1);                         // Precharge all banks
        nop             (trp);
 
        load_mode       (2, 0);                         // Extended Mode Register (2)
        nop             (tmrd-1);
 
        load_mode       (3, 0);                         // Extended Mode Register (3)
        nop             (tmrd-1);
 
        load_mode       (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with DLL Enable
        nop             (tmrd-1);
 
        load_mode       (0, 13'b0_000_1_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
        nop             (tmrd-1);
 
        precharge       (0, 1);                         // Precharge all banks
        nop             (trp);
 
        refresh;
        nop             (trfc-1);
 
        refresh;
        nop             (trfc-1);
 
        load_mode       (0, 13'b0_000_0_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
        nop             (tmrd-1);
 
        load_mode       (1, 13'b0_0_0_111_0_000_1_0_0); // Extended Mode Register with OCD Default
        nop             (tmrd-1);
 
        load_mode       (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with OCD Exit
        nop             (tmrd-1);
 
        // DLL RESET ENABLE - you will need 200 TCK before any read command.
        nop             (200);
 
        // WRITE SECTION
        activate        (0, 0);                       // Activate Bank 0, Row 0
        nop             (trcd-1);
        write           (0, 4, 0, 0, 'h3210);         // Write  Bank 0, Col 0
        nop             (tccd-1);
        write           (0, 0, 1, 0, 'h0123);         // Write  Bank 0, Col 0
 
        activate        (1, 0);                       // Activate Bank 1, Row 0
        nop             (trcd-1);
        write           (1, 0, 1, 0, 'h4567);         // Write  Bank 1, Col 0
 
        activate        (2, 0);                       // Activate Bank 2, Row 0
        nop             (trcd-1);
        write           (2, 0, 1, 0, 'h89AB);         // Write  Bank 2, Col 0
 
        activate        (3, 0);                       // Activate Bank 3, Row 0
        nop             (trcd-1);
        write           (3, 0, 1, 0, 'hCDEF);         // Write  Bank 3, Col 0
 
        nop             (cl - 1 + bl/2 + twtr-1);
 
        nop             (tras);
 
        // READ SECTION
        activate        (0, 0);                       // Activate Bank 0, Row 0
        nop             (trrd-1);
        activate        (1, 0);                       // Activate Bank 1, Row 0
        nop             (trrd-1);
        activate        (2, 0);                       // Activate Bank 2, Row 0
        nop             (trrd-1);
        activate        (3, 0);                       // Activate Bank 3, Row 0
        read            (0, 0, 1);                    // Read   Bank 0, Col 0
        nop             (bl/2);
        read            (1, 1, 1);                    // Read   Bank 1, Col 1
        nop             (bl/2);
        read            (2, 2, 1);                    // Read   Bank 2, Col 2
        nop             (bl/2);
        read            (3, 3, 1);                    // Read   Bank 3, Col 3
        nop             (rl + bl/2);
 
        activate        (0, 0);                       // Activate Bank 0, Row 0
        nop             (trrd-1);
        activate        (1, 0);                       // Activate Bank 1, Row 0
        nop             (trcd-1);
        $display ("%m at time %t: Figure 22: Consecutive READ Bursts", $time);
        read            (0, 0, 0);                    // Read   Bank 0, Col 0
        nop             (bl/2-1);
        read            (0, 4, 0);                    // Read   Bank 0, Col 4
        nop             (rl + bl/2);
 
        $display ("%m at time %t: Figure 23: Nonconsecutive READ Bursts", $time);
        read            (0, 0, 0);                    // Read   Bank 0, Col 0
        nop             (bl/2);
        read            (0, 4, 0);                    // Read   Bank 0, Col 4
        nop             (rl + bl/2);
 
        $display ("%m at time %t: Figure 24: READ Interrupted by READ", $time);
        read            (0, 0, 0);                    // Read   Bank 0, Col 0
        nop             (tccd-1);
        read            (1, 0, 0);                    // Read   Bank 0, Col 0
        nop             (rl + bl/2);
 
        $display ("%m at time %t: Figure 25 & 26: READ to PRECHARGE", $time);
        read            (0, 0, 0);                    // Read   Bank 0, Col 0
        nop             (al + bl/2 + trtp - 2);
        precharge       (0, 0);                       // Precharge Bank 0
        nop             (trp-1);
 
        activate        (0, 0);                       // Activate Bank 0, Row 0
        nop             (trcd-1);
        $display ("%m at time %t: Figure 27: READ to WRITE", $time);
        read            (0, 0, 0);                    // Read   Bank 0, Col 0
        nop             (rl + bl/2 - wl);
        write           (0, 0, 1, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (wl + bl/2 + twr + trp-1);
 
        activate        (0, 0);                       // Activate Bank 0, Row 0
        nop             (trcd-1);
        $display ("%m at time %t: Figure 36: Nonconsecutive WRITE to WRITE", $time);
        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (bl/2);
        write           (0, 4, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (wl + bl/2);
 
        $display ("%m at time %t: Figure 37: Random WRITE Cycles", $time);
        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (bl/2-1);
        write           (0, 4, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (wl + bl/2);
 
        $display ("%m at time %t: Figure 37: Figure 38: WRITE Interrupted by WRITE", $time);
        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (tccd-1);
        write           (1, 4, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (wl + bl/2);
 
        $display ("%m at time %t: Figure 39: WRITE to READ", $time);
        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (wl + bl/2 + twtr-1);
        read_verify     (0, 0, 0, 0, 'h0123);         // Read   Bank 0, Col 0
        nop             (rl + bl/2);
 
        $display ("%m at time %t: Figure 40: WRITE to PRECHARGE", $time);
        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
        nop             (wl + bl/2 + twr-1);
        precharge       (0, 1);                       // Precharge all banks
        nop             (trp-1);
 
        // odt Section
        $display ("%m at time %t: Figure 60: odt Timing for Active or Fast-Exit Power-Down Mode", $time);
        odt             = 1'b1;
        nop             (1);
        odt             = 1'b0;
        nop             (tanpd);
 
        $display ("%m at time %t: Figure 61: odt timing for Slow-Exit or Precharge Power-Down Modes", $time);
        cke             = 1'b0;
        @(negedge ck);
        odt             = 1'b1;
        @(negedge ck);
        odt             = 1'b0;
        repeat(tanpd)@(negedge ck);
        nop             (taxpd);
 
        $display ("%m at time %t: Figure 62 & 63: odt Transition Timings when Entering Power-Down Mode", $time);
        odt             = 1'b1;
        nop             (tanpd);
        power_down      (tcke);
 
        // Self Refresh Section
        nop             (taxpd);
        odt             = 1'b0;
        nop             (3); // taofd
        self_refresh    (tcke);
        nop             (tdllk);
        nop             (tcke);
 
        test_done;
    end

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] [ddr/] [subtest.vh] - Blame information for rev 74

Line No.	Rev	Author	Line
1	11	mikaeljf	`/****************************************************************************************`
2			`*`
3			`* File Name: subtest.vh`
4			`*`
5			`* Description: Micron SDRAM DDR2 (Double Data Rate 2)`
6			`* This file is included by tb.v`
7			`*`
8			`* Disclaimer This software code and all associated documentation, comments or other`
9			`* of Warranty: information (collectively "Software") is provided "AS IS" without`
10			`* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY`
11			`* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED`
12			`* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES`
13			`* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT`
14			`* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE`
15			`* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.`
16			`* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR`
17			`* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,`
18			`* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE`
19			`* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,`
20			`* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,`
21			`* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,`
22			`* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,`
23			`* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE`
24			`* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH`
25			`* DAMAGES. Because some jurisdictions prohibit the exclusion or`
26			`* limitation of liability for consequential or incidental damages, the`
27			`* above limitation may not apply to you.`
28			`*`
29			`* Copyright 2003 Micron Technology, Inc. All rights reserved.`
30			`*`
31			`****************************************************************************************/`
32
33			`initial begin : test`
34			`cke <= 1'b0;`
35			`cs_n <= 1'b1;`
36			`ras_n <= 1'b1;`
37			`cas_n <= 1'b1;`
38			`we_n <= 1'b1;`
39			`ba <= {BA_BITS{1'bz}};`
40			`a <= {ADDR_BITS{1'bz}};`
41			`odt <= 1'b0;`
42			`dq_en <= 1'b0;`
43			`dqs_en <= 1'b0;`
44
45			`cke <= 1'b1;`
46
47			`// POWERUP SECTION`
48			`power_up;`
49
50			`// INITIALIZE SECTION`
51			`precharge (0, 1); // Precharge all banks`
52			`nop (trp);`
53
54			`load_mode (2, 0); // Extended Mode Register (2)`
55			`nop (tmrd-1);`
56
57			`load_mode (3, 0); // Extended Mode Register (3)`
58			`nop (tmrd-1);`
59
60			`load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with DLL Enable`
61			`nop (tmrd-1);`
62
63			`load_mode (0, 13'b0_000_1_0_000_0_011 \| (twr-1)<<9 \| taa<<4); // Mode Register without DLL Reset (bl=8)`
64			`nop (tmrd-1);`
65
66			`precharge (0, 1); // Precharge all banks`
67			`nop (trp);`
68
69			`refresh;`
70			`nop (trfc-1);`
71
72			`refresh;`
73			`nop (trfc-1);`
74
75			`load_mode (0, 13'b0_000_0_0_000_0_011 \| (twr-1)<<9 \| taa<<4); // Mode Register without DLL Reset (bl=8)`
76			`nop (tmrd-1);`
77
78			`load_mode (1, 13'b0_0_0_111_0_000_1_0_0); // Extended Mode Register with OCD Default`
79			`nop (tmrd-1);`
80
81			`load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with OCD Exit`
82			`nop (tmrd-1);`
83
84			`// DLL RESET ENABLE - you will need 200 TCK before any read command.`
85			`nop (200);`
86
87			`// WRITE SECTION`
88			`activate (0, 0); // Activate Bank 0, Row 0`
89			`nop (trcd-1);`
90			`write (0, 4, 0, 0, 'h3210); // Write Bank 0, Col 0`
91			`nop (tccd-1);`
92			`write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0`
93
94			`activate (1, 0); // Activate Bank 1, Row 0`
95			`nop (trcd-1);`
96			`write (1, 0, 1, 0, 'h4567); // Write Bank 1, Col 0`
97
98			`activate (2, 0); // Activate Bank 2, Row 0`
99			`nop (trcd-1);`
100			`write (2, 0, 1, 0, 'h89AB); // Write Bank 2, Col 0`
101
102			`activate (3, 0); // Activate Bank 3, Row 0`
103			`nop (trcd-1);`
104			`write (3, 0, 1, 0, 'hCDEF); // Write Bank 3, Col 0`
105
106			`nop (cl - 1 + bl/2 + twtr-1);`
107
108			`nop (tras);`
109
110			`// READ SECTION`
111			`activate (0, 0); // Activate Bank 0, Row 0`
112			`nop (trrd-1);`
113			`activate (1, 0); // Activate Bank 1, Row 0`
114			`nop (trrd-1);`
115			`activate (2, 0); // Activate Bank 2, Row 0`
116			`nop (trrd-1);`
117			`activate (3, 0); // Activate Bank 3, Row 0`
118			`read (0, 0, 1); // Read Bank 0, Col 0`
119			`nop (bl/2);`
120			`read (1, 1, 1); // Read Bank 1, Col 1`
121			`nop (bl/2);`
122			`read (2, 2, 1); // Read Bank 2, Col 2`
123			`nop (bl/2);`
124			`read (3, 3, 1); // Read Bank 3, Col 3`
125			`nop (rl + bl/2);`
126
127			`activate (0, 0); // Activate Bank 0, Row 0`
128			`nop (trrd-1);`
129			`activate (1, 0); // Activate Bank 1, Row 0`
130			`nop (trcd-1);`
131			`$display ("%m at time %t: Figure 22: Consecutive READ Bursts", $time);`
132			`read (0, 0, 0); // Read Bank 0, Col 0`
133			`nop (bl/2-1);`
134			`read (0, 4, 0); // Read Bank 0, Col 4`
135			`nop (rl + bl/2);`
136
137			`$display ("%m at time %t: Figure 23: Nonconsecutive READ Bursts", $time);`
138			`read (0, 0, 0); // Read Bank 0, Col 0`
139			`nop (bl/2);`
140			`read (0, 4, 0); // Read Bank 0, Col 4`
141			`nop (rl + bl/2);`
142
143			`$display ("%m at time %t: Figure 24: READ Interrupted by READ", $time);`
144			`read (0, 0, 0); // Read Bank 0, Col 0`
145			`nop (tccd-1);`
146			`read (1, 0, 0); // Read Bank 0, Col 0`
147			`nop (rl + bl/2);`
148
149			`$display ("%m at time %t: Figure 25 & 26: READ to PRECHARGE", $time);`
150			`read (0, 0, 0); // Read Bank 0, Col 0`
151			`nop (al + bl/2 + trtp - 2);`
152			`precharge (0, 0); // Precharge Bank 0`
153			`nop (trp-1);`
154
155			`activate (0, 0); // Activate Bank 0, Row 0`
156			`nop (trcd-1);`
157			`$display ("%m at time %t: Figure 27: READ to WRITE", $time);`
158			`read (0, 0, 0); // Read Bank 0, Col 0`
159			`nop (rl + bl/2 - wl);`
160			`write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0`
161			`nop (wl + bl/2 + twr + trp-1);`
162
163			`activate (0, 0); // Activate Bank 0, Row 0`
164			`nop (trcd-1);`
165			`$display ("%m at time %t: Figure 36: Nonconsecutive WRITE to WRITE", $time);`
166			`write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0`
167			`nop (bl/2);`
168			`write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0`
169			`nop (wl + bl/2);`
170
171			`$display ("%m at time %t: Figure 37: Random WRITE Cycles", $time);`
172			`write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0`
173			`nop (bl/2-1);`
174			`write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0`
175			`nop (wl + bl/2);`
176
177			`$display ("%m at time %t: Figure 37: Figure 38: WRITE Interrupted by WRITE", $time);`
178			`write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0`
179			`nop (tccd-1);`
180			`write (1, 4, 0, 0, 'h0123); // Write Bank 0, Col 0`
181			`nop (wl + bl/2);`
182
183			`$display ("%m at time %t: Figure 39: WRITE to READ", $time);`
184			`write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0`
185			`nop (wl + bl/2 + twtr-1);`
186			`read_verify (0, 0, 0, 0, 'h0123); // Read Bank 0, Col 0`
187			`nop (rl + bl/2);`
188
189			`$display ("%m at time %t: Figure 40: WRITE to PRECHARGE", $time);`
190			`write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0`
191			`nop (wl + bl/2 + twr-1);`
192			`precharge (0, 1); // Precharge all banks`
193			`nop (trp-1);`
194
195			`// odt Section`
196			`$display ("%m at time %t: Figure 60: odt Timing for Active or Fast-Exit Power-Down Mode", $time);`
197			`odt = 1'b1;`
198			`nop (1);`
199			`odt = 1'b0;`
200			`nop (tanpd);`
201
202			`$display ("%m at time %t: Figure 61: odt timing for Slow-Exit or Precharge Power-Down Modes", $time);`
203			`cke = 1'b0;`
204			`@(negedge ck);`
205			`odt = 1'b1;`
206			`@(negedge ck);`
207			`odt = 1'b0;`
208			`repeat(tanpd)@(negedge ck);`
209			`nop (taxpd);`
210
211			`$display ("%m at time %t: Figure 62 & 63: odt Transition Timings when Entering Power-Down Mode", $time);`
212			`odt = 1'b1;`
213			`nop (tanpd);`
214			`power_down (tcke);`
215
216			`// Self Refresh Section`
217			`nop (taxpd);`
218			`odt = 1'b0;`
219			`nop (3); // taofd`
220			`self_refresh (tcke);`
221			`nop (tdllk);`
222			`nop (tcke);`
223
224			`test_done;`
225			`end`