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[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb_defines.v] - Blame information for rev 94

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Line No. Rev Author Line
1 94 unneback
// clock periods
2
`define WB0_CLK_PERIOD 20
3
`define SDRAM_CLK_PERIOD 6
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`define SDR_16
6 74 mikaeljf
`define DDR_16

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