URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb_defines.v] - Blame information for rev 99


// clock periods
`define WB0_CLK_PERIOD 20
`define SDRAM_CLK_PERIOD 6
 
`define SDR_16
`define DDR_16

Line No.	Rev	Author	Line
1	94	unneback	`// clock periods`
2			`define WB0_CLK_PERIOD 20
3			`define SDRAM_CLK_PERIOD 6
4
5			`define SDR_16
6	74	mikaeljf	`define DDR_16