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\input texinfo

@c -*-texinfo-*-

@c %**start of header

@setfilename versatile_mem_ctrl

@include version.texi

@settitle Versatile memory controller @value{VERSION}

@c %**end of header

@set DESIGN Versatile memory controller

@copying

This file documents the @value{DESIGN}.

Copyright @copyright{} 2011 ORSoC

@quotation

Permission is granted to copy, distribute and/or modify this document

under the terms of the GNU Free Documentation License, Version 1.2 or

any later version published by the Free Software Foundation; with no

Invariant Sections, with no Front-Cover Texts, and with no Back-Cover

Texts.  A copy of the license is included in the section entitled ``GNU

Free Documentation License''.

@end quotation

@end copying

@afourpaper

@titlepage

@title @value{DESIGN} User Guide

@c @subtitle subtitle-if-any

@c @subtitle second-subtitle

@author Michael Unneback

@author ORSoC

@c  The following two commands

@c  start the copyright page.

@page

@vskip 0pt plus 1filll

@insertcopying

Published by ORSoC

@end titlepage

@c So the toc is printed at the start.

@contents

@ifnottex

@node Top

@top Scope of this Document

This document is the user guide for @value{DESIGN}.

@end ifnottex

@node Document Introduction

@chapter Introduction

@cindex Introduction to this @value{DESIGN}

This design implements a versatile memory controller. If used in combination with the versitale library, available from OpenCores,

different types of system can easily be designed, including use cases where the system bus is in one clock domain and the memory

 controller in an other.

@section Dependencies to other IP cores

This design uses the following IP coreas available from OpenCores project verstile library.

@itemize @bullet

@item vl_cnt_shreg_ce_clear

@item vl_dff_ce_clear

@item vl_cnt_lfsr_zq

@item vl_dff

@item vl_o_dff

@item vl_io_dff_oe

@end itemize

@node Block diagram

@chapter Block Diagram

@cindex Block diagram

@section Synchronous design

@image{block-sdram}

Synchronous design where wishbone clock domain is equal to SDRAM and SDRAM controller clock domain.

@section Asynchronous design

@image{block-sdram-wbwb}

Asynchronous design where wishbone and SDRAM clock domain are independant. A wishbone rev B3 compatilble bridge

is available in project versatile_library from OpenCores, http://www.opencores.org.

@section Asynchronous design with multiple wishbone interfaces

@image{block-sdram-wbwb-arbiter}

Asynchronous design where wishbone and SDRAM clock domain are independant. Multiple wishbone port with use of a wishbone arbiter.

@node SDR SDRAM controller

@chapter SDR SDRAM controller

@section Module defines

@multitable @columnfractions .2 .8

@headitem Name @tab Description

@item NO_BURST @tab Define if burst cycles not used

@item WRAP4 @tab Define to support 4 word wrap burst

@item WRAP8 @tab Define to support 8 word wrap burst

@item WRAP16 @tab Define to support 16 word wrap burst

@end multitable

@section Module parameters

@multitable @columnfractions .2 .1 .7

@headitem Name @tab Default value @tab Description

@item ba_size @tab 2 @tab Bank adress vector size

@item row_size @tab 13 @tab Row adress vector size

@item col_size @tab 9 @tab Column adress vector size

@item cl @tab 2 @tab CAS latency

@end multitable

Parameters ba_size, col_size and row_size should be set depending on memory configuration. The following

table holds figures for some SDRAM memories.

@multitable @columnfractions .15 .25 .1 .1 .1 .3

@headitem Manufacturer @tab Partnumber @tab ba_size  @tab row_size @tab col_size @tab Memory size

@item Micron @tab MT48LC4M16 @tab 2 @tab 12 @tab 8 @tab 8Mbyte

@item Micron @tab MT48LC8M16 @tab 2 @tab 12 @tab 9 @tab 16Mbyte

@item Micron @tab MT48LC16M16 @tab 2 @tab 13 @tab 9 @tab 32Mbyte

@item Micron @tab MT48LC32M16 @tab 2 @tab 13 @tab 10 @tab 64Mbyte

@end multitable

Parameter cl should be set to either 2 or 3 depending on SDRAM clock.

@section Module IO signals

@subsection Wishbone signals

@multitable @columnfractions .2 .1 .1 .6

@headitem Name @tab Dir @tab Width @tab Description

@item dat_i @tab I  @tab 32 @tab Input data vector

@item adr_i @tab I  @tab  @tab Adress vector

@item sel_i @tab I  @tab 4 @tab Byte select signals

@item bte_i @tab I  @tab 2 @tab Bus tag identifier

@item we_i @tab I  @tab 1 @tab Write enable

@item cyc_i @tab I  @tab 1 @tab Active cycle indicator

@item stb_i @tab I  @tab 1 @tab Strobe

@item dat_o @tab O  @tab 32 @tab Output data vector

@item ack_o @tab O  @tab 1 @tab Acknowledge signal

@end multitable

Wishbone signal bte_i is optional and is only used for designs supporting burst transfer.

@subsection SDRAM signals

@multitable @columnfractions .2 .1 .1 .6

@headitem Name @tab Dir @tab Width @tab Description

@item ba @tab O @tab ba_size @tab Bank adress vector

@item a @tab O @tab 13 @tab Adress vector

@item cmd @tab O @tab 3 @tab SDRAM command, {ras_n, cas_n, we_n}

@item cke @tab O @tab 1 @tab Clock enable

@item cs_n @tab O @tab 1 @tab Chip select, active low

@item dqm @tab O @tab 2 @tab Data mask

@item dq_i @tab I @tab 16 @tab Data input vector

@item dq_o @tab O @tab 16 @tab Data output vector

@item dq_oe @tab O @tab 1 @tab Data output enable

@end multitable

@subsection System signals

@multitable @columnfractions .2 .1 .1 .6

@headitem Name @tab Dir @tab Width @tab Description

@item clk @tab I @tab 1 @tab SDRAM system clock

@item rst @tab I @tab 1 @tab Asynchronous reset, active hig

@end multitable

@node SDR SDRAM 16 bit data bus controller

@chapter SDR SDRAM 16 bit data bus controller

@cindex SDR SDRAM 16 bit data bus controller

@section State machine implementation

Design is based on a state machine as described below.

@image{sdr_sdram_16,14cm,16cm,,.png}

A counter is incremented on each cycle the state machine reside in any given state.

When changing state a counter clear is issued. The counter state vector is used for

two things

@itemize

@item controlling outputs, ie defining cmd and other control signals

@item to make sure timing reqiurements are fulfilled, ie define time from precharge to activate

@end itemize

@subsection State - init

The init state is responsible to make sure that a proper start-up and initialization of the SDRAM is

performed. The following sequence should be applied:

@enumerate

@item assert CKE low

@item provide stable clock

@item bring CKE high

@item perform PRECHARGE ALL command and wait for tRP

@item issue AUTO RERFESH and wait for tRFC

@item issue AUTO RERFESH and wait for tRFC

@item LOAD MODE REGISTER and wait for tMR

@end enumerate

After this state machine advances to idle state

@subsection State - idle

In state idle implementation awaits two different condition, appearing in order of priority

@enumerate

@item refresh request => next state is rfr

@item cyc_i & stb_i => next state is adr

@end enumerate

@subsection State - adr

Depending on status of open bank and open rows choice is taken whether to precharge and activate, activate or go

directly to read write state. Reason for this as a separate state is to be able to have comparison result as a

registered signal to achive an higher clock frequency.

@subsection State - pch

Open row in current bank is deactivated. State machine waits in pch state to fulfill tRP.

@subsection State - act

Row in current bank is activated. State machine waits in act state to fulfill tRCD.

@subsection State - rw

A two word read or write burst is started. If wishbone cycle is of type burst column will get incremented

with possible wrap around and a new burst started for each 32 bit word.

@section Timing

The follwoing timing requirements must be fulfilled:

@itemize

@item tMR - Load Mode Register period

@item tRCD - Active to read/write delay

@item tRP - Precharge command period

@item tRFC - Auto refresh period

@item tREF - refresh period

@end itemize

In the SDRAM datasheet the above timing figures will be given in ns and should be

converted to number of clock cycles. All of the above timing figures, except tREF, are implemented as parameters

in the design and should be set depending on SDRAM figures and actual clock period. All

parameters have default values of 2 clock cycles.

@subsection Bank/Row activation - tRCD

@image{tRCD,15cm,5cm,,.png}

Minimum time between activation of and read or write command.

@subsection Auto refresh mode

@image{aref,15cm,15cm,,.png}

Minumum time between precharge and auto refresh and active command.

@subsection Refresh period - tREF

The auto refresh period, tREF must be met. During auto refresh an internal address counter

is used and adress signals are treated as don't care. During the refresh period each row must

be refreshed. @*

For example consider a SDRAM with tREF = 64 ms and row size of 8K. An auto refresh command

should be issued once every 64 ms / 8192 = 7.813 us.@*

The refresh interval counter is implemented as an LFSR style counter for minimal area and maximum

performance. To accurately set the wrap value for this counter use the application VersatileCounter found

in the versatile library project at opencores. This program gives the wrap value for a given vector length.

Assuming an SDRAM clock frequency of 133 MHz which equals a period time of 7.5 ns we should issue an auto

refresh every 7.813 us / 7.5 ns = 1041 cycle. We need a state vector of 11 bits in the counter.@*

To get the wrap value we use the application@*

@command{./VersatileCounter.php 11 1041@*11111110101}

@node Example: Timing setup

@chapter Example: Timing setup

@section Requirements

SDRAM device to use:

@itemize

@item Micron MT48LC32M16-7E

@end itemize

@multitable @columnfractions .4 .2 .1 .1 .1 .1

@headitem Parameter @tab Symbol @tab Min @tab Max @tab Unit

@item Auto refresh period @tab tRFC @tab 66 @tab - @tab ns

@item Precharge command period @tab tRP @tab 15 @tab - @tab ns

@item Active to read or write delay @tab tRCD @tab 15 @tab - @tab ns

@item Load mode register command to active or refresh @tab tMRD @tab 2 @tab - @tab tCK

@item Refresh periods (8192 rows) @tab tREF @tab 66 @tab -@tab ms

@end multitable

Intended operating frequency is 75 MHz, tCK = 13.333 ns

@section Parameter settings

@multitable @columnfractions .2 .8

@headitem Symbol @tab Value

@item tRFC @tab 5

@item tRP  @tab 2

@item tRCD @tab 2

@item tMRD @tab 2

@end multitable

@*

Refresh rate is 66 ms / 8192 = 8.057 us@*

Number of clock cycles between refresh request 8.057 us / 13.333 ns = 604@*

@*

To get the wrap value we use the application from Versatile Library@*

@command{./VersatileCounter.php 10 604@*0101001110}

@c ****************************************************************************

@c End bits

@c ****************************************************************************

@node GNU Free Documentation License

@chapter GNU Free Documentation License

@cindex license for @value{DESIGN}

@include fdl.texi

@node Index

@unnumbered Index

@printindex cp

@bye