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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Blame information for rev 2

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Line No. Rev Author Line
1 2 unneback
svn_export:
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        svn export http://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
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        svn export http://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v
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        svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/lfsr_polynom.v
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        svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter.v
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dual_port_ram:
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        vppreproc +define+TYPE+"dc_dw" +define+DC +define+DW +define+DATA_WIDTH+36 +define+ADDR_WIDTH+8 --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v
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fifo_adr_counter:
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        cp fifo_adr_counter_defines.v versatile_counter_defines.v
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        vpp versatile_counter.v > tmp1.v
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        vppreproc --simple tmp1.v | cat copyright.v - > fifo_adr_counter.v
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ctrl_counter:
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        cp ctrl_counter_defines.v versatile_counter_defines.v
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        vpp versatile_counter.v > tmp1.v
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        vppreproc --simple tmp1.v | cat copyright.v - > ctrl_counter.v
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versatile_mem_ctrl:
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        vppreproc --simple versatile_mem_ctrl_top.v ctrl_counter.v fifo.v | cat copyright.v - > versatile_mem_ctrl_ip.v
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all:  ctrl_counter dual_port_ram fifo_adr_counter fifo versatile_mem_ctrl

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