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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Blame information for rev 98

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Line No. Rev Author Line
1 97 unneback
sdr_sdram_16_ctrl_actel.v:
2 95 unneback
        vppreproc --noline --noblank +define+RFR_LENGTH+10 +define+RFR_WRAP_VALUE+1001 +define+ACTEL sdr_sdram_16_ctrl.v > sdr_sdram_16_ctrl_actel.v
3 49 julius
 
4 97 unneback
export:
5
        svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v
6
 
7 50 julius
# the single all rule
8 95 unneback
all: sdr_sdram_16_ctrl_actel.v
9 50 julius
 
10 18 mikaeljf
clean:
11 50 julius
        rm -rf $(VERSATILE_FIFO_PROJECT_FILES) $(VERSATILE_COUNTER_PROJECT_FILES)
12 18 mikaeljf
        rm -rf fifo_fill.v sdr_16.v ddr_16.v
13 50 julius
        rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
14 18 mikaeljf
        rm -rf *_counter.v
15 24 mikaeljf
        rm -rf *.csv
16 18 mikaeljf
        rm -rf *~
17 95 unneback
        rm -rf sdr_sdram_16_ctrl_actel.v

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