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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [versatile_mem_ctrl_defines.v] - Blame information for rev 111

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Line No. Rev Author Line
1 111 unneback 
//=tab Main
2 
 
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// Number of WB groups
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//=select
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//`define WB_GRPS_1 // 1
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//`define WB_GRPS_2 // 2
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`define WB_GRPS_3 // 3
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//`define WB_GRPS_4 // 4
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//`define WB_GRPS_5 // 5
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//`define WB_GRPS_6 // 6
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//`define WB_GRPS_7 // 7
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//`define WB_GRPS_8 // 8
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//=end
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`ifdef WB_GRPS_2
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    `define WB_GRPS_1
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    `define NR_OF_WB_GRPS 2
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    `define NR_OF_PORTS 2
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`endif
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`ifdef WB_GRPS_3
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    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define NR_OF_WB_GRPS 3
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    `define NR_OF_PORTS 3
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`endif
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`ifdef WB_GRPS_4
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    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define WB_GRPS_3
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    `define NR_OF_WB_GRPS 4
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    `define NR_OF_PORTS 4
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`endif
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`ifdef WB_GRPS_5
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    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define WB_GRPS_3
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    `define WB_GRPS_4
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    `define NR_OF_WB_GRPS 5
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    `define NR_OF_PORTS 5
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`endif
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`ifdef WB_GRPS_6
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    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define WB_GRPS_3
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    `define WB_GRPS_4
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    `define WB_GRPS_5
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    `define NR_OF_WB_GRPS 6
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    `define NR_OF_PORTS 6
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`endif
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`ifdef WB_GRPS_7
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    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define WB_GRPS_3
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    `define WB_GRPS_4
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    `define WB_GRPS_5
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    `define WB_GRPS_6
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    `define NR_OF_WB_GRPS 7
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    `define NR_OF_PORTS 7
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`endif
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`ifdef WB_GRPS_8
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    `define WB_GRPS_1
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    `define WB_GRPS_2
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    `define WB_GRPS_3
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    `define WB_GRPS_4
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    `define WB_GRPS_5
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    `define WB_GRPS_6
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    `define WB_GRPS_7
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    `define NR_OF_WB_GRPS 8
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    `define NR_OF_PORTS 8
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`endif
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// Clock domain crossing WB1
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//=select
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//`define WB1_MEM_CLK // mem clk domain
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`define WB1_CLK // wb1 clk domain
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//=end
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// Clock domain crossing WB1
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//=select
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//`define WB2_MEM_CLK // mem clk domain
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`define WB2_CLK // wb2 clk domain
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//=end
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// Clock domain crossing WB1
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//=select
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`define WB3_MEM_CLK // mem clk domain
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//`define WB3_CLK // wb3 clk domain
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//=end
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// Clock domain crossing WB1
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//=select
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//`define WB4_MEM_CLK // mem clk domain
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`define WB4_CLK // wb4 clk domain
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//=end
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// Clock domain crossing WB1
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//=select
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//`define WB5_MEM_CLK // mem clk domain
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`define WB5_CLK // wb5 clk domain
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//=end
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// Clock domain crossing WB1
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//=select
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//`define WB6_MEM_CLK // mem clk domain
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`define WB6_CLK // wb6 clk domain
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//=end
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// Clock domain crossing WB1
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//=select
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//`define WB7_MEM_CLK // mem clk domain
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`define WB7_CLK // wb7 clk domain
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//=end
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// Clock domain crossing WB1
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//=select
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//`define WB8_MEM_CLK // mem clk domain
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`define WB8_CLK // wb8 clk domain
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//=end
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// Module base name
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`define BASE versatile_mem_ctrl_
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// Memory type
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//=select
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//`define RAM // RAM
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`define SDR // SDR
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//`define DDR2 // DDR2
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//`define DDR3 // DDR3
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//=end
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// Shadow RAM
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`define SHADOW_RAM
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//=tab RAM
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// Number of bits in address
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`define RAM_ADR_SIZE 16
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// Capacity in KBytes
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`define RAM_MEM_SIZE_KB 48
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`ifdef RAM_MEM_SIZE_KB
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`define RAM_MEM_SIZE `RAM_MEM_SIZE_KB*1024
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`endif
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// Memory init
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`define RAM_MEM_INIT_DUMMY
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`ifndef RAM_MEM_INIT_DUMMY
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    `define RAM_MEM_INIT 0
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`else
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    `define RAM_MEM_INIT 1
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`endif
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// Memory init file
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`define RAM_MEM_INIT_FILE "ram_init.v"
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`ifdef RAM
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`define WB_ADR_SIZE `RAM_ADR_SIZE
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`endif
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//=tab SDR SDRAM
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// External data bus size
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`define SDR_EXT_DAT_SIZE 16
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// Memory part
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//=select Memory part
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//`define MT48LC4M16 // Micron 4M16, 8MB
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`define MT48LC16M16 // Micron 16M16, 32MB
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//`define MT48LC32M16 // Micron 32M16, 64MB
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//=end
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// SDRAM clock frequency
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// set refresh counter timeout
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// all rows should be refreshed every 64 ms
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// SDRAM CLK frequency
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//=select SDRAM CLK
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`define SDR_SDRAM_CLK_64 // SDRAM_CLK_64
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//`define SDR_SDRAM_CLK_75 // SDRAM_CLK_75
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//`define SDR_SDRAM_CLK_125 // SDRAM_CLK_125
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//`define SDR_SDRAM_CLK_133 // SDRAM_CLK_133
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//`define SDR_SDRAM_CLK_154 // SDRAM_CLK_154
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//=end
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`ifdef MT48LC4M16
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// using 1 of MT48LC4M16
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// SDRAM data width is 16
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`define SDR_SDRAM_DATA_WIDTH 16
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`define SDR_SDRAM_DATA_WIDTH_16
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`define SDR_COL_SIZE 8
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`define SDR_ROW_SIZE 12
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`define SDR_ROW_SIZE_12
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`define SDR_BA_SIZE 2
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`endif //  `ifdef MT48LC4M16
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`ifdef MT48LC16M16
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// using 1 of MT48LC16M16
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// SDRAM data width is 16
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`define SDR_SDRAM_DATA_WIDTH 16
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`define SDR_SDRAM_DATA_WIDTH_16
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`define SDR_COL_SIZE 9
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`define SDR_ROW_SIZE 13
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`define SDR_ROW_SIZE_13
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`define SDR_BA_SIZE 2
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`endif //  `ifdef MT48LC16M16
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`ifdef MT48LC32M16
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// using 1 of MT48LC32M16
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// SDRAM data width is 16
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`define SDR_SDRAM_DATA_WIDTH 16
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`define SDR_SDRAM_DATA_WIDTH_16
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`define SDR_COL_SIZE 10
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`define SDR_ROW_SIZE 13
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`define SDR_ROW_SIZE_13
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`define SDR_BA_SIZE 2
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`endif //  `ifdef MT48LC16M16
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// Refresh whole memory every 64 ms
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// Refresh each row every 64 ms
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// refresh timeout = 64 ms / Tperiod / number_of_rows
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// 64 MHz, row_size=12
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// 64ms / (1/64MHz) / 2^12 = 1000
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// ./VersatileCounter.php 10 1000
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// 0101100100
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`ifdef SDR_SDRAM_CLK_64
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    `ifdef SDR_ROW_SIZE_12
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        `define SDR_RFR_LENGTH 10
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        `define SDR_RFR_WRAP_VALUE 0101100100
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    `endif
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    `ifdef SDR_ROW_SIZE_13
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        `define SDR_RFR_LENGTH 9
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        `define SDR_RFR_WRAP_VALUE 001000011
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    `endif
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`endif
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`ifdef SDR_SDRAM_CLK_75
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    `ifdef SDR_ROW_SIZE_12
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        `define SDR_RFR_LENGTH 11
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        `define SDR_RFR_WRAP_VALUE 00110001101
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    `endif
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    `ifdef SDR_ROW_SIZE_13
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        `define SDR_RFR_LENGTH 10
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        `define SDR_RFR_WRAP_VALUE 0110111101
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    `endif
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`endif
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`ifdef SDR_SDRAM_CLK_125
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    `ifdef SDR_ROW_SIZE_12
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        `define SDR_RFR_LENGTH 11
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        `define SDR_RFR_WRAP_VALUE 10001000001
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    `endif
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    `ifdef SDR_ROW_SIZE_13
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        `define SDR_RFR_LENGTH 10
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        `define SDR_RFR_WRAP_VALUE 1010000111
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    `endif
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`endif
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`ifdef SDR_SDRAM_CLK_133
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    `ifdef SDR_ROW_SIZE_12
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        `define SDR_RFR_LENGTH 12
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        `define SDR_RFR_WRAP_VALUE 101100000111
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    `endif
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    `ifdef SDR_ROW_SIZE_13
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        `define SDR_RFR_LENGTH 11
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        `define SDR_RFR_WRAP_VALUE 11111111010
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    `endif
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`endif
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`ifdef SDR_SDRAM_CLK_154
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    `ifdef SDR_ROW_SIZE_12
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        `define SDR_RFR_LENGTH 12
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        `define SDR_RFR_WRAP_VALUE 000101011110
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    `endif
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    `ifdef SDR_ROW_SIZE_13
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        `define SDR_RFR_LENGTH 11
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        `define SDR_RFR_WRAP_VALUE 00111101010
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    `endif
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`endif
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// Disable burst
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//`define SDR_NO_BURST
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// Enable 4 beat wishbone busrt
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`define SDR_BEAT4
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// Enable 8 beat wishbone busrt
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`define SDR_BEAT8
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// Enable 16 beat wishbone busrt
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`define SDR_BEAT16
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// tRFC
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`define SDR_TRFC 9
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// tRP
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`define SDR_TRP 2
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// tRCD
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`define SDR_TRCD 2
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// tMRD
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`define SDR_TMRD 2
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// LMR
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// [12:10] reserved
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// [9]     WB, write burst; 0 - programmed burst length, 1 - single location
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// [8:7]   OP Mode, 2'b00
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// [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
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// [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
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// [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
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// LMR: Write burst
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`define SDR_INIT_WB 1'b0
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// LMR: CAS latency
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`define SDR_INIT_CL 3'b010
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// LMR: Burst type
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`define SDR_INIT_BT 1'b0
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// LMR: Burst length
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`define SDR_INIT_BL 3'b001
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`ifdef SDR
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    `ifdef SDR_SDRAM_DATA_WIDTH_16
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        `define WB_ADR_SIZE `SDR_BA_SIZE+`SDR_COL_SIZE+`SDR_ROW_SIZE+1
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    `endif
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`endif
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//=tab DDR2 SDRAM
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// Use existing Avalon compatible IP
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`define DDR2_AVALON
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// IP module name
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`define DDR2_IP_NAME ALTERA_DDR2

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