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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [sim/] [rtl_sim/] [bin/] [wave_ddr.do] - Blame information for rev 28

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Line No. Rev Author Line
1 19 mikaeljf
onerror {resume}
2
quietly WaveActivateNextPane {} 0
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add wave -noupdate -expand -group {CLOCK & RESET} -divider Reset
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/wb_rst
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add wave -noupdate -expand -group {CLOCK & RESET} -divider Clocks
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/wb_clk
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
8
add wave -noupdate -expand -group {CLOCK & RESET} -divider {DCM/PLL generated clocks}
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_0
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_90
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_180
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add wave -noupdate -expand -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270
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add wave -noupdate -group DCM/PLL -divider {Xilinx DCM or Altera altpll}
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/rst
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk_in
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_in
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk0_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk90_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk180_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
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add wave -noupdate -group {WISHBONE IF} -divider wb0
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs0_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs0_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs0_sel_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs0_cti_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs0_bte_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_we_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_cyc_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_stb_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs0_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs0_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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add wave -noupdate -group {WISHBONE IF} -divider wb1
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs1_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs1_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs1_sel_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs1_cti_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs1_bte_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_we_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_cyc_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_stb_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs1_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs1_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
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add wave -noupdate -group {WISHBONE IF} -divider wb4
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs4_dat_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs4_adr_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs4_sel_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs4_cti_i
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wbs4_bte_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_we_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_cyc_i
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_stb_i
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wbs4_dat_o
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wbs4_ack_o
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
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add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/rst
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/a_clk
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/tx_fifo/a_dat_i
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add wave -noupdate -group {TX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/tx_fifo/a_fifo_full_o
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add wave -noupdate -group {TX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/tx_fifo/a_fifo_sel_i
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/a_we_i
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/b_clk
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/tx_fifo/b_dat_o
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add wave -noupdate -group {TX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/tx_fifo/b_fifo_empty_o
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/b_fifo_sel_i
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add wave -noupdate -group {TX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo/b_re_i
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/dpram_a_a
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/dpram_a_b
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/radr0
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/radr1
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add wave -noupdate -group {TX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/tx_fifo/radr4
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add wave -noupdate -group {TX FIFO} -divider {Tx FIFO 0}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[15]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[14]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[13]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[12]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[11]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[10]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[9]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[8]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[7]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[6]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[5]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[4]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[3]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[2]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[1]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[0]}
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add wave -noupdate -group {TX FIFO} -divider {Tx FIFO 1}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[47]}
94
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[46]}
95
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[45]}
96
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[44]}
97
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[43]}
98
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[42]}
99
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[41]}
100
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[40]}
101
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[39]}
102
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[38]}
103
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[37]}
104
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[36]}
105
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[35]}
106
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[34]}
107
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[33]}
108
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[32]}
109
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO 4}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[143]}
111
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[142]}
112
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[141]}
113
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[140]}
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add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[139]}
115
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[138]}
116
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[137]}
117
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[136]}
118
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[135]}
119
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[134]}
120
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[133]}
121
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[132]}
122
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[131]}
123
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[130]}
124
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[129]}
125
add wave -noupdate -group {TX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/tx_fifo/dpram/ram[128]}
126
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
127
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
128
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
129
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
130
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd
131
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/cs_n
132
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix binary /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_empty
133
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re
134
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_sel
135
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read
136
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write
137
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack
138
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req
139
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/sdram_clk
140
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]}
141
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o
142
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
143
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o
144
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_n_pad_o
145
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/cke_pad_o
146
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/cs_n_pad_o
147
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/ras_pad_o
148
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o
149
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o
150
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/ba_pad_o
151
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal -radix decimal /versatile_mem_ctrl_tb/dut/addr_pad_o
152
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_o
153
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dq_oe
154
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dq_en
155
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dqs_en
156
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/rdqs_n_pad_i
157
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
158
add wave -noupdate -group {DDR2 SDRAM IF} -format Logic /versatile_mem_ctrl_tb/dut/dqm_en
159
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/dqm_o
160
add wave -noupdate -group {DDR2 SDRAM IF} -format Literal /versatile_mem_ctrl_tb/dut/dm_rdqs_pad_io
161
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM}
162
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
163
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck
164
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck_n
165
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cke
166
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cs_n
167
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ras_n
168
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cas_n
169
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/we_n
170
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/ba
171
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/addr
172
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/odt
173
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dm_rdqs
174
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/dq
175
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs
176
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n
177
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n
178
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO Control}
179
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/rx_fifo_full
180
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/rx_fifo_empty
181
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 0}
182
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[7]}
183
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[6]}
184
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[5]}
185
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[4]}
186
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[3]}
187
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[2]}
188
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[1]}
189
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[0]}
190
add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/wadr0
191
add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/radr0
192
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 1}
193
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[39]}
194
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[38]}
195
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[37]}
196
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[36]}
197
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[35]}
198
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[34]}
199
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[33]}
200
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[32]}
201
add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/wadr1
202
add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/radr1
203
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 4}
204
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[143]}
205
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[142]}
206
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[141]}
207
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[140]}
208
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[139]}
209
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[138]}
210
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[137]}
211
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[136]}
212
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[135]}
213
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[134]}
214
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[133]}
215
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[132]}
216
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[131]}
217
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[130]}
218
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[129]}
219
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/rx_fifo/dpram/ram[128]}
220
add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/wadr4
221
add wave -noupdate -group {RX FIFO} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/rx_fifo/radr4
222
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
223
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
224
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
225
add wave -noupdate -group {BURST LENGTH} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
226
add wave -noupdate -group {BURST LENGTH} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
227
add wave -noupdate -group {BURST LENGTH} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
228
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
229
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/write
230
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/read
231
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
232
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
233
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
234
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/bte_i
235
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cti_i
236
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init
237
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
238
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
239
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
240
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
241
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
242
TreeUpdate [SetDefaultTree]
243
WaveRestoreCursors {{Cursor 1} {252260000 ps} 0}
244
configure wave -namecolwidth 371
245
configure wave -valuecolwidth 84
246
configure wave -justifyvalue left
247
configure wave -signalnamewidth 0
248
configure wave -snapdistance 10
249
configure wave -datasetprefix 0
250
configure wave -rowmargin 4
251
configure wave -childrowmargin 2
252
configure wave -gridoffset 0
253
configure wave -gridperiod 1
254
configure wave -griddelta 40
255
configure wave -timeline 0
256
configure wave -timelineunits ns
257
update
258
WaveRestoreZoom {193310526 ps} {259935789 ps}

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