| 1 |
19 |
mikaeljf |
onerror {resume}
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| 2 |
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quietly WaveActivateNextPane {} 0
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| 3 |
69 |
mikaeljf |
add wave -noupdate -group {CLOCK & RESET} -divider Reset
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| 4 |
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add wave -noupdate -group {CLOCK & RESET} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
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| 5 |
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add wave -noupdate -group {CLOCK & RESET} -divider Clocks
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| 6 |
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add wave -noupdate -group {CLOCK & RESET} -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_clk
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| 7 |
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
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| 8 |
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add wave -noupdate -group {CLOCK & RESET} -divider {DCM/PLL generated clocks}
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| 9 |
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_0
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| 10 |
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_90
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| 11 |
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_180
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| 12 |
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add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270
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| 13 |
19 |
mikaeljf |
add wave -noupdate -group DCM/PLL -divider {Xilinx DCM or Altera altpll}
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| 14 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/rst
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| 15 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk_in
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| 16 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_in
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| 17 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk0_out
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| 18 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk90_out
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| 19 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk180_out
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| 20 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clk270_out
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| 21 |
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add wave -noupdate -group DCM/PLL -format Logic /versatile_mem_ctrl_tb/dut/dcm_pll_0/clkfb_out
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| 22 |
69 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -divider {Clock & reset}
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| 23 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
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| 24 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_clk
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| 25 |
19 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -divider wb0
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| 26 |
69 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_0
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| 27 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0
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| 28 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0
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| 29 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0
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| 30 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_0
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| 31 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0
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| 32 |
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add wave -noupdate -group {WISHBONE IF} -divider wb1
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| 33 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1
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| 34 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1
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| 35 |
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_stb_i_1
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| 36 |
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_cyc_i_1
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| 37 |
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add wave -noupdate -group {WISHBONE IF} -format Logic /versatile_mem_ctrl_tb/dut/wb_ack_o_1
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| 38 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_1
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| 39 |
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add wave -noupdate -group {WISHBONE IF} -divider wb2
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| 40 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_2
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| 41 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_2
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| 42 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_2
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| 43 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_2
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| 44 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_2
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| 45 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_2
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| 46 |
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add wave -noupdate -group {WISHBONE IF} -divider wb3
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| 47 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_3
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| 48 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_3
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| 49 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_3
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| 50 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_3
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| 51 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3
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| 52 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3
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| 53 |
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add wave -noupdate -group {WISHBONE IF} -divider Testbench
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| 54 |
19 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
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| 55 |
69 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
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| 56 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb0_adr_i
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| 57 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
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| 58 |
19 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
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| 59 |
69 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
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| 60 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb1_adr_i
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| 61 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
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| 62 |
19 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
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| 63 |
69 |
mikaeljf |
add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
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| 64 |
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add wave -noupdate -group {WISHBONE IF} -format Literal /versatile_mem_ctrl_tb/wb4_adr_i
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| 65 |
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add wave -noupdate -group {WISHBONE IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
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| 66 |
19 |
mikaeljf |
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
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| 67 |
69 |
mikaeljf |
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
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| 68 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
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| 69 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
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| 70 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
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| 71 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[27]}
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| 72 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[26]}
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| 73 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[25]}
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| 74 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[24]}
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| 75 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[23]}
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| 76 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[22]}
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| 77 |
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[21]}
|
| 78 |
|
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[20]}
|
| 79 |
|
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[19]}
|
| 80 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[18]}
|
| 81 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[17]}
|
| 82 |
|
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add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[16]}
|
| 83 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[15]}
|
| 84 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[14]}
|
| 85 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[13]}
|
| 86 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[12]}
|
| 87 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[11]}
|
| 88 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[10]}
|
| 89 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[9]}
|
| 90 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[8]}
|
| 91 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[7]}
|
| 92 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[6]}
|
| 93 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[5]}
|
| 94 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[4]}
|
| 95 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[3]}
|
| 96 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[2]}
|
| 97 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[1]}
|
| 98 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[0]}
|
| 99 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -divider FIFO_1_1
|
| 100 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[31]}
|
| 101 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[30]}
|
| 102 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[29]}
|
| 103 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[28]}
|
| 104 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[27]}
|
| 105 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[26]}
|
| 106 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[25]}
|
| 107 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[24]}
|
| 108 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[23]}
|
| 109 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[22]}
|
| 110 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[21]}
|
| 111 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[20]}
|
| 112 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[19]}
|
| 113 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[18]}
|
| 114 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[17]}
|
| 115 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[16]}
|
| 116 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -divider FIFO_1_0
|
| 117 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[15]}
|
| 118 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[14]}
|
| 119 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[13]}
|
| 120 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[12]}
|
| 121 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[11]}
|
| 122 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[10]}
|
| 123 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[9]}
|
| 124 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[8]}
|
| 125 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[7]}
|
| 126 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[6]}
|
| 127 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[5]}
|
| 128 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[4]}
|
| 129 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[3]}
|
| 130 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]}
|
| 131 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]}
|
| 132 |
|
|
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]}
|
| 133 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
|
| 134 |
19 |
mikaeljf |
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
| 135 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
|
| 136 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
|
| 137 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
|
| 138 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd
|
| 139 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/cs_n
|
| 140 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix binary /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_empty
|
| 141 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re
|
| 142 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_sel
|
| 143 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read
|
| 144 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write
|
| 145 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack
|
| 146 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req
|
| 147 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]}
|
| 148 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o
|
| 149 |
69 |
mikaeljf |
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle
|
| 150 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/cur_row
|
| 151 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -divider
|
| 152 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
|
| 153 |
|
|
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
|
| 154 |
19 |
mikaeljf |
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM}
|
| 155 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
| 156 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck
|
| 157 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck_n
|
| 158 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cke
|
| 159 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cs_n
|
| 160 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ras_n
|
| 161 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/cas_n
|
| 162 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/we_n
|
| 163 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/ba
|
| 164 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/addr
|
| 165 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/odt
|
| 166 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dm_rdqs
|
| 167 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/ddr2_sdram/dq
|
| 168 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs
|
| 169 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n
|
| 170 |
|
|
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n
|
| 171 |
|
|
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 0}
|
| 172 |
69 |
mikaeljf |
add wave -noupdate -group {RX FIFO} -divider Control
|
| 173 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/d
|
| 174 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write
|
| 175 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write_enable
|
| 176 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk1
|
| 177 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst1
|
| 178 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read
|
| 179 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read_enable
|
| 180 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk2
|
| 181 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst2
|
| 182 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_full
|
| 183 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/q
|
| 184 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_empty
|
| 185 |
|
|
add wave -noupdate -group {RX FIFO} -divider FIFO_0_1
|
| 186 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[31]}
|
| 187 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[30]}
|
| 188 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[29]}
|
| 189 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[28]}
|
| 190 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[27]}
|
| 191 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[26]}
|
| 192 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[25]}
|
| 193 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[24]}
|
| 194 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[23]}
|
| 195 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[22]}
|
| 196 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[21]}
|
| 197 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[20]}
|
| 198 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[19]}
|
| 199 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[18]}
|
| 200 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[17]}
|
| 201 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[16]}
|
| 202 |
|
|
add wave -noupdate -group {RX FIFO} -divider FIFO_0_0
|
| 203 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[15]}
|
| 204 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[14]}
|
| 205 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[13]}
|
| 206 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[12]}
|
| 207 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[11]}
|
| 208 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[10]}
|
| 209 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[9]}
|
| 210 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[8]}
|
| 211 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[7]}
|
| 212 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[6]}
|
| 213 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[5]}
|
| 214 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[4]}
|
| 215 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[3]}
|
| 216 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[2]}
|
| 217 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[1]}
|
| 218 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[0]}
|
| 219 |
19 |
mikaeljf |
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 1}
|
| 220 |
69 |
mikaeljf |
add wave -noupdate -group {RX FIFO} -divider Control
|
| 221 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/d
|
| 222 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write
|
| 223 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write_enable
|
| 224 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk1
|
| 225 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst1
|
| 226 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read
|
| 227 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read_enable
|
| 228 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk2
|
| 229 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst2
|
| 230 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_full
|
| 231 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/q
|
| 232 |
|
|
add wave -noupdate -group {RX FIFO} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_empty
|
| 233 |
|
|
add wave -noupdate -group {RX FIFO} -divider FIFO_1_1
|
| 234 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[31]}
|
| 235 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[30]}
|
| 236 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[29]}
|
| 237 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[28]}
|
| 238 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[27]}
|
| 239 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[26]}
|
| 240 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[25]}
|
| 241 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[24]}
|
| 242 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[23]}
|
| 243 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[22]}
|
| 244 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[21]}
|
| 245 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[20]}
|
| 246 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[19]}
|
| 247 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[18]}
|
| 248 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[17]}
|
| 249 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[16]}
|
| 250 |
|
|
add wave -noupdate -group {RX FIFO} -divider FIFO_1_0
|
| 251 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[15]}
|
| 252 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[14]}
|
| 253 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[13]}
|
| 254 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[12]}
|
| 255 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[11]}
|
| 256 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[10]}
|
| 257 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[9]}
|
| 258 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[8]}
|
| 259 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[7]}
|
| 260 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[6]}
|
| 261 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[5]}
|
| 262 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[4]}
|
| 263 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[3]}
|
| 264 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[2]}
|
| 265 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[1]}
|
| 266 |
|
|
add wave -noupdate -group {RX FIFO} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[0]}
|
| 267 |
19 |
mikaeljf |
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/write
|
| 268 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/read
|
| 269 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
|
| 270 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
|
| 271 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
|
| 272 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/bte_i
|
| 273 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cti_i
|
| 274 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init
|
| 275 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
|
| 276 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
|
| 277 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
|
| 278 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
|
| 279 |
|
|
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
|
| 280 |
69 |
mikaeljf |
add wave -noupdate -expand -group {DDR2 IF} -divider FSM
|
| 281 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
| 282 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Controller side}
|
| 283 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Clock & reset}
|
| 284 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst
|
| 285 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
|
| 286 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Tx Data}
|
| 287 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
| 288 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
| 289 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
| 290 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Rx Data}
|
| 291 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o
|
| 292 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider {SDRAM side}
|
| 293 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider Address
|
| 294 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/ba_pad_o
|
| 295 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/addr_pad_o
|
| 296 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Data & mask}
|
| 297 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io
|
| 298 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dm_rdqs_pad_io
|
| 299 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider {Clock & strobe}
|
| 300 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cke_pad_o
|
| 301 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o
|
| 302 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_n_pad_o
|
| 303 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_o
|
| 304 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ck_fb_pad_i
|
| 305 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/dqs_oe
|
| 306 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_pad_io
|
| 307 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/dqs_n_pad_io
|
| 308 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal /versatile_mem_ctrl_tb/dut/rdqs_n_pad_i
|
| 309 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -divider Command
|
| 310 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cs_n_pad_o
|
| 311 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/ras_pad_o
|
| 312 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/cas_pad_o
|
| 313 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/we_pad_o
|
| 314 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/odt_pad_o
|
| 315 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/wb_rst
|
| 316 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
|
| 317 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
|
| 318 |
|
|
add wave -noupdate -expand -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
| 319 |
|
|
add wave -noupdate -divider {New Divider}
|
| 320 |
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
|
| 321 |
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
|
| 322 |
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
|
| 323 |
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
|
| 324 |
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
|
| 325 |
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
|
| 326 |
|
|
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
|
| 327 |
|
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
|
| 328 |
|
|
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
|
| 329 |
|
|
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
|
| 330 |
|
|
add wave -noupdate -divider TEMP
|
| 331 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/rx_dat_o
|
| 332 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_i
|
| 333 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg
|
| 334 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_we
|
| 335 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_reg
|
| 336 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_dly
|
| 337 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg
|
| 338 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_dly
|
| 339 |
|
|
add wave -noupdate -divider tmp
|
| 340 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/wb_dat_i_v
|
| 341 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/wb_dat_i
|
| 342 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_fifo_di
|
| 343 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/d
|
| 344 |
|
|
add wave -noupdate -divider tmp
|
| 345 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/d
|
| 346 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/write
|
| 347 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/write_enable
|
| 348 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/clk1
|
| 349 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/rst1
|
| 350 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_adr
|
| 351 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_data
|
| 352 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/read_enable
|
| 353 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/clk2
|
| 354 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/rst2
|
| 355 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_full
|
| 356 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/q
|
| 357 |
|
|
add wave -noupdate -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_empty
|
| 358 |
|
|
add wave -noupdate -divider
|
| 359 |
|
|
add wave -noupdate -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
|
| 360 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
|
| 361 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
|
| 362 |
|
|
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/fifo_rd_adr
|
| 363 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_o
|
| 364 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
|
| 365 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_tx
|
| 366 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_tx_reg
|
| 367 |
|
|
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_o
|
| 368 |
19 |
mikaeljf |
TreeUpdate [SetDefaultTree]
|
| 369 |
69 |
mikaeljf |
WaveRestoreCursors {{Cursor 1} {286644100 ps} 0}
|
| 370 |
|
|
configure wave -namecolwidth 287
|
| 371 |
|
|
configure wave -valuecolwidth 136
|
| 372 |
19 |
mikaeljf |
configure wave -justifyvalue left
|
| 373 |
|
|
configure wave -signalnamewidth 0
|
| 374 |
|
|
configure wave -snapdistance 10
|
| 375 |
|
|
configure wave -datasetprefix 0
|
| 376 |
|
|
configure wave -rowmargin 4
|
| 377 |
|
|
configure wave -childrowmargin 2
|
| 378 |
|
|
configure wave -gridoffset 0
|
| 379 |
|
|
configure wave -gridperiod 1
|
| 380 |
|
|
configure wave -griddelta 40
|
| 381 |
|
|
configure wave -timeline 0
|
| 382 |
|
|
configure wave -timelineunits ns
|
| 383 |
|
|
update
|
| 384 |
69 |
mikaeljf |
WaveRestoreZoom {286559678 ps} {286728522 ps}
|
