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mikaeljf |
# Usage:
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# cd /versatile_mem_ctrl/trunk/syn/altera/run/
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# quartus_sh -t ../bin/versatile_memory_controller.tcl
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15 |
mikaeljf |
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# Load Quartus II Tcl Project package
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package require ::quartus::project
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# Add the next line to get the execute_flow command
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package require ::quartus::flow
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set need_to_close_project 0
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set make_assignments 1
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# Check that the right project is open
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if {[is_project_open]} {
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if {[string compare $quartus(project) "versatile_memory_controller"]} {
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puts "Project versatile_memory_controller is not open"
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set make_assignments 0
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}
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} else {
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# Only open if not already open
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if {[project_exists versatile_memory_controller]} {
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75 |
mikaeljf |
project_open -revision versatile_mem_ctrl_top versatile_memory_controller
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15 |
mikaeljf |
} else {
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75 |
mikaeljf |
project_new -revision versatile_mem_ctrl_top versatile_memory_controller
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15 |
mikaeljf |
}
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set need_to_close_project 1
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}
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# Make assignments
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if {$make_assignments} {
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set_global_assignment -name FAMILY "Stratix III"
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:18:52 DECEMBER 14, 2009"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name SEARCH_PATH core_prbs/rtl/
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set_global_assignment -name SEARCH_PATH core_prbs/
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set_global_assignment -name SEARCH_PATH NPU1C_XCVR_reconfig/
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set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/
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set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/rate_match_fifo/
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set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/tx_phase_comp_fifo/
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set_global_assignment -name SEARCH_PATH altera/90/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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75 |
mikaeljf |
set_global_assignment -name MISC_FILE /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run/versatile_mem_ctrl_top.dpf
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15 |
mikaeljf |
set_global_assignment -name SDC_FILE ../bin/versatile_memory_controller.sdc
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set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/versatile_mem_ctrl_ip.v
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set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run -section_id eda_simulation
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# Commit assignments
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export_assignments
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# Compile
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execute_flow -compile
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# Close project
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if {$need_to_close_project} {
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project_close
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}
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}
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