1 |
20 |
mikaeljf |
# Usage:
|
2 |
|
|
# cd /versatile_mem_ctrl/trunk/syn/altera/run/
|
3 |
|
|
# quartus_sh -t ../bin/versatile_memory_controller.tcl
|
4 |
15 |
mikaeljf |
|
5 |
|
|
# Load Quartus II Tcl Project package
|
6 |
|
|
package require ::quartus::project
|
7 |
|
|
|
8 |
|
|
# Add the next line to get the execute_flow command
|
9 |
|
|
package require ::quartus::flow
|
10 |
|
|
|
11 |
|
|
set need_to_close_project 0
|
12 |
|
|
set make_assignments 1
|
13 |
|
|
|
14 |
|
|
# Check that the right project is open
|
15 |
|
|
if {[is_project_open]} {
|
16 |
|
|
if {[string compare $quartus(project) "versatile_memory_controller"]} {
|
17 |
|
|
puts "Project versatile_memory_controller is not open"
|
18 |
|
|
set make_assignments 0
|
19 |
|
|
}
|
20 |
|
|
} else {
|
21 |
|
|
# Only open if not already open
|
22 |
|
|
if {[project_exists versatile_memory_controller]} {
|
23 |
75 |
mikaeljf |
project_open -revision versatile_mem_ctrl_top versatile_memory_controller
|
24 |
15 |
mikaeljf |
} else {
|
25 |
75 |
mikaeljf |
project_new -revision versatile_mem_ctrl_top versatile_memory_controller
|
26 |
15 |
mikaeljf |
}
|
27 |
|
|
set need_to_close_project 1
|
28 |
|
|
}
|
29 |
|
|
|
30 |
|
|
# Make assignments
|
31 |
|
|
if {$make_assignments} {
|
32 |
|
|
set_global_assignment -name FAMILY "Stratix III"
|
33 |
|
|
set_global_assignment -name DEVICE AUTO
|
34 |
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
|
35 |
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:18:52 DECEMBER 14, 2009"
|
36 |
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
|
37 |
|
|
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
38 |
|
|
set_global_assignment -name SEARCH_PATH core_prbs/rtl/
|
39 |
|
|
set_global_assignment -name SEARCH_PATH core_prbs/
|
40 |
|
|
set_global_assignment -name SEARCH_PATH NPU1C_XCVR_reconfig/
|
41 |
|
|
set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/
|
42 |
|
|
set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/rate_match_fifo/
|
43 |
|
|
set_global_assignment -name SEARCH_PATH Bacchus_PTP_ALTLVDS_DYN_LINERATE_MULTICHANNEL/tx_phase_comp_fifo/
|
44 |
|
|
set_global_assignment -name SEARCH_PATH altera/90/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter/
|
45 |
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
46 |
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
47 |
|
|
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
48 |
|
|
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
49 |
75 |
mikaeljf |
set_global_assignment -name MISC_FILE /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run/versatile_mem_ctrl_top.dpf
|
50 |
15 |
mikaeljf |
set_global_assignment -name SDC_FILE ../bin/versatile_memory_controller.sdc
|
51 |
|
|
set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/versatile_mem_ctrl_ip.v
|
52 |
|
|
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY /home/mikael/opencores/versatile_mem_ctrl/trunk/syn/altera/run -section_id eda_simulation
|
53 |
|
|
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
|
54 |
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
55 |
|
|
|
56 |
|
|
# Commit assignments
|
57 |
|
|
export_assignments
|
58 |
|
|
|
59 |
|
|
# Compile
|
60 |
|
|
execute_flow -compile
|
61 |
|
|
|
62 |
|
|
|
63 |
|
|
# Close project
|
64 |
|
|
if {$need_to_close_project} {
|
65 |
|
|
project_close
|
66 |
|
|
}
|
67 |
|
|
}
|