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[/] [vg_z80_sbc/] [trunk/] [rtl/] [async_fifo.v] - Blame information for rev 35

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1 3 hharte
//==========================================
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// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
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// Coder    : Alex Claros F.
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// Date     : 15/May/2005.
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// Notes    : This implementation is based on the article 
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//            'Asynchronous FIFO in Virtex-II FPGAs'
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//            writen by Peter Alfke. This TechXclusive 
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//            article can be downloaded from the
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//            Xilinx website. It has some minor modifications.
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//=========================================
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`timescale 1ns / 1ps
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module async_fifo
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  #(parameter    DATA_WIDTH    = 8,
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                 ADDRESS_WIDTH = 4,
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                 FIFO_DEPTH    = (1 << ADDRESS_WIDTH))
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     //Reading port
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    (output wire [DATA_WIDTH-1:0]        Data_out,
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     output reg                          Empty_out,
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     input wire                          ReadEn_in,
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     input wire                          RClk,
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     //Writing port.     
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     input wire  [DATA_WIDTH-1:0]        Data_in,
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     output reg                          Full_out,
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     input wire                          WriteEn_in,
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     input wire                          WClk,
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     input wire                          Clear_in);
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    /////Internal connections & variables//////
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    reg   [DATA_WIDTH-1:0]              Mem [FIFO_DEPTH-1:0];
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    wire  [ADDRESS_WIDTH-1:0]           pNextWordToWrite, pNextWordToRead;
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    wire                                EqualAddresses;
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    wire                                NextWriteAddressEn, NextReadAddressEn;
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    wire                                Set_Status, Rst_Status;
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    reg                                 Status;
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    wire                                PresetFull, PresetEmpty;
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    //////////////Code///////////////
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    //Data ports logic:
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    //(Uses a dual-port RAM).
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    //'Data_out' logic:
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    assign  Data_out = Mem[pNextWordToRead];
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//    always @ (posedge RClk)
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//        if (!PresetEmpty)
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//            Data_out <= Mem[pNextWordToRead];
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//        if (ReadEn_in & !Empty_out)
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    //'Data_in' logic:
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    always @ (posedge WClk)
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        if (WriteEn_in & !Full_out)
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            Mem[pNextWordToWrite] <= Data_in;
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    //Fifo addresses support logic: 
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    //'Next Addresses' enable logic:
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    assign NextWriteAddressEn = WriteEn_in & ~Full_out;
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    assign NextReadAddressEn  = ReadEn_in  & ~Empty_out;
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    //Addreses (Gray counters) logic:
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    GrayCounter #(
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                .COUNTER_WIDTH( ADDRESS_WIDTH )
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    ) GrayCounter_pWr (
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        .GrayCount_out(pNextWordToWrite),
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        .Enable_in(NextWriteAddressEn),
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        .Clear_in(Clear_in),
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        .Clk(WClk)
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       );
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    GrayCounter #(
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                .COUNTER_WIDTH( ADDRESS_WIDTH )
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    ) GrayCounter_pRd (
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        .GrayCount_out(pNextWordToRead),
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        .Enable_in(NextReadAddressEn),
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        .Clear_in(Clear_in),
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        .Clk(RClk)
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       );
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    //'EqualAddresses' logic:
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    assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
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    //'Quadrant selectors' logic:
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    assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
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                         (pNextWordToWrite[ADDRESS_WIDTH-1] ^  pNextWordToRead[ADDRESS_WIDTH-2]);
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    assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^  pNextWordToRead[ADDRESS_WIDTH-1]) &
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                         (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
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    //'Status' latch logic:
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    always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
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        if (Rst_Status | Clear_in)
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            Status = 0;  //Going 'Empty'.
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        else if (Set_Status)
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            Status = 1;  //Going 'Full'.
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    //'Full_out' logic for the writing port:
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    assign PresetFull = Status & EqualAddresses;  //'Full' Fifo.
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    always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
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        if (PresetFull)
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            Full_out <= 1;
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        else
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            Full_out <= 0;
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    //'Empty_out' logic for the reading port:
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    assign PresetEmpty = ~Status & EqualAddresses;  //'Empty' Fifo.
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    always @ (posedge RClk, posedge PresetEmpty)  //D Flip-Flop w/ Asynchronous Preset.
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        if (PresetEmpty)
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            Empty_out <= 1;
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        else
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            Empty_out <= 0;
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endmodule

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