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[/] [vg_z80_sbc/] [trunk/] [rtl/] [ddr_clkgen.v] - Blame information for rev 35

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1 3 hharte 
//---------------------------------------------------------------------------
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// Wishbone DDR Controller
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//
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// (c) Joerg Bornschein (<jb@capsec.org>)
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//---------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`include "ddr_include.v"
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module ddr_clkgen
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#(
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        parameter phase_shift  = 0,
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        parameter clk_multiply = 13,
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        parameter clk_divide   = 5
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) (
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        input        clk,
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        input        reset,
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        output       locked,
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        //
20 20 hharte 
        output       read_clk,
21 3 hharte 
        output       write_clk,
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        output       write_clk90,
23 20 hharte 
        // DCM phase shift control
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        output   reg ps_ready,
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        input        ps_up,
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        input        ps_down
27 3 hharte 
);
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29 
 
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//----------------------------------------------------------------------------
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// ~133 MHz DDR Clock generator
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//----------------------------------------------------------------------------
33 20 hharte 
wire  read_clk_u;
34 3 hharte 
wire  dcm_fx_locked;
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36 20 hharte 
DCM #(
37 3 hharte 
        .CLKDV_DIVIDE(2.0),          // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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                                 //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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        .CLKFX_DIVIDE(clk_divide),   // Can be any integer from 1 to 32
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        .CLKFX_MULTIPLY(clk_multiply), // Can be any integer from 2 to 32
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        .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
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        .CLKIN_PERIOD(),             // Specify period of input clock
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        .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
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        .CLK_FEEDBACK("NONE"),       // Specify clock feedback of NONE, 1X or 2X
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        .DESKEW_ADJUST("SOURCE_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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                                 //   an integer from 0 to 15
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        .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
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        .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
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        .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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        .FACTORY_JF(16'hC080),       // FACTORY JF values
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        .PHASE_SHIFT(0),             // Amount of fixed phase shift from -255 to 255
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        .STARTUP_WAIT("FALSE")       // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) dcm_fx (
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        .DSSEN(),
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        .CLK0(),                   // 0 degree DCM CLK output
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        .CLK180(),                 // 180 degree DCM CLK output
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        .CLK270(),                 // 270 degree DCM CLK output
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        .CLK2X(),                  // 2X DCM CLK output
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        .CLK2X180(),               // 2X, 180 degree DCM CLK out
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        .CLK90(),                  // 90 degree DCM CLK output
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        .CLKDV(),                  // Divided DCM CLK out (CLKDV_DIVIDE)
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        .CLKFX(    read_clk_u ),   // DCM CLK synthesis out (M/D)
63 20 hharte 
        .CLKFX180(),               // 180 degree CLK synthesis out
64 3 hharte 
        .LOCKED(   dcm_fx_locked), // DCM LOCK status output
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        .PSDONE(),                 // Dynamic phase adjust done output
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        .STATUS(),                 // 8-bit DCM status bits output
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        .CLKFB(),                  // DCM clock feedback
68 20 hharte 
        .CLKIN(    clk   ),        // Clock input (from IBUFG, BUFG or DCM)
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        .PSCLK(    gnd   ),        // Dynamic phase adjust clock input
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        .PSEN(     gnd   ),        // Dynamic phase adjust enable input
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        .PSINCDEC( gnd   ),        // Dynamic phase adjust increment/decrement
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        .RST(      reset )         // DCM asynchronous reset input
73 3 hharte 
);
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75 
//----------------------------------------------------------------------------
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// BUFG read clock
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//----------------------------------------------------------------------------
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BUFG bufg_fx_clk (
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        .O(read_clk),             // Clock buffer output
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        .I(read_clk_u)            // Clock buffer input
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);
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83 
//----------------------------------------------------------------------------
84 20 hharte 
// Phase shifted clock for write path
85 3 hharte 
//----------------------------------------------------------------------------
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wire  phase_dcm_reset;
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wire  phase_dcm_locked;
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wire  write_clk_u, write_clk90_u, write_clk180_u, write_clk270_u;
89 20 hharte 
reg   psen, psincdec;
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wire  psdone;
91 3 hharte 
 
92 20 hharte 
DCM #(
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        .CLKDV_DIVIDE(2.0),     // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
94 3 hharte 
                            //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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        .CLKFX_DIVIDE(2),       // Can be any integer from 1 to 32
96 20 hharte 
        .CLKFX_MULTIPLY(2),     // Can be any integer from 2 to 32
97 3 hharte 
        .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
98 20 hharte 
        .CLKIN_PERIOD(),        // Specify period of input clock
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        .CLK_FEEDBACK("1X"),    // Specify clock feedback of NONE, 1X or 2X
100 3 hharte 
        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
101 20 hharte 
                                          //   an integer from 0 to 15
102 3 hharte 
        .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
103 
        .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
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        .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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        .FACTORY_JF(16'hC080),   // FACTORY JF values
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        .CLKOUT_PHASE_SHIFT("VARIABLE"), // Specify phase shift of NONE, FIXED or VARIABLE
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        .PHASE_SHIFT( phase_shift ), // Amount of fixed phase shift from -255 to 255
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        .STARTUP_WAIT("FALSE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) dcm_phase (
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        .DSSEN(),
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        .CLK0(   write_clk_u ),      // 0 degree DCM CLK output
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        .CLK90(  write_clk90_u ),    // 90 degree DCM CLK output
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        .CLK180( write_clk180_u ),   // 180 degree DCM CLK output
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        .CLK270( write_clk270_u ),   // 270 degree DCM CLK output
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        .CLK2X(),                    // 2X DCM CLK output
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        .CLK2X180(),                 // 2X, 180 degree DCM CLK out
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        .CLKDV(),                    // Divided DCM CLK out (CLKDV_DIVIDE)
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        .CLKFX(),                    // DCM CLK synthesis out (M/D)
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        .CLKFX180(),                 // 180 degree CLK synthesis out
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        .LOCKED( phase_dcm_locked ), // DCM LOCK status output
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        .STATUS(),                   // 8-bit DCM status bits output
122 20 hharte 
        .CLKFB( write_clk ),         // DCM clock feedback
123 3 hharte 
        .CLKIN( read_clk ),          // Clock input (from IBUFG, BUFG or DCM)
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        .PSCLK( clk ),               // Dynamic phase adjust clock input
125 20 hharte 
        .PSEN( psen ),               // Dynamic phase adjust enable input
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        .PSINCDEC( psincdec ),       // Dynamic phase adjust increment/decrement
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        .PSDONE( psdone ),           // Dynamic phase adjust done output
128 3 hharte 
        .RST( phase_dcm_reset )      // DCM asynchronous reset input
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);
130 
 
131 20 hharte 
// delayed reset for phase shifting DCM
132 3 hharte 
reg [3:0] reset_counter;
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assign phase_dcm_reset = reset | (reset_counter != 0);
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always @(posedge clk)
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begin
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        if (reset)
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                reset_counter <= 1;
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        else begin
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                if (dcm_fx_locked & (reset_counter != 0))
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                        reset_counter <= reset_counter + 1;
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        end
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end
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145 20 hharte 
//----------------------------------------------------------------------------
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// DCM phase shifting state machine
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//----------------------------------------------------------------------------
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parameter s_init     = 0;
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parameter s_idle     = 1;
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parameter s_waitdone = 2;
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parameter s_waitdone2= 3;
152 3 hharte 
 
153 20 hharte 
reg [1:0] state;
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always @(posedge clk)
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begin
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        if (reset) begin
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                state     <= s_init;
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                psen      <= 0;
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                ps_ready  <= 0;
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        end else begin
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                case (state)
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                s_init: begin
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                        if (phase_dcm_locked) begin
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                                ps_ready  <= 1;
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                                state     <= s_idle;
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                        end
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                end
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                s_idle: begin
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                        if (ps_up) begin
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                                ps_ready  <= 0;
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                                psen      <= 1;
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                                psincdec  <= 1;
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                                state     <= s_waitdone;
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                        end else if (ps_down) begin
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                                ps_ready  <= 0;
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                                psen      <= 1;
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                                psincdec  <= 0;
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                                state     <= s_waitdone;
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                        end
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                end
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                s_waitdone: begin
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                        psen     <= 0;
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                        if (psdone) begin
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                                state     <= s_waitdone2;
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                        end
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                end
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                s_waitdone2: begin
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                        if (~ps_up && ~ps_down) begin
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                                ps_ready  <= 1;
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                                state     <= s_idle;
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                        end
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                end
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                endcase
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        end
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end
197 
 
198 3 hharte 
//----------------------------------------------------------------------------
199 
// BUFG write clock
200 
//----------------------------------------------------------------------------
201 
BUFG bufg_write_clk (
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        .O(write_clk  ),          // Clock buffer output
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        .I(write_clk_u)           // Clock buffer input
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);
205 
 
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BUFG bufg_write_clk90 (
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        .O(write_clk90  ),        // Clock buffer output
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        .I(write_clk90_u)         // Clock buffer input
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);
210 
 
211 
//----------------------------------------------------------------------------
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// LOCKED logic
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//----------------------------------------------------------------------------
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reg phase_dcm_locked_delayed;
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216 
always @(posedge write_clk)
217 
begin
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        phase_dcm_locked_delayed <= phase_dcm_locked;
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end
220 
 
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assign locked = ~reset & phase_dcm_locked_delayed;
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endmodule

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