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//----------------------------------------------------------------------------
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// Wishbone DDR Controller
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//
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// (c) Joerg Bornschein (<jb@capsec.org>)
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//----------------------------------------------------------------------------
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`ifdef WBDDR_INCLUDE_V
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`else
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`define WBDDR_INCLUDE_V
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`timescale 1ns/10ps
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//----------------------------------------------------------------------------
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// Frequency and timeouts
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//----------------------------------------------------------------------------
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`define SYS_CLK_FREQUENCY 50000 // in kHz
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`define DDR_CLK_MULTIPLY 5
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`define DDR_CLK_DIVIDE 2
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//----------------------------------------------------------------------------
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// Width
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//----------------------------------------------------------------------------
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`define CMD_WIDTH 3
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`define A_WIDTH 13
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`define BA_WIDTH 2
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`define DQ_WIDTH 16
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`define DQS_WIDTH 2
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`define DM_WIDTH 2
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`define RFIFO_WIDTH (2 * `DQ_WIDTH )
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`define WFIFO_WIDTH (2 * (`DQ_WIDTH + `DM_WIDTH))
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`define CBA_WIDTH (`CMD_WIDTH+`BA_WIDTH+`A_WIDTH)
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// Ranges
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`define CMD_RNG (`CMD_WIDTH-1):0
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`define A_RNG (`A_WIDTH-1):0
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`define BA_RNG (`BA_WIDTH-1):0
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`define DQ_RNG (`DQ_WIDTH-1):0
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`define DQS_RNG (`DQS_WIDTH-1):0
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`define DM_RNG (`DM_WIDTH-1):0
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`define RFIFO_RNG (`RFIFO_WIDTH-1):0
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`define WFIFO_RNG (`WFIFO_WIDTH-1):0
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`define WFIFO_D0_RNG (1*`DQ_WIDTH-1):0
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`define WFIFO_D1_RNG (2*`DQ_WIDTH-1):(`DQ_WIDTH)
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`define WFIFO_M0_RNG (2*`DQ_WIDTH+1*`DM_WIDTH-1):(2*`DQ_WIDTH+0*`DM_WIDTH)
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`define WFIFO_M1_RNG (2*`DQ_WIDTH+2*`DM_WIDTH-1):(2*`DQ_WIDTH+1*`DM_WIDTH)
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`define CBA_RNG (`CBA_WIDTH-1):0
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`define CBA_CMD_RNG (`CBA_WIDTH-1):(`CBA_WIDTH-3)
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`define CBA_BA_RNG (`CBA_WIDTH-4):(`CBA_WIDTH-5)
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`define CBA_A_RNG (`CBA_WIDTH-6):0
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`define ROW_RNG 12:0
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//----------------------------------------------------------------------------
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// Configuration registers
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//----------------------------------------------------------------------------
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`define DDR_INIT_EMRS `A_WIDTH'b0000000000000 // DLL enable
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`define DDR_INIT_MRS1 `A_WIDTH'b0000101100011 // BURST=8, CL=2.5, DLL RESET
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`define DDR_INIT_MRS2 `A_WIDTH'b0000001100011 // BURST=8, CL=2.5
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//----------------------------------------------------------------------------
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// FML constants
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//----------------------------------------------------------------------------
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`define FML_ADR_RNG 25:4
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`define FML_ADR_BA_RNG 25:24
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`define FML_ADR_ROW_RNG 23:11
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`define FML_ADR_COL_RNG 10:4
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`define FML_DAT_RNG 31:0
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`define FML_BE_RNG 3:0
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//----------------------------------------------------------------------------
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// DDR constants
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//----------------------------------------------------------------------------
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`define DDR_CMD_NOP 3'b111
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`define DDR_CMD_ACT 3'b011
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`define DDR_CMD_READ 3'b101
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`define DDR_CMD_WRITE 3'b100
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`define DDR_CMD_TERM 3'b110
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`define DDR_CMD_PRE 3'b010
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`define DDR_CMD_AR 3'b001
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`define DDR_CMD_MRS 3'b000
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`define ADR_BA_RNG 25:24
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`define ADR_ROW_RNG 23:11
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`define ADR_COL_RNG 10:4
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`define T_MRD 2 // Mode register set
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`define T_RP 2 // Precharge Command Period
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`define T_RFC 8 // Precharge Command Period
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//----------------------------------------------------------------------------
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// Buffer Cache
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//----------------------------------------------------------------------------
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`define WAY_WIDTH (`WB_DAT_WIDTH + `WB_SEL_WIDTH)
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`define WAY_LINE_RNG (`WAY_WIDTH-1):0
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`define WAY_DAT_RNG 31:0
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`define WAY_VALID_RNG 35:32
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`define TAG_LINE_RNG 32:0
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`define TAG_LINE_TAG0_RNG 14:0
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`define TAG_LINE_TAG1_RNG 29:15
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`define TAG_LINE_DIRTY0_RNG 30
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`define TAG_LINE_DIRTY1_RNG 31
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`define TAG_LINE_LRU_RNG 32
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//----------------------------------------------------------------------------
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// Whishbone constants
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//----------------------------------------------------------------------------
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`define WB_ADR_WIDTH 32
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`define WB_DAT_WIDTH 32
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`define WB_SEL_WIDTH 4
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`define WB_ADR_RNG (`WB_ADR_WIDTH-1):0
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`define WB_DAT_RNG (`WB_DAT_WIDTH-1):0
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`define WB_SEL_RNG (`WB_SEL_WIDTH-1):0
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`define WB_WORD_RNG 3:2
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`define WB_SET_RNG 10:4
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`define WB_TAG_RNG 25:11
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`endif
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