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[/] [vg_z80_sbc/] [trunk/] [rtl/] [ddr_init.v] - Blame information for rev 35

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//----------------------------------------------------------------------------
// Wishbone DDR Controller
// 
// (c) Joerg Bornschein (<jb@capsec.org>)
//----------------------------------------------------------------------------
`include "ddr_include.v"
 
module ddr_init
#(
        parameter               wait200_init = 26
) (
        input                   clk,
        input                   reset,
        input                   pulse78,
        output                  wait200,
        output                  init_done,
        //
        output                  mngt_req,
        input                   mngt_ack,
        output [`CBA_RNG]       mngt_cba       // CMD, BA and ADDRESS
);
 
reg              cmd_req_reg;
reg [`CMD_RNG]   cmd_cmd_reg;
reg [ `BA_RNG]   cmd_ba_reg;
reg [  `A_RNG]   cmd_a_reg;
reg [7:0]        cmd_idle_reg;
 
//---------------------------------------------------------------------------
// Initial 200us delay
//---------------------------------------------------------------------------
 
// `define WAIT200_INIT 26
// `define WAIT200_INIT 1
 
reg [4:0] wait200_counter;
reg       wait200_reg;
 
always @(posedge clk)
begin
        if (reset) begin
                wait200_reg     <= 1;
                wait200_counter <= wait200_init;
        end else begin
                if (wait200_counter == 0)
                        wait200_reg <= 0;
 
                if (wait200_reg & pulse78)
                        wait200_counter <= wait200_counter - 1;
        end
end
 
assign wait200 = wait200_reg;
 
//----------------------------------------------------------------------------
// DDR Initialization State Machine
//----------------------------------------------------------------------------
 
parameter s_wait200 = 0;
parameter s_init1   = 1;
parameter s_init2   = 2;
parameter s_init3   = 3;
parameter s_init4   = 4;
parameter s_init5   = 5;
parameter s_init6   = 6;
parameter s_waitack = 7;
parameter s_idle    = 8;
 
reg [3:0]        state;
reg              init_done_reg;
 
assign mngt_cba     = {cmd_cmd_reg, cmd_ba_reg, cmd_a_reg};
assign mngt_req     = cmd_req_reg;
assign mngt_pri_req = ~init_done_reg;
assign init_done    = init_done_reg;
 
always @(posedge clk or posedge reset)
begin
        if (reset) begin
                init_done_reg <= 0;
                state         <= s_wait200;
                cmd_idle_reg  <= 0;
                cmd_req_reg   <= 0;
                cmd_cmd_reg   <= 'b0;
                cmd_ba_reg    <= 'b0;
                cmd_a_reg     <= 'b0;
        end else begin
                case (state)
                        s_wait200: begin
                                if (~wait200_reg) begin
                                                state         <= s_init1;
                                                cmd_req_reg   <= 1;
                                                cmd_cmd_reg   <= `DDR_CMD_PRE;   // PRE ALL
                                                cmd_a_reg[10] <= 1'b1;
                                        end
                                end
                        s_init1: begin
                                        if (mngt_ack) begin
                                                state         <= s_init2;
                                                cmd_req_reg   <= 1;
                                                cmd_cmd_reg   <= `DDR_CMD_MRS;   // EMRS
                                                cmd_ba_reg    <= 2'b01;
                                                cmd_a_reg     <= `DDR_INIT_EMRS;
                                        end
                                end
                        s_init2: begin
                                        if (mngt_ack) begin
                                                state         <= s_init3;
                                                cmd_req_reg   <= 1;
                                                cmd_cmd_reg   <= `DDR_CMD_MRS;   // MRS
                                                cmd_ba_reg    <= 2'b00;
                                                cmd_a_reg     <= `DDR_INIT_MRS1;
                                        end
                                end
                        s_init3: begin
                                        if (mngt_ack) begin
                                                state         <= s_init4;
                                                cmd_req_reg   <= 1;
                                                cmd_cmd_reg   <= `DDR_CMD_PRE;   // PRE ALL
                                                cmd_a_reg[10] <= 1'b1;
                                        end
                                end
                        s_init4: begin
                                        if (mngt_ack) begin
                                                state         <= s_init5;
                                                cmd_req_reg   <= 1;
                                                cmd_cmd_reg   <= `DDR_CMD_AR;   // AR
                                        end
                                end
                        s_init5: begin
                                        if (mngt_ack) begin
                                                state         <= s_init6;
                                                cmd_req_reg   <= 1;
                                                cmd_cmd_reg   <= `DDR_CMD_AR;   // AR
                                        end
                                end
                        s_init6: begin
                                        if (mngt_ack) begin
                                                init_done_reg <= 1;
                                                state         <= s_waitack;
                                                cmd_req_reg   <= 1;
                                                cmd_cmd_reg   <= `DDR_CMD_MRS;  // MRS
                                                cmd_ba_reg    <= 2'b00;
                                                cmd_a_reg     <= `DDR_INIT_MRS2;
                                        end
                                end
                        s_waitack: begin
                                        if (mngt_ack) begin
                                                state         <= s_idle;
                                                cmd_req_reg   <= 0;
                                                cmd_cmd_reg   <= 'b0;
                                                cmd_ba_reg    <= 'b0;
                                                cmd_a_reg     <= 'b0;
                                        end
                                end
                        s_idle: begin
                                end
                endcase ///////////////////////////////////////// INIT STATE MACHINE ///
        end
end
 
 
endmodule
 

Line No.	Rev	Author	Line
1	3	hharte	`//----------------------------------------------------------------------------`
2			`// Wishbone DDR Controller`
3			`//`
4			`// (c) Joerg Bornschein (<jb@capsec.org>)`
5			`//----------------------------------------------------------------------------`
6			`include "ddr_include.v"
7
8			`module ddr_init`
9			`#(`
10			`parameter wait200_init = 26`
11			`) (`
12			`input clk,`
13			`input reset,`
14			`input pulse78,`
15			`output wait200,`
16			`output init_done,`
17			`//`
18			`output mngt_req,`
19			`input mngt_ack,`
20			output [`CBA_RNG] mngt_cba // CMD, BA and ADDRESS
21			`);`
22
23			`reg cmd_req_reg;`
24			reg [`CMD_RNG] cmd_cmd_reg;
25			reg [ `BA_RNG] cmd_ba_reg;
26			reg [ `A_RNG] cmd_a_reg;
27			`reg [7:0] cmd_idle_reg;`
28
29			`//---------------------------------------------------------------------------`
30			`// Initial 200us delay`
31			`//---------------------------------------------------------------------------`
32
33			// `define WAIT200_INIT 26
34			// `define WAIT200_INIT 1
35
36			`reg [4:0] wait200_counter;`
37			`reg wait200_reg;`
38
39			`always @(posedge clk)`
40			`begin`
41			`if (reset) begin`
42			`wait200_reg <= 1;`
43			`wait200_counter <= wait200_init;`
44			`end else begin`
45			`if (wait200_counter == 0)`
46			`wait200_reg <= 0;`
47
48			`if (wait200_reg & pulse78)`
49			`wait200_counter <= wait200_counter - 1;`
50			`end`
51			`end`
52
53			`assign wait200 = wait200_reg;`
54
55			`//----------------------------------------------------------------------------`
56			`// DDR Initialization State Machine`
57			`//----------------------------------------------------------------------------`
58
59			`parameter s_wait200 = 0;`
60			`parameter s_init1 = 1;`
61			`parameter s_init2 = 2;`
62			`parameter s_init3 = 3;`
63			`parameter s_init4 = 4;`
64			`parameter s_init5 = 5;`
65			`parameter s_init6 = 6;`
66			`parameter s_waitack = 7;`
67			`parameter s_idle = 8;`
68
69			`reg [3:0] state;`
70			`reg init_done_reg;`
71
72			`assign mngt_cba = {cmd_cmd_reg, cmd_ba_reg, cmd_a_reg};`
73			`assign mngt_req = cmd_req_reg;`
74			`assign mngt_pri_req = ~init_done_reg;`
75			`assign init_done = init_done_reg;`
76
77			`always @(posedge clk or posedge reset)`
78			`begin`
79			`if (reset) begin`
80			`init_done_reg <= 0;`
81			`state <= s_wait200;`
82			`cmd_idle_reg <= 0;`
83			`cmd_req_reg <= 0;`
84			`cmd_cmd_reg <= 'b0;`
85			`cmd_ba_reg <= 'b0;`
86			`cmd_a_reg <= 'b0;`
87			`end else begin`
88			`case (state)`
89			`s_wait200: begin`
90			`if (~wait200_reg) begin`
91			`state <= s_init1;`
92			`cmd_req_reg <= 1;`
93			cmd_cmd_reg <= `DDR_CMD_PRE; // PRE ALL
94			`cmd_a_reg[10] <= 1'b1;`
95			`end`
96			`end`
97			`s_init1: begin`
98			`if (mngt_ack) begin`
99			`state <= s_init2;`
100			`cmd_req_reg <= 1;`
101			cmd_cmd_reg <= `DDR_CMD_MRS; // EMRS
102			`cmd_ba_reg <= 2'b01;`
103			cmd_a_reg <= `DDR_INIT_EMRS;
104			`end`
105			`end`
106			`s_init2: begin`
107			`if (mngt_ack) begin`
108			`state <= s_init3;`
109			`cmd_req_reg <= 1;`
110			cmd_cmd_reg <= `DDR_CMD_MRS; // MRS
111			`cmd_ba_reg <= 2'b00;`
112			cmd_a_reg <= `DDR_INIT_MRS1;
113			`end`
114			`end`
115			`s_init3: begin`
116			`if (mngt_ack) begin`
117			`state <= s_init4;`
118			`cmd_req_reg <= 1;`
119			cmd_cmd_reg <= `DDR_CMD_PRE; // PRE ALL
120			`cmd_a_reg[10] <= 1'b1;`
121			`end`
122			`end`
123			`s_init4: begin`
124			`if (mngt_ack) begin`
125			`state <= s_init5;`
126			`cmd_req_reg <= 1;`
127			cmd_cmd_reg <= `DDR_CMD_AR; // AR
128			`end`
129			`end`
130			`s_init5: begin`
131			`if (mngt_ack) begin`
132			`state <= s_init6;`
133			`cmd_req_reg <= 1;`
134			cmd_cmd_reg <= `DDR_CMD_AR; // AR
135			`end`
136			`end`
137			`s_init6: begin`
138			`if (mngt_ack) begin`
139			`init_done_reg <= 1;`
140			`state <= s_waitack;`
141			`cmd_req_reg <= 1;`
142			cmd_cmd_reg <= `DDR_CMD_MRS; // MRS
143			`cmd_ba_reg <= 2'b00;`
144			cmd_a_reg <= `DDR_INIT_MRS2;
145			`end`
146			`end`
147			`s_waitack: begin`
148			`if (mngt_ack) begin`
149			`state <= s_idle;`
150			`cmd_req_reg <= 0;`
151			`cmd_cmd_reg <= 'b0;`
152			`cmd_ba_reg <= 'b0;`
153			`cmd_a_reg <= 'b0;`
154			`end`
155			`end`
156			`s_idle: begin`
157			`end`
158			`endcase ///////////////////////////////////////// INIT STATE MACHINE ///`
159			`end`
160			`end`
161
162
163			`endmodule`
164

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[/] [vg_z80_sbc/] [trunk/] [rtl/] [ddr_init.v] - Blame information for rev 35