URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [ddr_pulse78.v] - Blame information for rev 35

Line No.	Rev	Author	Line
1	20	hharte	`//----------------------------------------------------------------------------`
2	3	hharte	`// Wishbone DDR Controller`
3			`//`
4			`// (c) Joerg Bornschein (<jb@capsec.org>)`
5	20	hharte	`//----------------------------------------------------------------------------`
6	3	hharte	`include "ddr_include.v"
7
8	20	hharte	`module ddr_pulse78 #(`
9			`parameter clk_freq = 50000000`
10			`) (`
11			`input clk,`
12			`input reset,`
13	3	hharte	`//`
14	20	hharte	`output reg pulse78`
15	3	hharte	`);`
16
17	20	hharte	`//----------------------------------------------------------------------------`
18			`//`
19			`//----------------------------------------------------------------------------`
20			`define PULSE78_RNG 10:0
21	3	hharte
22	20	hharte	`parameter pulse78_init = 78 * (clk_freq/10000000);`
23
24	3	hharte	reg [`PULSE78_RNG] counter;
25
26			`always @(posedge clk)`
27			`begin`
28			`if (reset) begin`
29	20	hharte	`counter <= pulse78_init;`
30			`pulse78 <= 0;`
31	3	hharte	`end else begin`
32			`if (counter == 0) begin`
33	20	hharte	`counter <= pulse78_init;`
34			`pulse78 <= 1'b1;`
35	3	hharte	`end else begin`
36	20	hharte	`counter <= counter - 1;`
37			`pulse78 <= 0;`
38	3	hharte	`end`
39			`end`
40			`end`
41
42			`endmodule`
43