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[/] [vg_z80_sbc/] [trunk/] [rtl/] [rotary.v] - Blame information for rev 36

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//----------------------------------------------------------------------------
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// Decode rotary encoder to clk-syncronous signals
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//
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// (c) Joerg Bornschein (<jb@capsec.org>)
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//----------------------------------------------------------------------------
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module rotary (
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        input        clk,
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        input        reset,
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        input [2:0]  rot,
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        //
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        output       rot_btn,
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        output reg   rot_event,
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        output reg   rot_left
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);
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assign rot_btn = 0;
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//----------------------------------------------------------------------------
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// decode rotary encoder
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//----------------------------------------------------------------------------
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parameter  counter_init = 10000000;
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reg [31:0] counter;
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reg rot_event2;
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reg rot_left2;
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always @(posedge clk)
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begin
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        if (reset)
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                counter <= counter_init;
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        else begin
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                rot_event  <= rot_event2;
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                rot_left   <= rot_left2;
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                rot_event2 <= 0;
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                rot_left2  <= 0;
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                if (counter == 0) begin
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                        counter <= counter_init;
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                        if (rot[0] | rot[1])
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                                rot_event2 <= 1;
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                        if (rot[0])
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                                rot_left2  <= 1;
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                end else
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                        counter <= counter - 1;
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        end
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end
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endmodule

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