URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [uart.v] - Blame information for rev 35

Details | Compare with Previous | View Log


//-----------------------------------------------------
// Design Name : uart 
// File Name   : uart.v
//-----------------------------------------------------
module uart #(
        parameter          freq_hz = 100000000,
        parameter          baud    = 115200
) (
        input              reset,
        input              clk,
        // UART lines
        input              uart_rxd,
        output reg         uart_txd,
        // 
        output reg [7:0]   rx_data,
        output reg         rx_avail,
        output reg         rx_error,
        input              rx_ack,
        input      [7:0]   tx_data,
        input              tx_wr,
        output reg         tx_busy
);
 
parameter divisor = freq_hz/baud/16;
 
//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
reg [15:0] enable16_counter;
 
wire    enable16;
assign  enable16 = (enable16_counter == 0);
 
always @(posedge clk)
begin
        if (reset) begin
                enable16_counter <= divisor-1;
        end else begin
                enable16_counter <= enable16_counter - 1;
                if (enable16_counter == 0) begin
                        enable16_counter <= divisor-1;
                end
        end
end
 
//-----------------------------------------------------------------
// syncronize uart_rxd
//-----------------------------------------------------------------
reg uart_rxd1;
reg uart_rxd2;
 
always @(posedge clk)
begin
        uart_rxd1 <= uart_rxd;
        uart_rxd2 <= uart_rxd1;
end
 
//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg       rx_busy;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [7:0] rxd_reg;
 
always @ (posedge clk)
begin
        if (reset) begin
                rx_busy     <= 0;
                rx_count16  <= 0;
                rx_bitcount <= 0;
                rx_avail    <= 0;
                rx_error    <= 0;
        end else begin
                if (rx_ack) begin
                        rx_avail <= 0;
                        rx_error <= 0;
                end
 
                if (enable16) begin
                        if (!rx_busy) begin           // look for start bit
                                if (!uart_rxd2) begin     //     start bit found
                                        rx_busy     <= 1;
                                        rx_count16  <= 7;
                                        rx_bitcount <= 0;
                                end
                        end else begin
                                rx_count16 <= rx_count16 + 1;
 
                                if (rx_count16 == 0) begin      // sample 
                                        rx_bitcount <= rx_bitcount + 1;
 
                                        if (rx_bitcount == 0) begin          // verify startbit
                                                if (uart_rxd2) begin
                                                        rx_busy <= 0;
                                                end
                                        end else if (rx_bitcount == 9) begin // look for stop bit
                                                rx_busy <= 0;
                                                if (uart_rxd2) begin             //   stop bit ok
                                                        rx_data  <= rxd_reg;
                                                        rx_avail <= 1;
                                                        rx_error <= 0;
                                                end else begin                  //   bas stop bit
                                                        rx_error <= 1;
                                                end
                                        end else begin
                                                rxd_reg <= { uart_rxd2, rxd_reg[7:1] };
                                        end
                                end
                        end
                end
        end
end
 
//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg [3:0] tx_bitcount;
reg [3:0] tx_count16;
reg [7:0] txd_reg;
 
always @ (posedge clk)
begin
        if (reset) begin
                tx_busy     <= 0;
                uart_txd    <= 1;
                tx_count16  <= 0;
        end else begin
                if (tx_wr && !tx_busy) begin
                        txd_reg     <= tx_data;
                        tx_bitcount <= 0;
                        tx_count16  <= 0;
                        tx_busy     <= 1;
                end
 
                if (enable16) begin
                        tx_count16  <= tx_count16 + 1;
 
                        if ((tx_count16 == 0) && tx_busy) begin
                                tx_bitcount <= tx_bitcount + 1;
 
                                if (tx_bitcount == 0) begin
                                        uart_txd <= 'b0;
                                end else if (tx_bitcount ==  9) begin
                                        uart_txd <= 'b1;
                                end else if (tx_bitcount == 10) begin
                                        tx_bitcount <= 0;
                                        tx_busy  <= 0;
                                end else begin
                                        uart_txd <= txd_reg[0];
                                        txd_reg  <= { 1'b0, txd_reg[7:1] };
                                end
                        end
 
                end
        end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	hharte	`//-----------------------------------------------------`
2			`// Design Name : uart`
3			`// File Name : uart.v`
4			`//-----------------------------------------------------`
5			`module uart #(`
6			`parameter freq_hz = 100000000,`
7			`parameter baud = 115200`
8			`) (`
9			`input reset,`
10			`input clk,`
11			`// UART lines`
12			`input uart_rxd,`
13			`output reg uart_txd,`
14			`//`
15			`output reg [7:0] rx_data,`
16			`output reg rx_avail,`
17			`output reg rx_error,`
18			`input rx_ack,`
19			`input [7:0] tx_data,`
20			`input tx_wr,`
21			`output reg tx_busy`
22			`);`
23
24			`parameter divisor = freq_hz/baud/16;`
25
26			`//-----------------------------------------------------------------`
27			`// enable16 generator`
28			`//-----------------------------------------------------------------`
29			`reg [15:0] enable16_counter;`
30
31			`wire enable16;`
32			`assign enable16 = (enable16_counter == 0);`
33
34			`always @(posedge clk)`
35			`begin`
36			`if (reset) begin`
37			`enable16_counter <= divisor-1;`
38			`end else begin`
39			`enable16_counter <= enable16_counter - 1;`
40			`if (enable16_counter == 0) begin`
41			`enable16_counter <= divisor-1;`
42			`end`
43			`end`
44			`end`
45
46			`//-----------------------------------------------------------------`
47			`// syncronize uart_rxd`
48			`//-----------------------------------------------------------------`
49			`reg uart_rxd1;`
50			`reg uart_rxd2;`
51
52			`always @(posedge clk)`
53			`begin`
54			`uart_rxd1 <= uart_rxd;`
55			`uart_rxd2 <= uart_rxd1;`
56			`end`
57
58			`//-----------------------------------------------------------------`
59			`// UART RX Logic`
60			`//-----------------------------------------------------------------`
61			`reg rx_busy;`
62			`reg [3:0] rx_count16;`
63			`reg [3:0] rx_bitcount;`
64			`reg [7:0] rxd_reg;`
65
66			`always @ (posedge clk)`
67			`begin`
68			`if (reset) begin`
69			`rx_busy <= 0;`
70			`rx_count16 <= 0;`
71			`rx_bitcount <= 0;`
72			`rx_avail <= 0;`
73			`rx_error <= 0;`
74			`end else begin`
75			`if (rx_ack) begin`
76			`rx_avail <= 0;`
77			`rx_error <= 0;`
78			`end`
79
80			`if (enable16) begin`
81			`if (!rx_busy) begin // look for start bit`
82			`if (!uart_rxd2) begin // start bit found`
83			`rx_busy <= 1;`
84			`rx_count16 <= 7;`
85			`rx_bitcount <= 0;`
86			`end`
87			`end else begin`
88			`rx_count16 <= rx_count16 + 1;`
89
90			`if (rx_count16 == 0) begin // sample`
91			`rx_bitcount <= rx_bitcount + 1;`
92
93			`if (rx_bitcount == 0) begin // verify startbit`
94			`if (uart_rxd2) begin`
95			`rx_busy <= 0;`
96			`end`
97			`end else if (rx_bitcount == 9) begin // look for stop bit`
98			`rx_busy <= 0;`
99			`if (uart_rxd2) begin // stop bit ok`
100			`rx_data <= rxd_reg;`
101			`rx_avail <= 1;`
102			`rx_error <= 0;`
103			`end else begin // bas stop bit`
104			`rx_error <= 1;`
105			`end`
106			`end else begin`
107			`rxd_reg <= { uart_rxd2, rxd_reg[7:1] };`
108			`end`
109			`end`
110			`end`
111			`end`
112			`end`
113			`end`
114
115			`//-----------------------------------------------------------------`
116			`// UART TX Logic`
117			`//-----------------------------------------------------------------`
118			`reg [3:0] tx_bitcount;`
119			`reg [3:0] tx_count16;`
120			`reg [7:0] txd_reg;`
121
122			`always @ (posedge clk)`
123			`begin`
124			`if (reset) begin`
125			`tx_busy <= 0;`
126			`uart_txd <= 1;`
127	22	hharte	`tx_count16 <= 0;`
128	3	hharte	`end else begin`
129			`if (tx_wr && !tx_busy) begin`
130			`txd_reg <= tx_data;`
131			`tx_bitcount <= 0;`
132	22	hharte	`tx_count16 <= 0;`
133	3	hharte	`tx_busy <= 1;`
134	22	hharte	`end`
135
136			`if (enable16) begin`
137	3	hharte	`tx_count16 <= tx_count16 + 1;`
138
139	22	hharte	`if ((tx_count16 == 0) && tx_busy) begin`
140	3	hharte	`tx_bitcount <= tx_bitcount + 1;`
141
142	22	hharte	`if (tx_bitcount == 0) begin`
143			`uart_txd <= 'b0;`
144			`end else if (tx_bitcount == 9) begin`
145	3	hharte	`uart_txd <= 'b1;`
146	22	hharte	`end else if (tx_bitcount == 10) begin`
147			`tx_bitcount <= 0;`
148	3	hharte	`tx_busy <= 0;`
149			`end else begin`
150			`uart_txd <= txd_reg[0];`
151			`txd_reg <= { 1'b0, txd_reg[7:1] };`
152			`end`
153			`end`
154	22	hharte
155	3	hharte	`end`
156			`end`
157			`end`
158
159
160			`endmodule`

Browse

Tools

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [uart.v] - Blame information for rev 35