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URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [vg_z80_sbc.defines] - Blame information for rev 10

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Line No. Rev Author Line
1 3 hharte 
# Generated by PERL program wishbone.pl.
2 
# File used as input for wishbone arbiter generation
3 10 hharte 
# Generated Sun Dec  7 17:41:47 2008
4 3 hharte 
 
5 
filename=wb
6 
intercon=intercon
7 
syscon=syscon
8 
target=generic
9 
hdl=vhdl
10 
signal_groups=0
11 
tga_bits=2
12 
tgc_bits=3
13 
tgd_bits=0
14 
rename_tga=bte
15 
rename_tgc=cti
16 
rename_tgd=tgd
17 
classic=000
18 
endofburst=111
19 
dat_size=32
20 
adr_size=24
21 
mux_type=andor
22 
interconnect=crossbarswitch
23 
 
24 
master wb32_pci_master
25 
  type=rw
26 
  lock_o=0
27 
  tga_o=0
28 
  tgc_o=0
29 
  tgd_o=0
30 
  err_i=1
31 
  rty_i=0
32 
  priority_wb_cpu_ctrl=1
33 
  priority_wb_sram=2
34 
  priority_wbs_flash=3
35 
  priority_wbs_ddr=4
36 
  priority_wbs_mmu=5
37 
  priority_wbs_vga=6
38 
  priority_wb_uart0=7
39 
  priority_wb_uart1=8
40 10 hharte 
  priority_wbs_vhdfd=9
41 
  priority_wbs_spimaster=10
42 
  priority_wbs_fpb=11
43 3 hharte 
end master wb32_pci_master
44 
 
45 
master wbm_z80
46 
  type=rw
47 
  lock_o=0
48 
  tga_o=0
49 
  tgc_o=0
50 
  tgd_o=0
51 
  err_i=0
52 
  rty_i=0
53 
  priority_wb_cpu_ctrl=1
54 
  priority_wb_sram=2
55 
  priority_wbs_flash=3
56 
  priority_wbs_ddr=4
57 
  priority_wbs_mmu=5
58 
  priority_wbs_vga=6
59 
  priority_wb_uart0=7
60 
  priority_wb_uart1=8
61 10 hharte 
  priority_wbs_vhdfd=9
62 
  priority_wbs_spimaster=10
63 
  priority_wbs_fpb=11
64 3 hharte 
end master wbm_z80
65 
 
66 
slave wb_cpu_ctrl
67 
  type=rw
68 10 hharte 
  adr_i_hi=2
69 
  adr_i_lo=0
70 3 hharte 
  tga_i=0
71 
  tgc_i=0
72 
  tgd_i=0
73 
  lock_i=0
74 
  err_o=0
75 
  rty_o=0
76 10 hharte 
  baseadr=0x40
77 
  size=0x20
78 3 hharte 
  baseadr1=0x00000000
79 
  size1=0xffffffff
80 
  baseadr2=0x00000000
81 
  size2=0xffffffff
82 
end slave wb_cpu_ctrl
83 
 
84 
slave wb_sram
85 
  type=rw
86 
  adr_i_hi=14
87 
  adr_i_lo=0
88 
  tga_i=0
89 
  tgc_i=0
90 
  tgd_i=0
91 
  lock_i=0
92 
  err_o=0
93 
  rty_o=0
94 
  baseadr=0x100000
95 
  size=0x100000
96 
  baseadr1=0x00000000
97 
  size1=0xffffffff
98 
  baseadr2=0x00000000
99 
  size2=0xffffffff
100 
end slave wb_sram
101 
 
102 
slave wbs_flash
103 
  type=rw
104 
  adr_i_hi=18
105 
  adr_i_lo=0
106 
  tga_i=0
107 
  tgc_i=0
108 
  tgd_i=0
109 
  lock_i=0
110 
  err_o=0
111 
  rty_o=0
112 
  baseadr=0x200000
113 
  size=0x100000
114 
  baseadr1=0x00000000
115 
  size1=0xffffffff
116 
  baseadr2=0x00000000
117 
  size2=0xffffffff
118 
end slave wbs_flash
119 
 
120 
slave wbs_ddr
121 
  type=rw
122 
  adr_i_hi=19
123 
  adr_i_lo=0
124 
  tga_i=0
125 
  tgc_i=0
126 
  tgd_i=0
127 
  lock_i=0
128 
  err_o=0
129 
  rty_o=0
130 
  baseadr=0x800000
131 
  size=0x100000
132 
  baseadr1=0x00000000
133 
  size1=0xffffffff
134 
  baseadr2=0x00000000
135 
  size2=0xffffffff
136 
end slave wbs_ddr
137 
 
138 
slave wbs_mmu
139 
  type=rw
140 10 hharte 
  adr_i_hi=1
141 3 hharte 
  adr_i_lo=0
142 
  tga_i=0
143 
  tgc_i=0
144 
  tgd_i=0
145 
  lock_i=0
146 
  err_o=0
147 
  rty_o=0
148 10 hharte 
  baseadr=0x60
149 
  size=0x20
150 3 hharte 
  baseadr1=0x00000000
151 
  size1=0xffffffff
152 
  baseadr2=0x00000000
153 
  size2=0xffffffff
154 
end slave wbs_mmu
155 
 
156 
slave wbs_vga
157 
  type=rw
158 
  adr_i_hi=13
159 
  adr_i_lo=0
160 
  tga_i=0
161 
  tgc_i=0
162 
  tgd_i=0
163 
  lock_i=0
164 
  err_o=0
165 
  rty_o=0
166 
  baseadr=0x600000
167 
  size=0x100000
168 
  baseadr1=0x00000000
169 
  size1=0xffffffff
170 
  baseadr2=0x00000000
171 
  size2=0xffffffff
172 
end slave wbs_vga
173 
 
174 
slave wb_uart0
175 
  type=rw
176 10 hharte 
  adr_i_hi=2
177 
  adr_i_lo=0
178 3 hharte 
  tga_i=0
179 
  tgc_i=0
180 
  tgd_i=0
181 
  lock_i=0
182 
  err_o=0
183 
  rty_o=0
184 10 hharte 
  baseadr=0x20
185 3 hharte 
  size=0x20
186 
  baseadr1=0x00000000
187 
  size1=0xffffffff
188 
  baseadr2=0x00000000
189 
  size2=0xffffffff
190 
end slave wb_uart0
191 
 
192 
slave wb_uart1
193 
  type=rw
194 
  adr_i_hi=4
195 
  adr_i_lo=0
196 
  tga_i=0
197 
  tgc_i=0
198 
  tgd_i=0
199 
  lock_i=0
200 
  err_o=0
201 
  rty_o=0
202 
  baseadr=0x00
203 
  size=0x20
204 
  baseadr1=0x00000000
205 
  size1=0xffffffff
206 
  baseadr2=0x00000000
207 
  size2=0xffffffff
208 
end slave wb_uart1
209 10 hharte 
 
210 
slave wbs_vhdfd
211 
  type=rw
212 
  adr_i_hi=2
213 
  adr_i_lo=0
214 
  tga_i=0
215 
  tgc_i=0
216 
  tgd_i=0
217 
  lock_i=0
218 
  err_o=0
219 
  rty_o=0
220 
  baseadr=0xc0
221 
  size=0x20
222 
  baseadr1=0x00000000
223 
  size1=0xffffffff
224 
  baseadr2=0x00000000
225 
  size2=0xffffffff
226 
end slave wbs_vhdfd
227 
 
228 
slave wbs_spimaster
229 
  type=rw
230 
  adr_i_hi=5
231 
  adr_i_lo=0
232 
  tga_i=0
233 
  tgc_i=0
234 
  tgd_i=0
235 
  lock_i=0
236 
  err_o=0
237 
  rty_o=0
238 
  baseadr=0x80
239 
  size=0x40
240 
  baseadr1=0x00000000
241 
  size1=0xffffffff
242 
  baseadr2=0x00000000
243 
  size2=0xffffffff
244 
end slave wbs_spimaster
245 
 
246 
slave wbs_fpb
247 
  type=rw
248 
  adr_i_hi=4
249 
  adr_i_lo=0
250 
  tga_i=0
251 
  tgc_i=0
252 
  tgd_i=0
253 
  lock_i=0
254 
  err_o=0
255 
  rty_o=0
256 
  baseadr=0xe0
257 
  size=0x20
258 
  baseadr1=0x00000000
259 
  size1=0xffffffff
260 
  baseadr2=0x00000000
261 
  size2=0xffffffff
262 
end slave wbs_fpb

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