URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [vg_z80_sbc.defines] - Blame information for rev 3

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# Generated by PERL program wishbone.pl.
# File used as input for wishbone arbiter generation
# Generated Wed Nov 26 14:33:45 2008
 
filename=wb
intercon=intercon
syscon=syscon
target=generic
hdl=vhdl
signal_groups=0
tga_bits=2
tgc_bits=3
tgd_bits=0
rename_tga=bte
rename_tgc=cti
rename_tgd=tgd
classic=000
endofburst=111
dat_size=32
adr_size=24
mux_type=andor
interconnect=crossbarswitch
 
master wb32_pci_master
  type=rw
  lock_o=0
  tga_o=0
  tgc_o=0
  tgd_o=0
  err_i=1
  rty_i=0
  priority_wb_cpu_ctrl=1
  priority_wb_sram=2
  priority_wbs_flash=3
  priority_wbs_ddr=4
  priority_wbs_mmu=5
  priority_wbs_vga=6
  priority_wb_uart0=7
  priority_wb_uart1=8
end master wb32_pci_master
 
master wbm_z80
  type=rw
  lock_o=0
  tga_o=0
  tgc_o=0
  tgd_o=0
  err_i=0
  rty_i=0
  priority_wb_cpu_ctrl=1
  priority_wb_sram=2
  priority_wbs_flash=3
  priority_wbs_ddr=4
  priority_wbs_mmu=5
  priority_wbs_vga=6
  priority_wb_uart0=7
  priority_wb_uart1=8
end master wbm_z80
 
slave wb_cpu_ctrl
  type=rw
  adr_i_hi=7
  adr_i_lo=2
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x200
  size=0x100
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_cpu_ctrl
 
slave wb_sram
  type=rw
  adr_i_hi=14
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x100000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_sram
 
slave wbs_flash
  type=rw
  adr_i_hi=18
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x200000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_flash
 
slave wbs_ddr
  type=rw
  adr_i_hi=19
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x800000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_ddr
 
slave wbs_mmu
  type=rw
  adr_i_hi=9
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0xF00000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_mmu
 
slave wbs_vga
  type=rw
  adr_i_hi=13
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x600000
  size=0x100000
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wbs_vga
 
slave wb_uart0
  type=rw
  adr_i_hi=4
  adr_i_lo=2
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0xE0
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_uart0
 
slave wb_uart1
  type=rw
  adr_i_hi=4
  adr_i_lo=0
  tga_i=0
  tgc_i=0
  tgd_i=0
  lock_i=0
  err_o=0
  rty_o=0
  baseadr=0x00
  size=0x20
  baseadr1=0x00000000
  size1=0xffffffff
  baseadr2=0x00000000
  size2=0xffffffff
end slave wb_uart1

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Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [vg_z80_sbc.defines] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	hharte	`# Generated by PERL program wishbone.pl.`
2			`# File used as input for wishbone arbiter generation`
3			`# Generated Wed Nov 26 14:33:45 2008`
4
5			`filename=wb`
6			`intercon=intercon`
7			`syscon=syscon`
8			`target=generic`
9			`hdl=vhdl`
10			`signal_groups=0`
11			`tga_bits=2`
12			`tgc_bits=3`
13			`tgd_bits=0`
14			`rename_tga=bte`
15			`rename_tgc=cti`
16			`rename_tgd=tgd`
17			`classic=000`
18			`endofburst=111`
19			`dat_size=32`
20			`adr_size=24`
21			`mux_type=andor`
22			`interconnect=crossbarswitch`
23
24			`master wb32_pci_master`
25			`type=rw`
26			`lock_o=0`
27			`tga_o=0`
28			`tgc_o=0`
29			`tgd_o=0`
30			`err_i=1`
31			`rty_i=0`
32			`priority_wb_cpu_ctrl=1`
33			`priority_wb_sram=2`
34			`priority_wbs_flash=3`
35			`priority_wbs_ddr=4`
36			`priority_wbs_mmu=5`
37			`priority_wbs_vga=6`
38			`priority_wb_uart0=7`
39			`priority_wb_uart1=8`
40			`end master wb32_pci_master`
41
42			`master wbm_z80`
43			`type=rw`
44			`lock_o=0`
45			`tga_o=0`
46			`tgc_o=0`
47			`tgd_o=0`
48			`err_i=0`
49			`rty_i=0`
50			`priority_wb_cpu_ctrl=1`
51			`priority_wb_sram=2`
52			`priority_wbs_flash=3`
53			`priority_wbs_ddr=4`
54			`priority_wbs_mmu=5`
55			`priority_wbs_vga=6`
56			`priority_wb_uart0=7`
57			`priority_wb_uart1=8`
58			`end master wbm_z80`
59
60			`slave wb_cpu_ctrl`
61			`type=rw`
62			`adr_i_hi=7`
63			`adr_i_lo=2`
64			`tga_i=0`
65			`tgc_i=0`
66			`tgd_i=0`
67			`lock_i=0`
68			`err_o=0`
69			`rty_o=0`
70			`baseadr=0x200`
71			`size=0x100`
72			`baseadr1=0x00000000`
73			`size1=0xffffffff`
74			`baseadr2=0x00000000`
75			`size2=0xffffffff`
76			`end slave wb_cpu_ctrl`
77
78			`slave wb_sram`
79			`type=rw`
80			`adr_i_hi=14`
81			`adr_i_lo=0`
82			`tga_i=0`
83			`tgc_i=0`
84			`tgd_i=0`
85			`lock_i=0`
86			`err_o=0`
87			`rty_o=0`
88			`baseadr=0x100000`
89			`size=0x100000`
90			`baseadr1=0x00000000`
91			`size1=0xffffffff`
92			`baseadr2=0x00000000`
93			`size2=0xffffffff`
94			`end slave wb_sram`
95
96			`slave wbs_flash`
97			`type=rw`
98			`adr_i_hi=18`
99			`adr_i_lo=0`
100			`tga_i=0`
101			`tgc_i=0`
102			`tgd_i=0`
103			`lock_i=0`
104			`err_o=0`
105			`rty_o=0`
106			`baseadr=0x200000`
107			`size=0x100000`
108			`baseadr1=0x00000000`
109			`size1=0xffffffff`
110			`baseadr2=0x00000000`
111			`size2=0xffffffff`
112			`end slave wbs_flash`
113
114			`slave wbs_ddr`
115			`type=rw`
116			`adr_i_hi=19`
117			`adr_i_lo=0`
118			`tga_i=0`
119			`tgc_i=0`
120			`tgd_i=0`
121			`lock_i=0`
122			`err_o=0`
123			`rty_o=0`
124			`baseadr=0x800000`
125			`size=0x100000`
126			`baseadr1=0x00000000`
127			`size1=0xffffffff`
128			`baseadr2=0x00000000`
129			`size2=0xffffffff`
130			`end slave wbs_ddr`
131
132			`slave wbs_mmu`
133			`type=rw`
134			`adr_i_hi=9`
135			`adr_i_lo=0`
136			`tga_i=0`
137			`tgc_i=0`
138			`tgd_i=0`
139			`lock_i=0`
140			`err_o=0`
141			`rty_o=0`
142			`baseadr=0xF00000`
143			`size=0x100000`
144			`baseadr1=0x00000000`
145			`size1=0xffffffff`
146			`baseadr2=0x00000000`
147			`size2=0xffffffff`
148			`end slave wbs_mmu`
149
150			`slave wbs_vga`
151			`type=rw`
152			`adr_i_hi=13`
153			`adr_i_lo=0`
154			`tga_i=0`
155			`tgc_i=0`
156			`tgd_i=0`
157			`lock_i=0`
158			`err_o=0`
159			`rty_o=0`
160			`baseadr=0x600000`
161			`size=0x100000`
162			`baseadr1=0x00000000`
163			`size1=0xffffffff`
164			`baseadr2=0x00000000`
165			`size2=0xffffffff`
166			`end slave wbs_vga`
167
168			`slave wb_uart0`
169			`type=rw`
170			`adr_i_hi=4`
171			`adr_i_lo=2`
172			`tga_i=0`
173			`tgc_i=0`
174			`tgd_i=0`
175			`lock_i=0`
176			`err_o=0`
177			`rty_o=0`
178			`baseadr=0xE0`
179			`size=0x20`
180			`baseadr1=0x00000000`
181			`size1=0xffffffff`
182			`baseadr2=0x00000000`
183			`size2=0xffffffff`
184			`end slave wb_uart0`
185
186			`slave wb_uart1`
187			`type=rw`
188			`adr_i_hi=4`
189			`adr_i_lo=0`
190			`tga_i=0`
191			`tgc_i=0`
192			`tgd_i=0`
193			`lock_i=0`
194			`err_o=0`
195			`rty_o=0`
196			`baseadr=0x00`
197			`size=0x20`
198			`baseadr1=0x00000000`
199			`size1=0xffffffff`
200			`baseadr2=0x00000000`
201			`size2=0xffffffff`
202			`end slave wb_uart1`