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URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] [vg_z80_sbc.defines] - Blame information for rev 30

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Line No. Rev Author Line
1 3 hharte 
# Generated by PERL program wishbone.pl.
2 
# File used as input for wishbone arbiter generation
3 30 hharte 
# Generated Mon Dec  8 20:57:48 2008
4 3 hharte 
 
5 
filename=wb
6 
intercon=intercon
7 
syscon=syscon
8 
target=generic
9 
hdl=vhdl
10 
signal_groups=0
11 
tga_bits=2
12 
tgc_bits=3
13 
tgd_bits=0
14 
rename_tga=bte
15 
rename_tgc=cti
16 
rename_tgd=tgd
17 
classic=000
18 
endofburst=111
19 
dat_size=32
20 
adr_size=24
21 
mux_type=andor
22 
interconnect=crossbarswitch
23 
 
24 
master wb32_pci_master
25 
  type=rw
26 
  lock_o=0
27 
  tga_o=0
28 
  tgc_o=0
29 
  tgd_o=0
30 
  err_i=1
31 
  rty_i=0
32 30 hharte 
  priority_wbs_sram=1
33 
  priority_wbs_flash=2
34 
  priority_wbs_ddr=3
35 
  priority_wbs_vga=4
36 
  priority_wbs_kbd=5
37 
  priority_wbs_mmu=6
38 
  priority_wb_cpu_ctrl=7
39 
  priority_wbs_spimaster=8
40 10 hharte 
  priority_wbs_vhdfd=9
41 30 hharte 
  priority_wbs_fpb=10
42 3 hharte 
end master wb32_pci_master
43 
 
44 
master wbm_z80
45 
  type=rw
46 
  lock_o=0
47 
  tga_o=0
48 
  tgc_o=0
49 
  tgd_o=0
50 
  err_i=0
51 
  rty_i=0
52 30 hharte 
  priority_wbs_sram=1
53 
  priority_wbs_flash=2
54 
  priority_wbs_ddr=3
55 
  priority_wbs_vga=4
56 
  priority_wbs_kbd=5
57 
  priority_wbs_mmu=6
58 
  priority_wb_cpu_ctrl=7
59 
  priority_wbs_spimaster=8
60 10 hharte 
  priority_wbs_vhdfd=9
61 30 hharte 
  priority_wbs_fpb=10
62 3 hharte 
end master wbm_z80
63 
 
64 30 hharte 
slave wbs_sram
65 3 hharte 
  type=rw
66 
  adr_i_hi=14
67 
  adr_i_lo=0
68 
  tga_i=0
69 
  tgc_i=0
70 
  tgd_i=0
71 
  lock_i=0
72 
  err_o=0
73 
  rty_o=0
74 
  baseadr=0x100000
75 
  size=0x100000
76 
  baseadr1=0x00000000
77 
  size1=0xffffffff
78 
  baseadr2=0x00000000
79 
  size2=0xffffffff
80 30 hharte 
end slave wbs_sram
81 3 hharte 
 
82 
slave wbs_flash
83 
  type=rw
84 
  adr_i_hi=18
85 
  adr_i_lo=0
86 
  tga_i=0
87 
  tgc_i=0
88 
  tgd_i=0
89 
  lock_i=0
90 
  err_o=0
91 
  rty_o=0
92 
  baseadr=0x200000
93 
  size=0x100000
94 
  baseadr1=0x00000000
95 
  size1=0xffffffff
96 
  baseadr2=0x00000000
97 
  size2=0xffffffff
98 
end slave wbs_flash
99 
 
100 
slave wbs_ddr
101 
  type=rw
102 
  adr_i_hi=19
103 
  adr_i_lo=0
104 
  tga_i=0
105 
  tgc_i=0
106 
  tgd_i=0
107 
  lock_i=0
108 
  err_o=0
109 
  rty_o=0
110 
  baseadr=0x800000
111 
  size=0x100000
112 
  baseadr1=0x00000000
113 
  size1=0xffffffff
114 
  baseadr2=0x00000000
115 
  size2=0xffffffff
116 
end slave wbs_ddr
117 
 
118 30 hharte 
slave wbs_vga
119 3 hharte 
  type=rw
120 30 hharte 
  adr_i_hi=13
121 3 hharte 
  adr_i_lo=0
122 
  tga_i=0
123 
  tgc_i=0
124 
  tgd_i=0
125 
  lock_i=0
126 
  err_o=0
127 
  rty_o=0
128 30 hharte 
  baseadr=0x600000
129 
  size=0x100000
130 3 hharte 
  baseadr1=0x00000000
131 
  size1=0xffffffff
132 
  baseadr2=0x00000000
133 
  size2=0xffffffff
134 30 hharte 
end slave wbs_vga
135 3 hharte 
 
136 30 hharte 
slave wbs_kbd
137 3 hharte 
  type=rw
138 30 hharte 
  adr_i_hi=2
139 3 hharte 
  adr_i_lo=0
140 
  tga_i=0
141 
  tgc_i=0
142 
  tgd_i=0
143 
  lock_i=0
144 
  err_o=0
145 
  rty_o=0
146 30 hharte 
  baseadr=0x00
147 
  size=0x20
148 3 hharte 
  baseadr1=0x00000000
149 
  size1=0xffffffff
150 
  baseadr2=0x00000000
151 
  size2=0xffffffff
152 30 hharte 
end slave wbs_kbd
153 3 hharte 
 
154 30 hharte 
slave wbs_mmu
155 3 hharte 
  type=rw
156 30 hharte 
  adr_i_hi=1
157 10 hharte 
  adr_i_lo=0
158 3 hharte 
  tga_i=0
159 
  tgc_i=0
160 
  tgd_i=0
161 
  lock_i=0
162 
  err_o=0
163 
  rty_o=0
164 10 hharte 
  baseadr=0x20
165 3 hharte 
  size=0x20
166 
  baseadr1=0x00000000
167 
  size1=0xffffffff
168 
  baseadr2=0x00000000
169 
  size2=0xffffffff
170 30 hharte 
end slave wbs_mmu
171 3 hharte 
 
172 30 hharte 
slave wb_cpu_ctrl
173 3 hharte 
  type=rw
174 30 hharte 
  adr_i_hi=2
175 3 hharte 
  adr_i_lo=0
176 
  tga_i=0
177 
  tgc_i=0
178 
  tgd_i=0
179 
  lock_i=0
180 
  err_o=0
181 
  rty_o=0
182 30 hharte 
  baseadr=0x40
183 
  size=0x40
184 3 hharte 
  baseadr1=0x00000000
185 
  size1=0xffffffff
186 
  baseadr2=0x00000000
187 
  size2=0xffffffff
188 30 hharte 
end slave wb_cpu_ctrl
189 10 hharte 
 
190 30 hharte 
slave wbs_spimaster
191 10 hharte 
  type=rw
192 30 hharte 
  adr_i_hi=5
193 10 hharte 
  adr_i_lo=0
194 
  tga_i=0
195 
  tgc_i=0
196 
  tgd_i=0
197 
  lock_i=0
198 
  err_o=0
199 
  rty_o=0
200 30 hharte 
  baseadr=0x80
201 
  size=0x40
202 10 hharte 
  baseadr1=0x00000000
203 
  size1=0xffffffff
204 
  baseadr2=0x00000000
205 
  size2=0xffffffff
206 30 hharte 
end slave wbs_spimaster
207 10 hharte 
 
208 30 hharte 
slave wbs_vhdfd
209 10 hharte 
  type=rw
210 30 hharte 
  adr_i_hi=2
211 10 hharte 
  adr_i_lo=0
212 
  tga_i=0
213 
  tgc_i=0
214 
  tgd_i=0
215 
  lock_i=0
216 
  err_o=0
217 
  rty_o=0
218 30 hharte 
  baseadr=0xc0
219 
  size=0x20
220 10 hharte 
  baseadr1=0x00000000
221 
  size1=0xffffffff
222 
  baseadr2=0x00000000
223 
  size2=0xffffffff
224 30 hharte 
end slave wbs_vhdfd
225 10 hharte 
 
226 
slave wbs_fpb
227 
  type=rw
228 
  adr_i_hi=4
229 
  adr_i_lo=0
230 
  tga_i=0
231 
  tgc_i=0
232 
  tgd_i=0
233 
  lock_i=0
234 
  err_o=0
235 
  rty_o=0
236 
  baseadr=0xe0
237 
  size=0x20
238 
  baseadr1=0x00000000
239 
  size1=0xffffffff
240 
  baseadr2=0x00000000
241 
  size2=0xffffffff
242 
end slave wbs_fpb

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