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[/] [vg_z80_sbc/] [trunk/] [rtl/] [wb.vhd] - Blame information for rev 37

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Line No. Rev Author Line
1 3 hharte 
-- Generated by PERL program wishbone.pl. Do not edit this file.
2 
--
3 13 hharte 
-- For defines see vg_z80_sbc.defines
4 3 hharte 
--
5 30 hharte 
-- Generated Mon Dec  8 20:57:48 2008
6 3 hharte 
--
7 
-- Wishbone masters:
8 
--   wb32_pci_master
9 
--   wbm_z80
10 
--
11 
-- Wishbone slaves:
12 30 hharte 
--   wbs_sram
13 3 hharte 
--     baseadr 0x100000 - size 0x100000
14 
--   wbs_flash
15 
--     baseadr 0x200000 - size 0x100000
16 
--   wbs_ddr
17 
--     baseadr 0x800000 - size 0x100000
18 
--   wbs_vga
19 
--     baseadr 0x600000 - size 0x100000
20 30 hharte 
--   wbs_kbd
21 
--     baseadr 0x00 - size 0x20
22 
--   wbs_mmu
23 13 hharte 
--     baseadr 0x20 - size 0x20
24 30 hharte 
--   wb_cpu_ctrl
25 
--     baseadr 0x40 - size 0x40
26 
--   wbs_spimaster
27 
--     baseadr 0x80 - size 0x40
28 13 hharte 
--   wbs_vhdfd
29 
--     baseadr 0xc0 - size 0x20
30 
--   wbs_fpb
31 
--     baseadr 0xe0 - size 0x20
32 3 hharte 
-----------------------------------------------------------------------------------------
33 
library IEEE;
34 
use IEEE.std_logic_1164.all;
35 
 
36 
package intercon_package is
37 
 
38 
 
39 
function "and" (
40 
  l : std_logic_vector;
41 
  r : std_logic)
42 
return std_logic_vector;
43 
end intercon_package;
44 
package body intercon_package is
45 
 
46 
function "and" (
47 
  l : std_logic_vector;
48 
  r : std_logic)
49 
return std_logic_vector is
50 
  variable result : std_logic_vector(l'range);
51 
begin  -- "and"
52 
  for i in l'range loop
53 
  result(i) := l(i) and r;
54 
end loop;  -- i
55 
return result;
56 
end "and";
57 
end intercon_package;
58 
library IEEE;
59 
use IEEE.std_logic_1164.all;
60 
 
61 
entity trafic_supervision is
62 
 
63 
  generic (
64 
    priority     : integer := 1;
65 
    tot_priority : integer := 2);
66 
 
67 
  port (
68 
    bg           : in  std_logic;       -- bus grant
69 
    ce           : in  std_logic;       -- clock enable
70 
    trafic_limit : out std_logic;
71 
    clk          : in  std_logic;
72 
    reset        : in  std_logic);
73 
 
74 
end trafic_supervision;
75 
 
76 
architecture rtl of trafic_supervision is
77 
 
78 
  signal shreg : std_logic_vector(tot_priority-1 downto 0);
79 
  signal cntr : integer range 0 to tot_priority;
80 
 
81 
begin  -- rtl
82 
 
83 
  -- purpose: holds information of usage of latest cycles
84 
  -- type   : sequential
85 
  -- inputs : clk, reset, ce, bg
86 
  -- outputs: shreg('left)
87 
  sh_reg: process (clk,reset)
88 
  begin  -- process shreg
89 
    if reset = '1' then                 -- asynchronous reset (active hi)
90 
      shreg <= (others=>'0');
91 
    elsif clk'event and clk = '1' then  -- rising clock edge
92 
      if ce='1' then
93 
        shreg <= shreg(tot_priority-2 downto 0) & bg;
94 
      end if;
95 
    end if;
96 
  end process sh_reg;
97 
 
98 
  -- purpose: keeps track of used cycles
99 
  -- type   : sequential
100 
  -- inputs : clk, reset, shreg('left), bg, ce
101 
  -- outputs: trafic_limit
102 
  counter: process (clk, reset)
103 
  begin  -- process counter
104 
    if reset = '1' then                 -- asynchronous reset (active hi)
105 
      cntr <= 0;
106 
      trafic_limit <= '0';
107 
    elsif clk'event and clk = '1' then  -- rising clock edge
108 
      if ce='1' then
109 
        if bg='1' and shreg(tot_priority-1)='0' then
110 
          cntr <= cntr + 1;
111 
          if cntr=priority-1 then
112 
            trafic_limit <= '1';
113 
          end if;
114 
        elsif bg='0' and shreg(tot_priority-1)='1' then
115 
          cntr <= cntr - 1;
116 
          if cntr=priority then
117 
            trafic_limit <= '0';
118 
          end if;
119 
        end if;
120 
      end if;
121 
    end if;
122 
  end process counter;
123 
 
124 
end rtl;
125 
 
126 
library IEEE;
127 
use IEEE.std_logic_1164.all;
128 
use work.intercon_package.all;
129 
 
130 
entity intercon is
131 
  port (
132 
  -- wishbone master port(s)
133 
  -- wb32_pci_master
134 
  wb32_pci_master_dat_i : out std_logic_vector(31 downto 0);
135 
  wb32_pci_master_ack_i : out std_logic;
136 
  wb32_pci_master_err_i : out std_logic;
137 
  wb32_pci_master_dat_o : in  std_logic_vector(31 downto 0);
138 
  wb32_pci_master_we_o  : in  std_logic;
139 
  wb32_pci_master_sel_o : in  std_logic_vector(3 downto 0);
140 
  wb32_pci_master_adr_o : in  std_logic_vector(23 downto 0);
141 
  wb32_pci_master_cyc_o : in  std_logic;
142 
  wb32_pci_master_stb_o : in  std_logic;
143 
  -- wbm_z80
144 
  wbm_z80_dat_i : out std_logic_vector(31 downto 0);
145 
  wbm_z80_ack_i : out std_logic;
146 
  wbm_z80_dat_o : in  std_logic_vector(31 downto 0);
147 
  wbm_z80_we_o  : in  std_logic;
148 
  wbm_z80_sel_o : in  std_logic_vector(3 downto 0);
149 
  wbm_z80_adr_o : in  std_logic_vector(23 downto 0);
150 
  wbm_z80_cyc_o : in  std_logic;
151 
  wbm_z80_stb_o : in  std_logic;
152 
  -- wishbone slave port(s)
153 30 hharte 
  -- wbs_sram
154 
  wbs_sram_dat_o : in  std_logic_vector(31 downto 0);
155 
  wbs_sram_ack_o : in  std_logic;
156 
  wbs_sram_dat_i : out std_logic_vector(31 downto 0);
157 
  wbs_sram_we_i  : out std_logic;
158 
  wbs_sram_sel_i : out std_logic_vector(3 downto 0);
159 
  wbs_sram_adr_i : out std_logic_vector(14 downto 0);
160 
  wbs_sram_cyc_i : out std_logic;
161 
  wbs_sram_stb_i : out std_logic;
162 3 hharte 
  -- wbs_flash
163 
  wbs_flash_dat_o : in  std_logic_vector(31 downto 0);
164 
  wbs_flash_ack_o : in  std_logic;
165 
  wbs_flash_dat_i : out std_logic_vector(31 downto 0);
166 
  wbs_flash_we_i  : out std_logic;
167 
  wbs_flash_sel_i : out std_logic_vector(3 downto 0);
168 
  wbs_flash_adr_i : out std_logic_vector(18 downto 0);
169 
  wbs_flash_cyc_i : out std_logic;
170 
  wbs_flash_stb_i : out std_logic;
171 
  -- wbs_ddr
172 
  wbs_ddr_dat_o : in  std_logic_vector(31 downto 0);
173 
  wbs_ddr_ack_o : in  std_logic;
174 
  wbs_ddr_dat_i : out std_logic_vector(31 downto 0);
175 
  wbs_ddr_we_i  : out std_logic;
176 
  wbs_ddr_sel_i : out std_logic_vector(3 downto 0);
177 
  wbs_ddr_adr_i : out std_logic_vector(19 downto 0);
178 
  wbs_ddr_cyc_i : out std_logic;
179 
  wbs_ddr_stb_i : out std_logic;
180 30 hharte 
  -- wbs_vga
181 
  wbs_vga_dat_o : in  std_logic_vector(31 downto 0);
182 
  wbs_vga_ack_o : in  std_logic;
183 
  wbs_vga_dat_i : out std_logic_vector(31 downto 0);
184 
  wbs_vga_we_i  : out std_logic;
185 
  wbs_vga_sel_i : out std_logic_vector(3 downto 0);
186 
  wbs_vga_adr_i : out std_logic_vector(13 downto 0);
187 
  wbs_vga_cyc_i : out std_logic;
188 
  wbs_vga_stb_i : out std_logic;
189 
  -- wbs_kbd
190 
  wbs_kbd_dat_o : in  std_logic_vector(31 downto 0);
191 
  wbs_kbd_ack_o : in  std_logic;
192 
  wbs_kbd_dat_i : out std_logic_vector(31 downto 0);
193 
  wbs_kbd_we_i  : out std_logic;
194 
  wbs_kbd_sel_i : out std_logic_vector(3 downto 0);
195 
  wbs_kbd_adr_i : out std_logic_vector(2 downto 0);
196 
  wbs_kbd_cyc_i : out std_logic;
197 
  wbs_kbd_stb_i : out std_logic;
198 3 hharte 
  -- wbs_mmu
199 
  wbs_mmu_dat_o : in  std_logic_vector(31 downto 0);
200 
  wbs_mmu_ack_o : in  std_logic;
201 
  wbs_mmu_dat_i : out std_logic_vector(31 downto 0);
202 
  wbs_mmu_we_i  : out std_logic;
203 
  wbs_mmu_sel_i : out std_logic_vector(3 downto 0);
204 13 hharte 
  wbs_mmu_adr_i : out std_logic_vector(1 downto 0);
205 3 hharte 
  wbs_mmu_cyc_i : out std_logic;
206 
  wbs_mmu_stb_i : out std_logic;
207 30 hharte 
  -- wb_cpu_ctrl
208 
  wb_cpu_ctrl_dat_o : in  std_logic_vector(31 downto 0);
209 
  wb_cpu_ctrl_ack_o : in  std_logic;
210 
  wb_cpu_ctrl_dat_i : out std_logic_vector(31 downto 0);
211 
  wb_cpu_ctrl_we_i  : out std_logic;
212 
  wb_cpu_ctrl_sel_i : out std_logic_vector(3 downto 0);
213 
  wb_cpu_ctrl_adr_i : out std_logic_vector(2 downto 0);
214 
  wb_cpu_ctrl_cyc_i : out std_logic;
215 
  wb_cpu_ctrl_stb_i : out std_logic;
216 
  -- wbs_spimaster
217 
  wbs_spimaster_dat_o : in  std_logic_vector(31 downto 0);
218 
  wbs_spimaster_ack_o : in  std_logic;
219 
  wbs_spimaster_dat_i : out std_logic_vector(31 downto 0);
220 
  wbs_spimaster_we_i  : out std_logic;
221 
  wbs_spimaster_sel_i : out std_logic_vector(3 downto 0);
222 
  wbs_spimaster_adr_i : out std_logic_vector(5 downto 0);
223 
  wbs_spimaster_cyc_i : out std_logic;
224 
  wbs_spimaster_stb_i : out std_logic;
225 13 hharte 
  -- wbs_vhdfd
226 
  wbs_vhdfd_dat_o : in  std_logic_vector(31 downto 0);
227 
  wbs_vhdfd_ack_o : in  std_logic;
228 
  wbs_vhdfd_dat_i : out std_logic_vector(31 downto 0);
229 
  wbs_vhdfd_we_i  : out std_logic;
230 
  wbs_vhdfd_sel_i : out std_logic_vector(3 downto 0);
231 
  wbs_vhdfd_adr_i : out std_logic_vector(2 downto 0);
232 
  wbs_vhdfd_cyc_i : out std_logic;
233 
  wbs_vhdfd_stb_i : out std_logic;
234 
  -- wbs_fpb
235 
  wbs_fpb_dat_o : in  std_logic_vector(31 downto 0);
236 
  wbs_fpb_ack_o : in  std_logic;
237 
  wbs_fpb_dat_i : out std_logic_vector(31 downto 0);
238 
  wbs_fpb_we_i  : out std_logic;
239 
  wbs_fpb_sel_i : out std_logic_vector(3 downto 0);
240 
  wbs_fpb_adr_i : out std_logic_vector(4 downto 0);
241 
  wbs_fpb_cyc_i : out std_logic;
242 
  wbs_fpb_stb_i : out std_logic;
243 3 hharte 
  -- clock and reset
244 
  clk   : in std_logic;
245 
  reset : in std_logic);
246 
end intercon;
247 
architecture rtl of intercon is
248 30 hharte 
  signal wb32_pci_master_wbs_sram_ss : std_logic; -- slave select
249 
  signal wb32_pci_master_wbs_sram_bg : std_logic; -- bus grant
250 3 hharte 
  signal wb32_pci_master_wbs_flash_ss : std_logic; -- slave select
251 
  signal wb32_pci_master_wbs_flash_bg : std_logic; -- bus grant
252 
  signal wb32_pci_master_wbs_ddr_ss : std_logic; -- slave select
253 
  signal wb32_pci_master_wbs_ddr_bg : std_logic; -- bus grant
254 30 hharte 
  signal wb32_pci_master_wbs_vga_ss : std_logic; -- slave select
255 
  signal wb32_pci_master_wbs_vga_bg : std_logic; -- bus grant
256 
  signal wb32_pci_master_wbs_kbd_ss : std_logic; -- slave select
257 
  signal wb32_pci_master_wbs_kbd_bg : std_logic; -- bus grant
258 3 hharte 
  signal wb32_pci_master_wbs_mmu_ss : std_logic; -- slave select
259 
  signal wb32_pci_master_wbs_mmu_bg : std_logic; -- bus grant
260 30 hharte 
  signal wb32_pci_master_wb_cpu_ctrl_ss : std_logic; -- slave select
261 
  signal wb32_pci_master_wb_cpu_ctrl_bg : std_logic; -- bus grant
262 
  signal wb32_pci_master_wbs_spimaster_ss : std_logic; -- slave select
263 
  signal wb32_pci_master_wbs_spimaster_bg : std_logic; -- bus grant
264 13 hharte 
  signal wb32_pci_master_wbs_vhdfd_ss : std_logic; -- slave select
265 
  signal wb32_pci_master_wbs_vhdfd_bg : std_logic; -- bus grant
266 
  signal wb32_pci_master_wbs_fpb_ss : std_logic; -- slave select
267 
  signal wb32_pci_master_wbs_fpb_bg : std_logic; -- bus grant
268 30 hharte 
  signal wbm_z80_wbs_sram_ss : std_logic; -- slave select
269 
  signal wbm_z80_wbs_sram_bg : std_logic; -- bus grant
270 3 hharte 
  signal wbm_z80_wbs_flash_ss : std_logic; -- slave select
271 
  signal wbm_z80_wbs_flash_bg : std_logic; -- bus grant
272 
  signal wbm_z80_wbs_ddr_ss : std_logic; -- slave select
273 
  signal wbm_z80_wbs_ddr_bg : std_logic; -- bus grant
274 30 hharte 
  signal wbm_z80_wbs_vga_ss : std_logic; -- slave select
275 
  signal wbm_z80_wbs_vga_bg : std_logic; -- bus grant
276 
  signal wbm_z80_wbs_kbd_ss : std_logic; -- slave select
277 
  signal wbm_z80_wbs_kbd_bg : std_logic; -- bus grant
278 3 hharte 
  signal wbm_z80_wbs_mmu_ss : std_logic; -- slave select
279 
  signal wbm_z80_wbs_mmu_bg : std_logic; -- bus grant
280 30 hharte 
  signal wbm_z80_wb_cpu_ctrl_ss : std_logic; -- slave select
281 
  signal wbm_z80_wb_cpu_ctrl_bg : std_logic; -- bus grant
282 
  signal wbm_z80_wbs_spimaster_ss : std_logic; -- slave select
283 
  signal wbm_z80_wbs_spimaster_bg : std_logic; -- bus grant
284 13 hharte 
  signal wbm_z80_wbs_vhdfd_ss : std_logic; -- slave select
285 
  signal wbm_z80_wbs_vhdfd_bg : std_logic; -- bus grant
286 
  signal wbm_z80_wbs_fpb_ss : std_logic; -- slave select
287 
  signal wbm_z80_wbs_fpb_bg : std_logic; -- bus grant
288 3 hharte 
begin  -- rtl
289 30 hharte 
arbiter_wbs_sram : block
290 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
291 
  signal wb32_pci_master_trafic_limit : std_logic;
292 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
293 
  signal wbm_z80_trafic_limit : std_logic;
294 
  signal ce, idle, ack : std_logic;
295 
begin
296 30 hharte 
ack <= wbs_sram_ack_o;
297 3 hharte 
 
298 
trafic_supervision_1 : entity work.trafic_supervision
299 
generic map(
300 
  priority => 1,
301 
  tot_priority => 2)
302 
port map(
303 30 hharte 
  bg => wb32_pci_master_wbs_sram_bg,
304 3 hharte 
  ce => ce,
305 
  trafic_limit => wb32_pci_master_trafic_limit,
306 
  clk => clk,
307 
  reset => reset);
308 
 
309 
trafic_supervision_2 : entity work.trafic_supervision
310 
generic map(
311 
  priority => 1,
312 
  tot_priority => 2)
313 
port map(
314 30 hharte 
  bg => wbm_z80_wbs_sram_bg,
315 3 hharte 
  ce => ce,
316 
  trafic_limit => wbm_z80_trafic_limit,
317 
  clk => clk,
318 
  reset => reset);
319 
 
320 
process(clk,reset)
321 
begin
322 
if reset='1' then
323 
  wb32_pci_master_bg_q <= '0';
324 
elsif clk'event and clk='1' then
325 
if wb32_pci_master_bg_q='0' then
326 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
327 
elsif ack='1' then
328 
  wb32_pci_master_bg_q <= '0';
329 
end if;
330 
end if;
331 
end process;
332 
 
333 
process(clk,reset)
334 
begin
335 
if reset='1' then
336 
  wbm_z80_bg_q <= '0';
337 
elsif clk'event and clk='1' then
338 
if wbm_z80_bg_q='0' then
339 
  wbm_z80_bg_q <= wbm_z80_bg;
340 
elsif ack='1' then
341 
  wbm_z80_bg_q <= '0';
342 
end if;
343 
end if;
344 
end process;
345 
 
346 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
347 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_sram_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
348 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_sram_ss='1' and wbm_z80_trafic_limit='0' else '0';
349 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_sram_ss='1' else '0';
350 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_sram_ss='1' else '0';
351 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
352 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
353 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_sram_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_sram_ss) when idle='1' else '0';
354 
wb32_pci_master_wbs_sram_bg <= wb32_pci_master_bg;
355 
wbm_z80_wbs_sram_bg <= wbm_z80_bg;
356 
end block arbiter_wbs_sram;
357 
arbiter_wbs_flash : block
358 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
359 
  signal wb32_pci_master_trafic_limit : std_logic;
360 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
361 
  signal wbm_z80_trafic_limit : std_logic;
362 
  signal ce, idle, ack : std_logic;
363 
begin
364 30 hharte 
ack <= wbs_flash_ack_o;
365 3 hharte 
 
366 
trafic_supervision_1 : entity work.trafic_supervision
367 
generic map(
368 
  priority => 2,
369 
  tot_priority => 4)
370 
port map(
371 30 hharte 
  bg => wb32_pci_master_wbs_flash_bg,
372 3 hharte 
  ce => ce,
373 
  trafic_limit => wb32_pci_master_trafic_limit,
374 
  clk => clk,
375 
  reset => reset);
376 
 
377 
trafic_supervision_2 : entity work.trafic_supervision
378 
generic map(
379 
  priority => 2,
380 
  tot_priority => 4)
381 
port map(
382 30 hharte 
  bg => wbm_z80_wbs_flash_bg,
383 3 hharte 
  ce => ce,
384 
  trafic_limit => wbm_z80_trafic_limit,
385 
  clk => clk,
386 
  reset => reset);
387 
 
388 
process(clk,reset)
389 
begin
390 
if reset='1' then
391 
  wb32_pci_master_bg_q <= '0';
392 
elsif clk'event and clk='1' then
393 
if wb32_pci_master_bg_q='0' then
394 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
395 
elsif ack='1' then
396 
  wb32_pci_master_bg_q <= '0';
397 
end if;
398 
end if;
399 
end process;
400 
 
401 
process(clk,reset)
402 
begin
403 
if reset='1' then
404 
  wbm_z80_bg_q <= '0';
405 
elsif clk'event and clk='1' then
406 
if wbm_z80_bg_q='0' then
407 
  wbm_z80_bg_q <= wbm_z80_bg;
408 
elsif ack='1' then
409 
  wbm_z80_bg_q <= '0';
410 
end if;
411 
end if;
412 
end process;
413 
 
414 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
415 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_flash_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
416 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_flash_ss='1' and wbm_z80_trafic_limit='0' else '0';
417 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_flash_ss='1' else '0';
418 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_flash_ss='1' else '0';
419 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
420 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
421 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_flash_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_flash_ss) when idle='1' else '0';
422 
wb32_pci_master_wbs_flash_bg <= wb32_pci_master_bg;
423 
wbm_z80_wbs_flash_bg <= wbm_z80_bg;
424 
end block arbiter_wbs_flash;
425 
arbiter_wbs_ddr : block
426 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
427 
  signal wb32_pci_master_trafic_limit : std_logic;
428 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
429 
  signal wbm_z80_trafic_limit : std_logic;
430 
  signal ce, idle, ack : std_logic;
431 
begin
432 30 hharte 
ack <= wbs_ddr_ack_o;
433 3 hharte 
 
434 
trafic_supervision_1 : entity work.trafic_supervision
435 
generic map(
436 
  priority => 3,
437 
  tot_priority => 6)
438 
port map(
439 30 hharte 
  bg => wb32_pci_master_wbs_ddr_bg,
440 3 hharte 
  ce => ce,
441 
  trafic_limit => wb32_pci_master_trafic_limit,
442 
  clk => clk,
443 
  reset => reset);
444 
 
445 
trafic_supervision_2 : entity work.trafic_supervision
446 
generic map(
447 
  priority => 3,
448 
  tot_priority => 6)
449 
port map(
450 30 hharte 
  bg => wbm_z80_wbs_ddr_bg,
451 3 hharte 
  ce => ce,
452 
  trafic_limit => wbm_z80_trafic_limit,
453 
  clk => clk,
454 
  reset => reset);
455 
 
456 
process(clk,reset)
457 
begin
458 
if reset='1' then
459 
  wb32_pci_master_bg_q <= '0';
460 
elsif clk'event and clk='1' then
461 
if wb32_pci_master_bg_q='0' then
462 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
463 
elsif ack='1' then
464 
  wb32_pci_master_bg_q <= '0';
465 
end if;
466 
end if;
467 
end process;
468 
 
469 
process(clk,reset)
470 
begin
471 
if reset='1' then
472 
  wbm_z80_bg_q <= '0';
473 
elsif clk'event and clk='1' then
474 
if wbm_z80_bg_q='0' then
475 
  wbm_z80_bg_q <= wbm_z80_bg;
476 
elsif ack='1' then
477 
  wbm_z80_bg_q <= '0';
478 
end if;
479 
end if;
480 
end process;
481 
 
482 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
483 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_ddr_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
484 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_ddr_ss='1' and wbm_z80_trafic_limit='0' else '0';
485 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_ddr_ss='1' else '0';
486 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_ddr_ss='1' else '0';
487 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
488 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
489 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_ddr_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_ddr_ss) when idle='1' else '0';
490 
wb32_pci_master_wbs_ddr_bg <= wb32_pci_master_bg;
491 
wbm_z80_wbs_ddr_bg <= wbm_z80_bg;
492 
end block arbiter_wbs_ddr;
493 
arbiter_wbs_vga : block
494 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
495 
  signal wb32_pci_master_trafic_limit : std_logic;
496 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
497 
  signal wbm_z80_trafic_limit : std_logic;
498 
  signal ce, idle, ack : std_logic;
499 
begin
500 30 hharte 
ack <= wbs_vga_ack_o;
501 3 hharte 
 
502 
trafic_supervision_1 : entity work.trafic_supervision
503 
generic map(
504 
  priority => 4,
505 
  tot_priority => 8)
506 
port map(
507 30 hharte 
  bg => wb32_pci_master_wbs_vga_bg,
508 3 hharte 
  ce => ce,
509 
  trafic_limit => wb32_pci_master_trafic_limit,
510 
  clk => clk,
511 
  reset => reset);
512 
 
513 
trafic_supervision_2 : entity work.trafic_supervision
514 
generic map(
515 
  priority => 4,
516 
  tot_priority => 8)
517 
port map(
518 30 hharte 
  bg => wbm_z80_wbs_vga_bg,
519 3 hharte 
  ce => ce,
520 
  trafic_limit => wbm_z80_trafic_limit,
521 
  clk => clk,
522 
  reset => reset);
523 
 
524 
process(clk,reset)
525 
begin
526 
if reset='1' then
527 
  wb32_pci_master_bg_q <= '0';
528 
elsif clk'event and clk='1' then
529 
if wb32_pci_master_bg_q='0' then
530 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
531 
elsif ack='1' then
532 
  wb32_pci_master_bg_q <= '0';
533 
end if;
534 
end if;
535 
end process;
536 
 
537 
process(clk,reset)
538 
begin
539 
if reset='1' then
540 
  wbm_z80_bg_q <= '0';
541 
elsif clk'event and clk='1' then
542 
if wbm_z80_bg_q='0' then
543 
  wbm_z80_bg_q <= wbm_z80_bg;
544 
elsif ack='1' then
545 
  wbm_z80_bg_q <= '0';
546 
end if;
547 
end if;
548 
end process;
549 
 
550 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
551 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_vga_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
552 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_vga_ss='1' and wbm_z80_trafic_limit='0' else '0';
553 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_vga_ss='1' else '0';
554 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_vga_ss='1' else '0';
555 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
556 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
557 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_vga_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_vga_ss) when idle='1' else '0';
558 
wb32_pci_master_wbs_vga_bg <= wb32_pci_master_bg;
559 
wbm_z80_wbs_vga_bg <= wbm_z80_bg;
560 
end block arbiter_wbs_vga;
561 
arbiter_wbs_kbd : block
562 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
563 
  signal wb32_pci_master_trafic_limit : std_logic;
564 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
565 
  signal wbm_z80_trafic_limit : std_logic;
566 
  signal ce, idle, ack : std_logic;
567 
begin
568 30 hharte 
ack <= wbs_kbd_ack_o;
569 3 hharte 
 
570 
trafic_supervision_1 : entity work.trafic_supervision
571 
generic map(
572 
  priority => 5,
573 
  tot_priority => 10)
574 
port map(
575 30 hharte 
  bg => wb32_pci_master_wbs_kbd_bg,
576 3 hharte 
  ce => ce,
577 
  trafic_limit => wb32_pci_master_trafic_limit,
578 
  clk => clk,
579 
  reset => reset);
580 
 
581 
trafic_supervision_2 : entity work.trafic_supervision
582 
generic map(
583 
  priority => 5,
584 
  tot_priority => 10)
585 
port map(
586 30 hharte 
  bg => wbm_z80_wbs_kbd_bg,
587 3 hharte 
  ce => ce,
588 
  trafic_limit => wbm_z80_trafic_limit,
589 
  clk => clk,
590 
  reset => reset);
591 
 
592 
process(clk,reset)
593 
begin
594 
if reset='1' then
595 
  wb32_pci_master_bg_q <= '0';
596 
elsif clk'event and clk='1' then
597 
if wb32_pci_master_bg_q='0' then
598 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
599 
elsif ack='1' then
600 
  wb32_pci_master_bg_q <= '0';
601 
end if;
602 
end if;
603 
end process;
604 
 
605 
process(clk,reset)
606 
begin
607 
if reset='1' then
608 
  wbm_z80_bg_q <= '0';
609 
elsif clk'event and clk='1' then
610 
if wbm_z80_bg_q='0' then
611 
  wbm_z80_bg_q <= wbm_z80_bg;
612 
elsif ack='1' then
613 
  wbm_z80_bg_q <= '0';
614 
end if;
615 
end if;
616 
end process;
617 
 
618 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
619 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_kbd_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
620 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_kbd_ss='1' and wbm_z80_trafic_limit='0' else '0';
621 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_kbd_ss='1' else '0';
622 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_kbd_ss='1' else '0';
623 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
624 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
625 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_kbd_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_kbd_ss) when idle='1' else '0';
626 
wb32_pci_master_wbs_kbd_bg <= wb32_pci_master_bg;
627 
wbm_z80_wbs_kbd_bg <= wbm_z80_bg;
628 
end block arbiter_wbs_kbd;
629 
arbiter_wbs_mmu : block
630 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
631 
  signal wb32_pci_master_trafic_limit : std_logic;
632 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
633 
  signal wbm_z80_trafic_limit : std_logic;
634 
  signal ce, idle, ack : std_logic;
635 
begin
636 30 hharte 
ack <= wbs_mmu_ack_o;
637 3 hharte 
 
638 
trafic_supervision_1 : entity work.trafic_supervision
639 
generic map(
640 
  priority => 6,
641 
  tot_priority => 12)
642 
port map(
643 30 hharte 
  bg => wb32_pci_master_wbs_mmu_bg,
644 3 hharte 
  ce => ce,
645 
  trafic_limit => wb32_pci_master_trafic_limit,
646 
  clk => clk,
647 
  reset => reset);
648 
 
649 
trafic_supervision_2 : entity work.trafic_supervision
650 
generic map(
651 
  priority => 6,
652 
  tot_priority => 12)
653 
port map(
654 30 hharte 
  bg => wbm_z80_wbs_mmu_bg,
655 3 hharte 
  ce => ce,
656 
  trafic_limit => wbm_z80_trafic_limit,
657 
  clk => clk,
658 
  reset => reset);
659 
 
660 
process(clk,reset)
661 
begin
662 
if reset='1' then
663 
  wb32_pci_master_bg_q <= '0';
664 
elsif clk'event and clk='1' then
665 
if wb32_pci_master_bg_q='0' then
666 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
667 
elsif ack='1' then
668 
  wb32_pci_master_bg_q <= '0';
669 
end if;
670 
end if;
671 
end process;
672 
 
673 
process(clk,reset)
674 
begin
675 
if reset='1' then
676 
  wbm_z80_bg_q <= '0';
677 
elsif clk'event and clk='1' then
678 
if wbm_z80_bg_q='0' then
679 
  wbm_z80_bg_q <= wbm_z80_bg;
680 
elsif ack='1' then
681 
  wbm_z80_bg_q <= '0';
682 
end if;
683 
end if;
684 
end process;
685 
 
686 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
687 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_mmu_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
688 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_mmu_ss='1' and wbm_z80_trafic_limit='0' else '0';
689 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_mmu_ss='1' else '0';
690 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_mmu_ss='1' else '0';
691 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
692 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
693 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_mmu_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_mmu_ss) when idle='1' else '0';
694 
wb32_pci_master_wbs_mmu_bg <= wb32_pci_master_bg;
695 
wbm_z80_wbs_mmu_bg <= wbm_z80_bg;
696 
end block arbiter_wbs_mmu;
697 
arbiter_wb_cpu_ctrl : block
698 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
699 
  signal wb32_pci_master_trafic_limit : std_logic;
700 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
701 
  signal wbm_z80_trafic_limit : std_logic;
702 
  signal ce, idle, ack : std_logic;
703 
begin
704 30 hharte 
ack <= wb_cpu_ctrl_ack_o;
705 3 hharte 
 
706 
trafic_supervision_1 : entity work.trafic_supervision
707 
generic map(
708 
  priority => 7,
709 
  tot_priority => 14)
710 
port map(
711 30 hharte 
  bg => wb32_pci_master_wb_cpu_ctrl_bg,
712 3 hharte 
  ce => ce,
713 
  trafic_limit => wb32_pci_master_trafic_limit,
714 
  clk => clk,
715 
  reset => reset);
716 
 
717 
trafic_supervision_2 : entity work.trafic_supervision
718 
generic map(
719 
  priority => 7,
720 
  tot_priority => 14)
721 
port map(
722 30 hharte 
  bg => wbm_z80_wb_cpu_ctrl_bg,
723 3 hharte 
  ce => ce,
724 
  trafic_limit => wbm_z80_trafic_limit,
725 
  clk => clk,
726 
  reset => reset);
727 
 
728 
process(clk,reset)
729 
begin
730 
if reset='1' then
731 
  wb32_pci_master_bg_q <= '0';
732 
elsif clk'event and clk='1' then
733 
if wb32_pci_master_bg_q='0' then
734 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
735 
elsif ack='1' then
736 
  wb32_pci_master_bg_q <= '0';
737 
end if;
738 
end if;
739 
end process;
740 
 
741 
process(clk,reset)
742 
begin
743 
if reset='1' then
744 
  wbm_z80_bg_q <= '0';
745 
elsif clk'event and clk='1' then
746 
if wbm_z80_bg_q='0' then
747 
  wbm_z80_bg_q <= wbm_z80_bg;
748 
elsif ack='1' then
749 
  wbm_z80_bg_q <= '0';
750 
end if;
751 
end if;
752 
end process;
753 
 
754 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
755 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wb_cpu_ctrl_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
756 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wb_cpu_ctrl_ss='1' and wbm_z80_trafic_limit='0' else '0';
757 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wb_cpu_ctrl_ss='1' else '0';
758 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wb_cpu_ctrl_ss='1' else '0';
759 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
760 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
761 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wb_cpu_ctrl_ss) or (wbm_z80_cyc_o and wbm_z80_wb_cpu_ctrl_ss) when idle='1' else '0';
762 
wb32_pci_master_wb_cpu_ctrl_bg <= wb32_pci_master_bg;
763 
wbm_z80_wb_cpu_ctrl_bg <= wbm_z80_bg;
764 
end block arbiter_wb_cpu_ctrl;
765 
arbiter_wbs_spimaster : block
766 3 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
767 
  signal wb32_pci_master_trafic_limit : std_logic;
768 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
769 
  signal wbm_z80_trafic_limit : std_logic;
770 
  signal ce, idle, ack : std_logic;
771 
begin
772 30 hharte 
ack <= wbs_spimaster_ack_o;
773 3 hharte 
 
774 
trafic_supervision_1 : entity work.trafic_supervision
775 
generic map(
776 
  priority => 8,
777 
  tot_priority => 16)
778 
port map(
779 30 hharte 
  bg => wb32_pci_master_wbs_spimaster_bg,
780 3 hharte 
  ce => ce,
781 
  trafic_limit => wb32_pci_master_trafic_limit,
782 
  clk => clk,
783 
  reset => reset);
784 
 
785 
trafic_supervision_2 : entity work.trafic_supervision
786 
generic map(
787 
  priority => 8,
788 
  tot_priority => 16)
789 
port map(
790 30 hharte 
  bg => wbm_z80_wbs_spimaster_bg,
791 3 hharte 
  ce => ce,
792 
  trafic_limit => wbm_z80_trafic_limit,
793 
  clk => clk,
794 
  reset => reset);
795 
 
796 
process(clk,reset)
797 
begin
798 
if reset='1' then
799 
  wb32_pci_master_bg_q <= '0';
800 
elsif clk'event and clk='1' then
801 
if wb32_pci_master_bg_q='0' then
802 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
803 
elsif ack='1' then
804 
  wb32_pci_master_bg_q <= '0';
805 
end if;
806 
end if;
807 
end process;
808 
 
809 
process(clk,reset)
810 
begin
811 
if reset='1' then
812 
  wbm_z80_bg_q <= '0';
813 
elsif clk'event and clk='1' then
814 
if wbm_z80_bg_q='0' then
815 
  wbm_z80_bg_q <= wbm_z80_bg;
816 
elsif ack='1' then
817 
  wbm_z80_bg_q <= '0';
818 
end if;
819 
end if;
820 
end process;
821 
 
822 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
823 30 hharte 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_spimaster_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
824 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_spimaster_ss='1' and wbm_z80_trafic_limit='0' else '0';
825 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_spimaster_ss='1' else '0';
826 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_spimaster_ss='1' else '0';
827 3 hharte 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
828 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
829 30 hharte 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_spimaster_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_spimaster_ss) when idle='1' else '0';
830 
wb32_pci_master_wbs_spimaster_bg <= wb32_pci_master_bg;
831 
wbm_z80_wbs_spimaster_bg <= wbm_z80_bg;
832 
end block arbiter_wbs_spimaster;
833 13 hharte 
arbiter_wbs_vhdfd : block
834 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
835 
  signal wb32_pci_master_trafic_limit : std_logic;
836 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
837 
  signal wbm_z80_trafic_limit : std_logic;
838 
  signal ce, idle, ack : std_logic;
839 
begin
840 
ack <= wbs_vhdfd_ack_o;
841 
 
842 
trafic_supervision_1 : entity work.trafic_supervision
843 
generic map(
844 
  priority => 9,
845 
  tot_priority => 18)
846 
port map(
847 
  bg => wb32_pci_master_wbs_vhdfd_bg,
848 
  ce => ce,
849 
  trafic_limit => wb32_pci_master_trafic_limit,
850 
  clk => clk,
851 
  reset => reset);
852 
 
853 
trafic_supervision_2 : entity work.trafic_supervision
854 
generic map(
855 
  priority => 9,
856 
  tot_priority => 18)
857 
port map(
858 
  bg => wbm_z80_wbs_vhdfd_bg,
859 
  ce => ce,
860 
  trafic_limit => wbm_z80_trafic_limit,
861 
  clk => clk,
862 
  reset => reset);
863 
 
864 
process(clk,reset)
865 
begin
866 
if reset='1' then
867 
  wb32_pci_master_bg_q <= '0';
868 
elsif clk'event and clk='1' then
869 
if wb32_pci_master_bg_q='0' then
870 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
871 
elsif ack='1' then
872 
  wb32_pci_master_bg_q <= '0';
873 
end if;
874 
end if;
875 
end process;
876 
 
877 
process(clk,reset)
878 
begin
879 
if reset='1' then
880 
  wbm_z80_bg_q <= '0';
881 
elsif clk'event and clk='1' then
882 
if wbm_z80_bg_q='0' then
883 
  wbm_z80_bg_q <= wbm_z80_bg;
884 
elsif ack='1' then
885 
  wbm_z80_bg_q <= '0';
886 
end if;
887 
end if;
888 
end process;
889 
 
890 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
891 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_vhdfd_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
892 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_vhdfd_ss='1' and wbm_z80_trafic_limit='0' else '0';
893 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_vhdfd_ss='1' else '0';
894 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_vhdfd_ss='1' else '0';
895 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
896 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
897 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_vhdfd_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_vhdfd_ss) when idle='1' else '0';
898 
wb32_pci_master_wbs_vhdfd_bg <= wb32_pci_master_bg;
899 
wbm_z80_wbs_vhdfd_bg <= wbm_z80_bg;
900 
end block arbiter_wbs_vhdfd;
901 30 hharte 
arbiter_wbs_fpb : block
902 13 hharte 
  signal wb32_pci_master_bg, wb32_pci_master_bg_1, wb32_pci_master_bg_2, wb32_pci_master_bg_q : std_logic;
903 
  signal wb32_pci_master_trafic_limit : std_logic;
904 
  signal wbm_z80_bg, wbm_z80_bg_1, wbm_z80_bg_2, wbm_z80_bg_q : std_logic;
905 
  signal wbm_z80_trafic_limit : std_logic;
906 
  signal ce, idle, ack : std_logic;
907 
begin
908 30 hharte 
ack <= wbs_fpb_ack_o;
909 13 hharte 
 
910 
trafic_supervision_1 : entity work.trafic_supervision
911 
generic map(
912 
  priority => 10,
913 
  tot_priority => 20)
914 
port map(
915 30 hharte 
  bg => wb32_pci_master_wbs_fpb_bg,
916 13 hharte 
  ce => ce,
917 
  trafic_limit => wb32_pci_master_trafic_limit,
918 
  clk => clk,
919 
  reset => reset);
920 
 
921 
trafic_supervision_2 : entity work.trafic_supervision
922 
generic map(
923 
  priority => 10,
924 
  tot_priority => 20)
925 
port map(
926 
  bg => wbm_z80_wbs_fpb_bg,
927 
  ce => ce,
928 
  trafic_limit => wbm_z80_trafic_limit,
929 
  clk => clk,
930 
  reset => reset);
931 
 
932 
process(clk,reset)
933 
begin
934 
if reset='1' then
935 
  wb32_pci_master_bg_q <= '0';
936 
elsif clk'event and clk='1' then
937 
if wb32_pci_master_bg_q='0' then
938 
  wb32_pci_master_bg_q <= wb32_pci_master_bg;
939 
elsif ack='1' then
940 
  wb32_pci_master_bg_q <= '0';
941 
end if;
942 
end if;
943 
end process;
944 
 
945 
process(clk,reset)
946 
begin
947 
if reset='1' then
948 
  wbm_z80_bg_q <= '0';
949 
elsif clk'event and clk='1' then
950 
if wbm_z80_bg_q='0' then
951 
  wbm_z80_bg_q <= wbm_z80_bg;
952 
elsif ack='1' then
953 
  wbm_z80_bg_q <= '0';
954 
end if;
955 
end if;
956 
end process;
957 
 
958 
idle <= '1' when wb32_pci_master_bg_q='0' and wbm_z80_bg_q='0' else '0';
959 
wb32_pci_master_bg_1 <= '1' when idle='1' and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_fpb_ss='1' and wb32_pci_master_trafic_limit='0' else '0';
960 
wbm_z80_bg_1 <= '1' when idle='1' and (wb32_pci_master_bg_1='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_fpb_ss='1' and wbm_z80_trafic_limit='0' else '0';
961 
wb32_pci_master_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0') and wb32_pci_master_cyc_o='1' and wb32_pci_master_wbs_fpb_ss='1' else '0';
962 
wbm_z80_bg_2 <= '1' when idle='1' and (wb32_pci_master_bg_1='0' and wbm_z80_bg_1='0' and wb32_pci_master_bg_2='0') and wbm_z80_cyc_o='1' and wbm_z80_wbs_fpb_ss='1' else '0';
963 
wb32_pci_master_bg <= wb32_pci_master_bg_q or wb32_pci_master_bg_1 or wb32_pci_master_bg_2;
964 
wbm_z80_bg <= wbm_z80_bg_q or wbm_z80_bg_1 or wbm_z80_bg_2;
965 
ce <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_fpb_ss) or (wbm_z80_cyc_o and wbm_z80_wbs_fpb_ss) when idle='1' else '0';
966 
wb32_pci_master_wbs_fpb_bg <= wb32_pci_master_bg;
967 
wbm_z80_wbs_fpb_bg <= wbm_z80_bg;
968 
end block arbiter_wbs_fpb;
969 3 hharte 
decoder:block
970 
begin
971 30 hharte 
wb32_pci_master_wbs_sram_ss <= '1' when wb32_pci_master_adr_o(23 downto 20)="0001" else
972 3 hharte 
'0';
973 
wb32_pci_master_wbs_flash_ss <= '1' when wb32_pci_master_adr_o(23 downto 20)="0010" else
974 
'0';
975 
wb32_pci_master_wbs_ddr_ss <= '1' when wb32_pci_master_adr_o(23 downto 20)="1000" else
976 
'0';
977 
wb32_pci_master_wbs_vga_ss <= '1' when wb32_pci_master_adr_o(23 downto 20)="0110" else
978 
'0';
979 30 hharte 
wb32_pci_master_wbs_kbd_ss <= '1' when wb32_pci_master_adr_o(23 downto 5)="0000000000000000000" else
980 3 hharte 
'0';
981 30 hharte 
wb32_pci_master_wbs_mmu_ss <= '1' when wb32_pci_master_adr_o(23 downto 5)="0000000000000000001" else
982 3 hharte 
'0';
983 30 hharte 
wb32_pci_master_wb_cpu_ctrl_ss <= '1' when wb32_pci_master_adr_o(23 downto 6)="000000000000000001" else
984 3 hharte 
'0';
985 13 hharte 
wb32_pci_master_wbs_spimaster_ss <= '1' when wb32_pci_master_adr_o(23 downto 6)="000000000000000010" else
986 
'0';
987 30 hharte 
wb32_pci_master_wbs_vhdfd_ss <= '1' when wb32_pci_master_adr_o(23 downto 5)="0000000000000000110" else
988 
'0';
989 13 hharte 
wb32_pci_master_wbs_fpb_ss <= '1' when wb32_pci_master_adr_o(23 downto 5)="0000000000000000111" else
990 
'0';
991 30 hharte 
wbm_z80_wbs_sram_ss <= '1' when wbm_z80_adr_o(23 downto 20)="0001" else
992 13 hharte 
'0';
993 3 hharte 
wbm_z80_wbs_flash_ss <= '1' when wbm_z80_adr_o(23 downto 20)="0010" else
994 
'0';
995 
wbm_z80_wbs_ddr_ss <= '1' when wbm_z80_adr_o(23 downto 20)="1000" else
996 
'0';
997 
wbm_z80_wbs_vga_ss <= '1' when wbm_z80_adr_o(23 downto 20)="0110" else
998 
'0';
999 30 hharte 
wbm_z80_wbs_kbd_ss <= '1' when wbm_z80_adr_o(23 downto 5)="0000000000000000000" else
1000 3 hharte 
'0';
1001 30 hharte 
wbm_z80_wbs_mmu_ss <= '1' when wbm_z80_adr_o(23 downto 5)="0000000000000000001" else
1002 3 hharte 
'0';
1003 30 hharte 
wbm_z80_wb_cpu_ctrl_ss <= '1' when wbm_z80_adr_o(23 downto 6)="000000000000000001" else
1004 13 hharte 
'0';
1005 
wbm_z80_wbs_spimaster_ss <= '1' when wbm_z80_adr_o(23 downto 6)="000000000000000010" else
1006 
'0';
1007 30 hharte 
wbm_z80_wbs_vhdfd_ss <= '1' when wbm_z80_adr_o(23 downto 5)="0000000000000000110" else
1008 
'0';
1009 13 hharte 
wbm_z80_wbs_fpb_ss <= '1' when wbm_z80_adr_o(23 downto 5)="0000000000000000111" else
1010 
'0';
1011 30 hharte 
wbs_sram_adr_i <= (wb32_pci_master_adr_o(14 downto 0) and wb32_pci_master_wbs_sram_bg) or (wbm_z80_adr_o(14 downto 0) and wbm_z80_wbs_sram_bg);
1012 3 hharte 
wbs_flash_adr_i <= (wb32_pci_master_adr_o(18 downto 0) and wb32_pci_master_wbs_flash_bg) or (wbm_z80_adr_o(18 downto 0) and wbm_z80_wbs_flash_bg);
1013 
wbs_ddr_adr_i <= (wb32_pci_master_adr_o(19 downto 0) and wb32_pci_master_wbs_ddr_bg) or (wbm_z80_adr_o(19 downto 0) and wbm_z80_wbs_ddr_bg);
1014 30 hharte 
wbs_vga_adr_i <= (wb32_pci_master_adr_o(13 downto 0) and wb32_pci_master_wbs_vga_bg) or (wbm_z80_adr_o(13 downto 0) and wbm_z80_wbs_vga_bg);
1015 
wbs_kbd_adr_i <= (wb32_pci_master_adr_o(2 downto 0) and wb32_pci_master_wbs_kbd_bg) or (wbm_z80_adr_o(2 downto 0) and wbm_z80_wbs_kbd_bg);
1016 13 hharte 
wbs_mmu_adr_i <= (wb32_pci_master_adr_o(1 downto 0) and wb32_pci_master_wbs_mmu_bg) or (wbm_z80_adr_o(1 downto 0) and wbm_z80_wbs_mmu_bg);
1017 30 hharte 
wb_cpu_ctrl_adr_i <= (wb32_pci_master_adr_o(2 downto 0) and wb32_pci_master_wb_cpu_ctrl_bg) or (wbm_z80_adr_o(2 downto 0) and wbm_z80_wb_cpu_ctrl_bg);
1018 
wbs_spimaster_adr_i <= (wb32_pci_master_adr_o(5 downto 0) and wb32_pci_master_wbs_spimaster_bg) or (wbm_z80_adr_o(5 downto 0) and wbm_z80_wbs_spimaster_bg);
1019 13 hharte 
wbs_vhdfd_adr_i <= (wb32_pci_master_adr_o(2 downto 0) and wb32_pci_master_wbs_vhdfd_bg) or (wbm_z80_adr_o(2 downto 0) and wbm_z80_wbs_vhdfd_bg);
1020 
wbs_fpb_adr_i <= (wb32_pci_master_adr_o(4 downto 0) and wb32_pci_master_wbs_fpb_bg) or (wbm_z80_adr_o(4 downto 0) and wbm_z80_wbs_fpb_bg);
1021 3 hharte 
end block decoder;
1022 
 
1023 
-- cyc_i(s)
1024 30 hharte 
wbs_sram_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_sram_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_sram_bg);
1025 3 hharte 
wbs_flash_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_flash_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_flash_bg);
1026 
wbs_ddr_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_ddr_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_ddr_bg);
1027 30 hharte 
wbs_vga_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_vga_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_vga_bg);
1028 
wbs_kbd_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_kbd_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_kbd_bg);
1029 3 hharte 
wbs_mmu_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_mmu_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_mmu_bg);
1030 30 hharte 
wb_cpu_ctrl_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wb_cpu_ctrl_bg) or (wbm_z80_cyc_o and wbm_z80_wb_cpu_ctrl_bg);
1031 
wbs_spimaster_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_spimaster_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_spimaster_bg);
1032 13 hharte 
wbs_vhdfd_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_vhdfd_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_vhdfd_bg);
1033 
wbs_fpb_cyc_i <= (wb32_pci_master_cyc_o and wb32_pci_master_wbs_fpb_bg) or (wbm_z80_cyc_o and wbm_z80_wbs_fpb_bg);
1034 3 hharte 
-- stb_i(s)
1035 30 hharte 
wbs_sram_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_sram_bg) or (wbm_z80_stb_o and wbm_z80_wbs_sram_bg);
1036 3 hharte 
wbs_flash_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_flash_bg) or (wbm_z80_stb_o and wbm_z80_wbs_flash_bg);
1037 
wbs_ddr_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_ddr_bg) or (wbm_z80_stb_o and wbm_z80_wbs_ddr_bg);
1038 30 hharte 
wbs_vga_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_vga_bg) or (wbm_z80_stb_o and wbm_z80_wbs_vga_bg);
1039 
wbs_kbd_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_kbd_bg) or (wbm_z80_stb_o and wbm_z80_wbs_kbd_bg);
1040 3 hharte 
wbs_mmu_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_mmu_bg) or (wbm_z80_stb_o and wbm_z80_wbs_mmu_bg);
1041 30 hharte 
wb_cpu_ctrl_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wb_cpu_ctrl_bg) or (wbm_z80_stb_o and wbm_z80_wb_cpu_ctrl_bg);
1042 
wbs_spimaster_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_spimaster_bg) or (wbm_z80_stb_o and wbm_z80_wbs_spimaster_bg);
1043 13 hharte 
wbs_vhdfd_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_vhdfd_bg) or (wbm_z80_stb_o and wbm_z80_wbs_vhdfd_bg);
1044 
wbs_fpb_stb_i <= (wb32_pci_master_stb_o and wb32_pci_master_wbs_fpb_bg) or (wbm_z80_stb_o and wbm_z80_wbs_fpb_bg);
1045 3 hharte 
-- we_i(s)
1046 30 hharte 
wbs_sram_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_sram_bg) or (wbm_z80_we_o and wbm_z80_wbs_sram_bg);
1047 3 hharte 
wbs_flash_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_flash_bg) or (wbm_z80_we_o and wbm_z80_wbs_flash_bg);
1048 
wbs_ddr_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_ddr_bg) or (wbm_z80_we_o and wbm_z80_wbs_ddr_bg);
1049 30 hharte 
wbs_vga_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_vga_bg) or (wbm_z80_we_o and wbm_z80_wbs_vga_bg);
1050 
wbs_kbd_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_kbd_bg) or (wbm_z80_we_o and wbm_z80_wbs_kbd_bg);
1051 3 hharte 
wbs_mmu_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_mmu_bg) or (wbm_z80_we_o and wbm_z80_wbs_mmu_bg);
1052 30 hharte 
wb_cpu_ctrl_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wb_cpu_ctrl_bg) or (wbm_z80_we_o and wbm_z80_wb_cpu_ctrl_bg);
1053 
wbs_spimaster_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_spimaster_bg) or (wbm_z80_we_o and wbm_z80_wbs_spimaster_bg);
1054 13 hharte 
wbs_vhdfd_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_vhdfd_bg) or (wbm_z80_we_o and wbm_z80_wbs_vhdfd_bg);
1055 
wbs_fpb_we_i <= (wb32_pci_master_we_o and wb32_pci_master_wbs_fpb_bg) or (wbm_z80_we_o and wbm_z80_wbs_fpb_bg);
1056 3 hharte 
-- ack_i(s)
1057 30 hharte 
wb32_pci_master_ack_i <= (wbs_sram_ack_o and wb32_pci_master_wbs_sram_bg) or (wbs_flash_ack_o and wb32_pci_master_wbs_flash_bg) or (wbs_ddr_ack_o and wb32_pci_master_wbs_ddr_bg) or (wbs_vga_ack_o and wb32_pci_master_wbs_vga_bg) or (wbs_kbd_ack_o and wb32_pci_master_wbs_kbd_bg) or (wbs_mmu_ack_o and wb32_pci_master_wbs_mmu_bg) or (wb_cpu_ctrl_ack_o and wb32_pci_master_wb_cpu_ctrl_bg) or (wbs_spimaster_ack_o and wb32_pci_master_wbs_spimaster_bg) or (wbs_vhdfd_ack_o and wb32_pci_master_wbs_vhdfd_bg) or (wbs_fpb_ack_o and wb32_pci_master_wbs_fpb_bg);
1058 
wbm_z80_ack_i <= (wbs_sram_ack_o and wbm_z80_wbs_sram_bg) or (wbs_flash_ack_o and wbm_z80_wbs_flash_bg) or (wbs_ddr_ack_o and wbm_z80_wbs_ddr_bg) or (wbs_vga_ack_o and wbm_z80_wbs_vga_bg) or (wbs_kbd_ack_o and wbm_z80_wbs_kbd_bg) or (wbs_mmu_ack_o and wbm_z80_wbs_mmu_bg) or (wb_cpu_ctrl_ack_o and wbm_z80_wb_cpu_ctrl_bg) or (wbs_spimaster_ack_o and wbm_z80_wbs_spimaster_bg) or (wbs_vhdfd_ack_o and wbm_z80_wbs_vhdfd_bg) or (wbs_fpb_ack_o and wbm_z80_wbs_fpb_bg);
1059 3 hharte 
-- rty_i(s)
1060 
-- err_i(s)
1061 
wb32_pci_master_err_i <= '0';
1062 
-- sel_i(s)
1063 30 hharte 
wbs_sram_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_sram_bg) or (wbm_z80_sel_o and wbm_z80_wbs_sram_bg);
1064 3 hharte 
wbs_flash_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_flash_bg) or (wbm_z80_sel_o and wbm_z80_wbs_flash_bg);
1065 
wbs_ddr_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_ddr_bg) or (wbm_z80_sel_o and wbm_z80_wbs_ddr_bg);
1066 30 hharte 
wbs_vga_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_vga_bg) or (wbm_z80_sel_o and wbm_z80_wbs_vga_bg);
1067 
wbs_kbd_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_kbd_bg) or (wbm_z80_sel_o and wbm_z80_wbs_kbd_bg);
1068 3 hharte 
wbs_mmu_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_mmu_bg) or (wbm_z80_sel_o and wbm_z80_wbs_mmu_bg);
1069 30 hharte 
wb_cpu_ctrl_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wb_cpu_ctrl_bg) or (wbm_z80_sel_o and wbm_z80_wb_cpu_ctrl_bg);
1070 
wbs_spimaster_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_spimaster_bg) or (wbm_z80_sel_o and wbm_z80_wbs_spimaster_bg);
1071 13 hharte 
wbs_vhdfd_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_vhdfd_bg) or (wbm_z80_sel_o and wbm_z80_wbs_vhdfd_bg);
1072 
wbs_fpb_sel_i <= (wb32_pci_master_sel_o and wb32_pci_master_wbs_fpb_bg) or (wbm_z80_sel_o and wbm_z80_wbs_fpb_bg);
1073 3 hharte 
-- slave dat_i(s)
1074 30 hharte 
wbs_sram_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_sram_bg) or (wbm_z80_dat_o and wbm_z80_wbs_sram_bg);
1075 3 hharte 
wbs_flash_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_flash_bg) or (wbm_z80_dat_o and wbm_z80_wbs_flash_bg);
1076 
wbs_ddr_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_ddr_bg) or (wbm_z80_dat_o and wbm_z80_wbs_ddr_bg);
1077 30 hharte 
wbs_vga_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_vga_bg) or (wbm_z80_dat_o and wbm_z80_wbs_vga_bg);
1078 
wbs_kbd_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_kbd_bg) or (wbm_z80_dat_o and wbm_z80_wbs_kbd_bg);
1079 3 hharte 
wbs_mmu_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_mmu_bg) or (wbm_z80_dat_o and wbm_z80_wbs_mmu_bg);
1080 30 hharte 
wb_cpu_ctrl_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wb_cpu_ctrl_bg) or (wbm_z80_dat_o and wbm_z80_wb_cpu_ctrl_bg);
1081 
wbs_spimaster_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_spimaster_bg) or (wbm_z80_dat_o and wbm_z80_wbs_spimaster_bg);
1082 13 hharte 
wbs_vhdfd_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_vhdfd_bg) or (wbm_z80_dat_o and wbm_z80_wbs_vhdfd_bg);
1083 
wbs_fpb_dat_i <= (wb32_pci_master_dat_o and wb32_pci_master_wbs_fpb_bg) or (wbm_z80_dat_o and wbm_z80_wbs_fpb_bg);
1084 3 hharte 
-- master dat_i(s)
1085 30 hharte 
wb32_pci_master_dat_i <= (wbs_sram_dat_o and wb32_pci_master_wbs_sram_bg) or (wbs_flash_dat_o and wb32_pci_master_wbs_flash_bg) or (wbs_ddr_dat_o and wb32_pci_master_wbs_ddr_bg) or (wbs_vga_dat_o and wb32_pci_master_wbs_vga_bg) or (wbs_kbd_dat_o and wb32_pci_master_wbs_kbd_bg) or (wbs_mmu_dat_o and wb32_pci_master_wbs_mmu_bg) or (wb_cpu_ctrl_dat_o and wb32_pci_master_wb_cpu_ctrl_bg) or (wbs_spimaster_dat_o and wb32_pci_master_wbs_spimaster_bg) or (wbs_vhdfd_dat_o and wb32_pci_master_wbs_vhdfd_bg) or (wbs_fpb_dat_o and wb32_pci_master_wbs_fpb_bg);
1086 
wbm_z80_dat_i <= (wbs_sram_dat_o and wbm_z80_wbs_sram_bg) or (wbs_flash_dat_o and wbm_z80_wbs_flash_bg) or (wbs_ddr_dat_o and wbm_z80_wbs_ddr_bg) or (wbs_vga_dat_o and wbm_z80_wbs_vga_bg) or (wbs_kbd_dat_o and wbm_z80_wbs_kbd_bg) or (wbs_mmu_dat_o and wbm_z80_wbs_mmu_bg) or (wb_cpu_ctrl_dat_o and wbm_z80_wb_cpu_ctrl_bg) or (wbs_spimaster_dat_o and wbm_z80_wbs_spimaster_bg) or (wbs_vhdfd_dat_o and wbm_z80_wbs_vhdfd_bg) or (wbs_fpb_dat_o and wbm_z80_wbs_fpb_bg);
1087 3 hharte 
-- tgc_i
1088 
-- tga_i
1089 
end rtl;

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