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[/] [vg_z80_sbc/] [trunk/] [rtl/] [wb_ddr.v] - Blame information for rev 35

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//----------------------------------------------------------------------------
// Wishbone DDR Controller
// 
// (c) Joerg Bornschein (<jb@capsec.org>)
//----------------------------------------------------------------------------
 
`include "ddr_include.v"
 
module wb_ddr
#(
        parameter clk_freq     = 100000000,
        parameter clk_multiply = 12,
        parameter clk_divide   = 5,
        parameter phase_shift  = 0,
        parameter wait200_init = 26
) (
        input                    clk,
        input                    reset,
        //  DDR ports
        output             [2:0] ddr_clk,
        output             [2:0] ddr_clk_n,
        input                    ddr_clk_fb,
        output                   ddr_ras_n,
        output                   ddr_cas_n,
        output                   ddr_we_n,
        output             [1:0] ddr_cke,
        output             [1:0] ddr_cs_n,
        output        [  `A_RNG] ddr_a,
        output        [ `BA_RNG] ddr_ba,
        inout         [ `DQ_RNG] ddr_dq,
        inout         [`DQS_RNG] ddr_dqs,
        output        [ `DM_RNG] ddr_dm,
        // Wishbone Slave Interface
        input      [`WB_ADR_RNG] wb_adr_i,
        input      [`WB_DAT_RNG] wb_dat_i,
        output reg [`WB_DAT_RNG] wb_dat_o,
        input      [`WB_SEL_RNG] wb_sel_i,
        input                    wb_cyc_i,
        input                    wb_stb_i,
        input                    wb_we_i,
        output reg               wb_ack_o,
        // XXX Temporary DCM control input XXX
        output                   ps_ready,
        input                    ps_up,
        input                    ps_down,
        // XXX probe wires XXX
        output                   probe_clk,
        input              [7:0] probe_sel,
        output reg         [7:0] probe
);
 
//----------------------------------------------------------------------------
// Wishbone handling
//----------------------------------------------------------------------------
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
wire wb_wr = wb_stb_i & wb_cyc_i &  wb_we_i;
 
wire [`WB_WORD_RNG] wb_adr_word = wb_adr_i[`WB_WORD_RNG]; // word in bufferline
wire [`WB_SET_RNG]  wb_adr_set  = wb_adr_i[`WB_SET_RNG];  // index into wayX_ram
wire [`WB_TAG_RNG]  wb_adr_tag  = wb_adr_i[`WB_TAG_RNG];  // more significant bits
 
//----------------------------------------------------------------------------
// TAG RAM (2-way set assioziative)
//----------------------------------------------------------------------------
wire [`TAG_LINE_RNG] tag_load;
wire [`TAG_LINE_RNG] tag_store;
wire                 tag_we;
 
wire [`WB_TAG_RNG] tag_load_set0   = tag_load[`TAG_LINE_TAG0_RNG];
wire [`WB_TAG_RNG] tag_load_set1   = tag_load[`TAG_LINE_TAG1_RNG];
wire               tag_load_dirty0 = tag_load[`TAG_LINE_DIRTY0_RNG];
wire               tag_load_dirty1 = tag_load[`TAG_LINE_DIRTY1_RNG];
wire               tag_load_lru    = tag_load[`TAG_LINE_LRU_RNG];
 
reg [`WB_TAG_RNG] tag_store_set0;
reg [`WB_TAG_RNG] tag_store_set1;
reg               tag_store_dirty0;
reg               tag_store_dirty1;
reg               tag_store_lru;
 
assign tag_store[`TAG_LINE_TAG0_RNG]   = tag_store_set0;
assign tag_store[`TAG_LINE_TAG1_RNG]   = tag_store_set1;
assign tag_store[`TAG_LINE_DIRTY0_RNG] = tag_store_dirty0;
assign tag_store[`TAG_LINE_DIRTY1_RNG] = tag_store_dirty1;
assign tag_store[`TAG_LINE_LRU_RNG]    = tag_store_lru;
 
wire [`WB_SET_RNG]   ls_tag_adr;
wire [`TAG_LINE_RNG] ls_tag_load;
reg  [`TAG_LINE_RNG] ls_tag_store;
reg                  ls_tag_we;
 
dpram #(
        .adr_width(   7 ),
        .dat_width(  33 )
) tag_ram (
        .clk (     clk         ),
        //
        .adr0(     wb_adr_set  ),
        .dout0(    tag_load    ),
        .din0(     tag_store   ),
        .we0(      tag_we      ),
        //
        .adr1(     ls_tag_adr   ),
        .dout1(    ls_tag_load  ),
        .din1(     ls_tag_store ),
        .we1(      ls_tag_we    )
);
 
wire tag_load_match0 = (tag_load_set0 == wb_adr_tag);
wire tag_load_match1 = (tag_load_set1 == wb_adr_tag);
wire tag_load_match  = tag_load_match0 | tag_load_match1;
 
//----------------------------------------------------------------------------
// Buffer cache ram (2 ways)
//----------------------------------------------------------------------------
wire [8:0] wayX_adr = { wb_adr_set, wb_adr_word };
 
wire [`WAY_LINE_RNG]  way0_load, way1_load;
wire [`WAY_LINE_RNG]  wayX_store;
 
wire [31:0]   way0_load_dat   = way0_load[`WAY_DAT_RNG];
wire [31:0]   way1_load_dat   = way1_load[`WAY_DAT_RNG];
wire [3:0]    way0_load_valid = way0_load[`WAY_VALID_RNG];
wire [3:0]    way1_load_valid = way1_load[`WAY_VALID_RNG];
 
wire          way0_we;
wire          way1_we;
reg  [31:0]   wayX_store_dat;
reg  [3:0]    wayX_store_valid;
 
assign wayX_store[`WAY_DAT_RNG]   = wayX_store_dat;
assign wayX_store[`WAY_VALID_RNG] = wayX_store_valid;
 
wire [8:0]            ls_wayX_adr;
wire [`WAY_LINE_RNG]  ls_way0_load;
wire [`WAY_LINE_RNG]  ls_way1_load;
wire [`WAY_LINE_RNG]  ls_wayX_store;
wire                  ls_way0_we;
wire                  ls_way1_we;
reg                   ls_wayX_we;
 
wire way0_sel_valid = ( (~way0_load_valid & wb_sel_i) == 'b0);
wire way1_sel_valid = ( (~way1_load_valid & wb_sel_i) == 'b0);
wire wayX_sel_valid = (tag_load_match0) ? way0_sel_valid : way1_sel_valid;
 
// synthesis attribute ram_style of way0_ram is block
dpram #(
        .adr_width(   9 ),
        .dat_width(  36 )
) way0_ram (
        .clk(    clk         ),
        //
        .adr0(   wayX_adr    ),
        .dout0(  way0_load   ),
        .din0(   wayX_store  ),
        .we0(    way0_we     ),
        //
        .adr1(   ls_wayX_adr   ),
        .dout1(  ls_way0_load  ),
        .we1(    ls_way0_we    ),
        .din1(   ls_wayX_store )
);
 
// synthesis attribute ram_style of way1_ram is block
dpram #(
        .adr_width(   9 ),
        .dat_width(  36 )
) way1_ram (
        .clk(    clk         ),
        //
        .adr0(   wayX_adr    ),
        .dout0(  way1_load   ),
        .din0(   wayX_store  ),
        .we0(    way1_we     ),
        //
        .adr1(   ls_wayX_adr   ),
        .dout1(  ls_way1_load  ),
        .we1(    ls_way1_we    ),
        .din1(   ls_wayX_store )
);
 
//----------------------------------------------------------------------------
// Write/update buffer cache from wishbone side
//----------------------------------------------------------------------------
wire store_to_way0 =  tag_load_lru & ~tag_load_dirty0;   // store new data into way0?  XXX spill_done XXX
wire store_to_way1 = ~tag_load_lru & ~tag_load_dirty1;   // store new data into way1?  XXX spill_done XXX
wire store_to_way  =  store_to_way0 | store_to_way1;
 
reg update_lru0;  // 
reg update_lru1;
 
reg update_way0;  //
reg update_way1;
 
assign way0_we = update_way0;
assign way1_we = update_way1;
assign tag_we  = way0_we | way1_we | update_lru0 | update_lru1;
 
//----------------------------------------------------------------------------
// MUX wayX_store input
//----------------------------------------------------------------------------
 
integer  i;
always @(*)
begin
/*
        for(i=0; i<4; i=i+1) begin
                if (wb_sel_i[i]) begin
                        wayX_store_dat[8*i+7:8*i] = wb_dat_i[8*i+7:8*i];
                        wayX_store_valid[i]       = 1;
                end else if (update_way0) begin
                        wayX_store_dat[8*i+7:8*i] = way0_load_dat[8*i+7:8*i];
                        wayX_store_valid[i]       = way0_load_valid[i];
                end else begin
                        wayX_store_dat[8*i+7:8*i] = way1_load_dat[8*i+7:8*i];
                        wayX_store_valid[i]       = way1_load_valid[i];
                end
        end
*/
 
        if (wb_sel_i[0]) begin
                wayX_store_dat[8*0+7:8*0] = wb_dat_i[8*0+7:8*0];
                wayX_store_valid[0]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*0+7:8*0] = way0_load_dat[8*0+7:8*0];
                wayX_store_valid[0]       = way0_load_valid[0];
        end else begin
                wayX_store_dat[8*0+7:8*0] = way1_load_dat[8*0+7:8*0];
                wayX_store_valid[0]       = way1_load_valid[0];
        end
 
        if (wb_sel_i[1]) begin
                wayX_store_dat[8*1+7:8*1] = wb_dat_i[8*1+7:8*1];
                wayX_store_valid[1]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*1+7:8*1] = way0_load_dat[8*1+7:8*1];
                wayX_store_valid[1]       = way0_load_valid[1];
        end else begin
                wayX_store_dat[8*1+7:8*1] = way1_load_dat[8*1+7:8*1];
                wayX_store_valid[1]       = way1_load_valid[1];
        end
 
        if (wb_sel_i[2]) begin
                wayX_store_dat[8*2+7:8*2] = wb_dat_i[8*2+7:8*2];
                wayX_store_valid[2]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*2+7:8*2] = way0_load_dat[8*2+7:8*2];
                wayX_store_valid[2]       = way0_load_valid[2];
        end else begin
                wayX_store_dat[8*2+7:8*2] = way1_load_dat[8*2+7:8*2];
                wayX_store_valid[2]       = way1_load_valid[2];
        end
 
        if (wb_sel_i[3]) begin
                wayX_store_dat[8*3+7:8*3] = wb_dat_i[8*3+7:8*3];
                wayX_store_valid[3]       = 1;
        end else if (update_way0) begin
                wayX_store_dat[8*3+7:8*3] = way0_load_dat[8*3+7:8*3];
                wayX_store_valid[3]       = way0_load_valid[3];
        end else begin
                wayX_store_dat[8*3+7:8*3] = way1_load_dat[8*3+7:8*3];
                wayX_store_valid[3]       = way1_load_valid[3];
        end
end
 
always @(*)
begin
        if (update_way0) begin
                tag_store_set0    = wb_adr_tag;
                tag_store_dirty0  = 1;
        end else begin
                tag_store_set0    = tag_load_set0;
                tag_store_dirty0  = tag_load_dirty0;
        end
 
        if (update_way1) begin
                tag_store_set1    = wb_adr_tag;
                tag_store_dirty1  = 1;
        end else begin
                tag_store_set1    = tag_load_set1;
                tag_store_dirty1  = tag_load_dirty1;
        end
 
        if (update_lru0)
                tag_store_lru     = 0;
        else if (update_lru1)
                tag_store_lru     = 1;
        else
                tag_store_lru     = tag_load_lru;
end
 
//----------------------------------------------------------------------------
// Wishbone FSM
//----------------------------------------------------------------------------
reg  ls_fill;
reg  ls_spill;
reg  ls_way;
wire ls_busy;
 
reg [`WB_TAG_RNG]  ls_adr_tag;
reg [`WB_SET_RNG]  ls_adr_set;
reg [`WB_WORD_RNG] ls_adr_word;
 
reg  [2:0] state;
 
parameter s_idle   = 0;
parameter s_read   = 1;
parameter s_rspill = 2;
parameter s_rfill  = 3;
parameter s_write  = 4;
parameter s_wspill = 5;
 
// Syncronous part of FSM
always @(posedge clk)
begin
        if (reset) begin
                state    <= s_idle;
                ls_spill <= 0;
                ls_fill  <= 0;
                ls_way   <= 0;
        end else begin
                ls_fill   <=  0;
                ls_spill  <=  0;
 
                case (state)
                s_idle: begin
                        if (wb_rd)
                                state      <= s_read;
 
                        if (wb_wr)
                                state      <= s_write;
                end
                s_read: begin
                        if ((tag_load_match0 & way0_sel_valid) | (tag_load_match1 & way1_sel_valid)) begin
                                state      <= s_idle;
                        end else if (store_to_way & ~ls_busy) begin
                                state      <= s_rfill;
                                ls_fill    <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_tag <=  wb_adr_tag;
                                ls_adr_set <=  wb_adr_set;
                        end else if (~ls_busy) begin
                                state      <= s_rspill;
                                ls_spill   <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_set <=  wb_adr_set;
                                if (tag_load_lru == 1)
                                        ls_adr_tag <=  tag_load_set0;
                                else
                                        ls_adr_tag <=  tag_load_set1;
                        end
                end
                s_rspill: begin
                        if (~ls_busy) begin
                                state      <= s_rfill;
                                ls_fill    <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_tag <=  wb_adr_tag;
                                ls_adr_set <=  wb_adr_set;
                        end
                end
                s_rfill: begin
                        if (tag_load_match & wayX_sel_valid)
                                state      <= s_idle;
                end
                s_write: begin
                        if (tag_load_match | store_to_way) begin
                                state      <= s_idle;
                        end else if (~ls_busy) begin
                                state      <= s_wspill;
                                ls_spill   <=  1;
                                ls_way     <= ~tag_load_lru;
                                ls_adr_set <=  wb_adr_set;
                                if (tag_load_lru == 1)
                                        ls_adr_tag <=  tag_load_set0;
                                else
                                        ls_adr_tag <=  tag_load_set1;
                        end
                end
                s_wspill: begin
                        if (tag_load_match | store_to_way) begin
                                state      <= s_idle;
                        end
                end
                default:
                        state <= s_idle;
                endcase
        end
end
 
// Asyncronous part of FSM
always @(*)
begin
        update_lru0  <= 0;
        update_lru1  <= 0;
        update_way0  <= 0;
        update_way1  <= 0;
        wb_dat_o     <= 0;
        wb_ack_o     <= 0;
 
        case (state)
        s_idle: begin end
        s_read: begin
                if (tag_load_match0 & way0_sel_valid) begin
                        update_lru0  <= 1;
                        wb_dat_o     <= way0_load_dat;
                        wb_ack_o     <= 1;
                end else if (tag_load_match1 & way1_sel_valid) begin
                        update_lru1  <= 1;
                        wb_dat_o     <= way1_load_dat;
                        wb_ack_o     <= 1;
                end
        end
        s_write: begin
                if (tag_load_match0 | store_to_way0) begin
                        update_lru0  <= 1;
                        update_way0  <= 1;
                        wb_ack_o     <= 1;
                end else if (tag_load_match1 | store_to_way1) begin
                        update_lru1  <= 1;
                        update_way1  <= 1;
                        wb_ack_o     <= 1;
                end
        end
        endcase
end
 
 
 
//----------------------------------------------------------------------------
// DDR Controller Engine (including clkgen, [rw]-path)
//----------------------------------------------------------------------------
reg                 fml_rd;
reg                 fml_wr;
wire                fml_done;
wire [`FML_ADR_RNG] fml_adr;
wire [`FML_DAT_RNG] fml_wdat;
wire [`FML_BE_RNG]  fml_wbe;
reg                 fml_wnext;
reg                 fml_wnext2;
wire                fml_rempty;
reg                 fml_rnext;
wire [`FML_DAT_RNG] fml_rdat;
 
ddr_ctrl #(
        .phase_shift(  phase_shift  ),
        .clk_multiply( clk_multiply ),
        .clk_divide(   clk_divide   ),
        .wait200_init( wait200_init )
) ctrl0 (
        .clk(          clk         ),
        .reset(        reset       ),
        // DDR Ports
        .ddr_clk(      ddr_clk     ),
        .ddr_clk_n(    ddr_clk_n   ),
        .ddr_clk_fb(   ddr_clk_fb  ),
        .ddr_ras_n(    ddr_ras_n   ),
        .ddr_cas_n(    ddr_cas_n   ),
        .ddr_we_n(     ddr_we_n    ),
        .ddr_cke(      ddr_cke     ),
        .ddr_cs_n(     ddr_cs_n    ),
        .ddr_a(        ddr_a       ),
        .ddr_ba(       ddr_ba      ),
        .ddr_dq(       ddr_dq      ),
        .ddr_dqs(      ddr_dqs     ),
        .ddr_dm(       ddr_dm      ),
        // FML (FastMemoryLink)
        .fml_rd(       fml_rd      ),
        .fml_wr(       fml_wr      ),
        .fml_done(     fml_done    ),
        .fml_adr(      fml_adr     ),
        .fml_wdat(     fml_wdat    ),
        .fml_wbe(      fml_wbe     ),
        .fml_wnext(    fml_wnext2  ),
        .fml_rempty(   fml_rempty  ),
        .fml_rdat(     fml_rdat    ),
        .fml_rnext(    fml_rnext   ),
        // DCM phase shift control
        .ps_ready(     ps_ready   ),
        .ps_up(        ps_up      ),
        .ps_down(      ps_down    )
);
 
assign fml_adr = { ls_adr_tag, ls_adr_set };
 
assign fml_wdat  = (ls_way) ? ls_way1_load[`WAY_DAT_RNG] :
                              ls_way0_load[`WAY_DAT_RNG];
 
assign fml_wbe   = (ls_way) ? ls_way1_load[`WAY_VALID_RNG] :
                              ls_way0_load[`WAY_VALID_RNG];
 
assign ls_tag_adr    = { ls_adr_set };
assign ls_wayX_adr   = { ls_adr_set, ls_adr_word };
assign ls_way0_we    = ls_wayX_we & ~ls_way;
assign ls_way1_we    = ls_wayX_we &  ls_way;
 
assign ls_wayX_store[`WAY_DAT_RNG]   = fml_rdat;
assign ls_wayX_store[`WAY_VALID_RNG] = 4'b1111;
 
 
//----------------------------------------------------------------------------
// LS (Load and Store) Engine
//----------------------------------------------------------------------------
parameter l_idle     = 0;
parameter l_fill     = 1;
parameter l_spill    = 2;
parameter l_waitdone = 3;
 
reg [2:0] ls_state;
assign ls_busy = (ls_state != l_idle) || ls_fill || ls_spill;
 
// Syncronous part FSM
always @(posedge clk)
begin
        if (reset) begin
                ls_state     <= l_idle;
                ls_adr_word  <= 0;
                fml_wr       <= 0;
                fml_rd       <= 0;
        end else begin
                fml_wnext2 <= fml_wnext;
 
                case (ls_state)
                l_idle: begin
                        ls_adr_word <= 0;
 
                        if (ls_spill) begin
                                ls_state    <= l_spill;
                                ls_adr_word <= ls_adr_word + 1;
                        end
                        if (ls_fill) begin
                                ls_state    <= l_fill;
                                fml_rd      <= 1;
                        end
                end
                l_spill: begin
                        ls_adr_word <= ls_adr_word + 1;
 
                        if (ls_adr_word == 3) begin
                                ls_state    <= l_waitdone;
                                fml_wr      <= 1;
                        end
                end
                l_waitdone: begin
                        ls_adr_word <= 0;
 
                        if (fml_done) begin
                                ls_state    <= l_idle;
                                fml_wr      <= 0;
                        end
                end
                l_fill: begin
                        if (fml_done)
                                fml_rd <= 0;
 
                        if (~fml_rempty)
                                ls_adr_word <= ls_adr_word + 1;
 
                        if (~fml_rempty & (ls_adr_word == 3))
                                ls_state    <= l_idle;
                end
                endcase
        end
end
 
always @(*)
begin
        fml_wnext      <= 0;
        fml_rnext      <= 0;
        ls_tag_we      <= 0;
        ls_tag_store   <= ls_tag_load;
        ls_wayX_we     <= 0;
 
        case (ls_state)
        l_idle: begin
                if (ls_spill) begin
                        fml_wnext  <= 1;
                end
        end
        l_spill: begin
                fml_wnext      <= 1;
        end
        l_waitdone: begin
                if (ls_way == 0)
                        ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
                else
                        ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
 
                if (fml_done)
                        ls_tag_we    <= 1;
        end
        l_fill: begin
                if (ls_way == 0) begin
                        ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
                        ls_tag_store[`TAG_LINE_TAG0_RNG]   <= ls_adr_tag;
                end else begin
                        ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
                        ls_tag_store[`TAG_LINE_TAG1_RNG]   <= ls_adr_tag;
                end
 
                if (~fml_rempty) begin
                        ls_wayX_we  <= 1;
                        fml_rnext   <= 1;
                end
 
                if (~fml_rempty & (ls_adr_word == 3))
                        ls_tag_we   <= 1;
        end
        endcase
end
 
always @(posedge clk)
begin
        if (ls_fill)
                $display ("At time %t WB_DDR fill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);
 
        if (ls_spill)
                $display ("At time %t WB_DDR spill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);
end
 
endmodule

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[/] [vg_z80_sbc/] [trunk/] [rtl/] [wb_ddr.v] - Blame information for rev 35

Line No.	Rev	Author	Line
1	3	hharte	`//----------------------------------------------------------------------------`
2			`// Wishbone DDR Controller`
3			`//`
4			`// (c) Joerg Bornschein (<jb@capsec.org>)`
5			`//----------------------------------------------------------------------------`
6
7			`include "ddr_include.v"
8
9			`module wb_ddr`
10			`#(`
11	20	hharte	`parameter clk_freq = 100000000,`
12	3	hharte	`parameter clk_multiply = 12,`
13			`parameter clk_divide = 5,`
14	20	hharte	`parameter phase_shift = 0,`
15	3	hharte	`parameter wait200_init = 26`
16			`) (`
17	20	hharte	`input clk,`
18			`input reset,`
19	3	hharte	`// DDR ports`
20	20	hharte	`output [2:0] ddr_clk,`
21			`output [2:0] ddr_clk_n,`
22	3	hharte	`input ddr_clk_fb,`
23			`output ddr_ras_n,`
24			`output ddr_cas_n,`
25			`output ddr_we_n,`
26	20	hharte	`output [1:0] ddr_cke,`
27			`output [1:0] ddr_cs_n,`
28	3	hharte	output [ `A_RNG] ddr_a,
29			output [ `BA_RNG] ddr_ba,
30			inout [ `DQ_RNG] ddr_dq,
31			inout [`DQS_RNG] ddr_dqs,
32			output [ `DM_RNG] ddr_dm,
33			`// Wishbone Slave Interface`
34			input [`WB_ADR_RNG] wb_adr_i,
35			input [`WB_DAT_RNG] wb_dat_i,
36			output reg [`WB_DAT_RNG] wb_dat_o,
37			input [`WB_SEL_RNG] wb_sel_i,
38			`input wb_cyc_i,`
39			`input wb_stb_i,`
40			`input wb_we_i,`
41	20	hharte	`output reg wb_ack_o,`
42			`// XXX Temporary DCM control input XXX`
43			`output ps_ready,`
44			`input ps_up,`
45			`input ps_down,`
46			`// XXX probe wires XXX`
47			`output probe_clk,`
48			`input [7:0] probe_sel,`
49			`output reg [7:0] probe`
50	3	hharte	`);`
51
52			`//----------------------------------------------------------------------------`
53			`// Wishbone handling`
54			`//----------------------------------------------------------------------------`
55			`wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;`
56			`wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i;`
57
58			wire [`WB_WORD_RNG] wb_adr_word = wb_adr_i[`WB_WORD_RNG]; // word in bufferline
59			wire [`WB_SET_RNG] wb_adr_set = wb_adr_i[`WB_SET_RNG]; // index into wayX_ram
60			wire [`WB_TAG_RNG] wb_adr_tag = wb_adr_i[`WB_TAG_RNG]; // more significant bits
61
62			`//----------------------------------------------------------------------------`
63			`// TAG RAM (2-way set assioziative)`
64			`//----------------------------------------------------------------------------`
65			wire [`TAG_LINE_RNG] tag_load;
66			wire [`TAG_LINE_RNG] tag_store;
67			`wire tag_we;`
68
69			wire [`WB_TAG_RNG] tag_load_set0 = tag_load[`TAG_LINE_TAG0_RNG];
70			wire [`WB_TAG_RNG] tag_load_set1 = tag_load[`TAG_LINE_TAG1_RNG];
71			wire tag_load_dirty0 = tag_load[`TAG_LINE_DIRTY0_RNG];
72			wire tag_load_dirty1 = tag_load[`TAG_LINE_DIRTY1_RNG];
73			wire tag_load_lru = tag_load[`TAG_LINE_LRU_RNG];
74
75			reg [`WB_TAG_RNG] tag_store_set0;
76			reg [`WB_TAG_RNG] tag_store_set1;
77			`reg tag_store_dirty0;`
78			`reg tag_store_dirty1;`
79			`reg tag_store_lru;`
80
81			assign tag_store[`TAG_LINE_TAG0_RNG] = tag_store_set0;
82			assign tag_store[`TAG_LINE_TAG1_RNG] = tag_store_set1;
83			assign tag_store[`TAG_LINE_DIRTY0_RNG] = tag_store_dirty0;
84			assign tag_store[`TAG_LINE_DIRTY1_RNG] = tag_store_dirty1;
85			assign tag_store[`TAG_LINE_LRU_RNG] = tag_store_lru;
86
87			wire [`WB_SET_RNG] ls_tag_adr;
88			wire [`TAG_LINE_RNG] ls_tag_load;
89			reg [`TAG_LINE_RNG] ls_tag_store;
90			`reg ls_tag_we;`
91
92			`dpram #(`
93			`.adr_width( 7 ),`
94			`.dat_width( 33 )`
95			`) tag_ram (`
96			`.clk ( clk ),`
97			`//`
98			`.adr0( wb_adr_set ),`
99			`.dout0( tag_load ),`
100			`.din0( tag_store ),`
101			`.we0( tag_we ),`
102			`//`
103			`.adr1( ls_tag_adr ),`
104			`.dout1( ls_tag_load ),`
105			`.din1( ls_tag_store ),`
106			`.we1( ls_tag_we )`
107			`);`
108
109			`wire tag_load_match0 = (tag_load_set0 == wb_adr_tag);`
110			`wire tag_load_match1 = (tag_load_set1 == wb_adr_tag);`
111			`wire tag_load_match = tag_load_match0 \| tag_load_match1;`
112
113			`//----------------------------------------------------------------------------`
114			`// Buffer cache ram (2 ways)`
115			`//----------------------------------------------------------------------------`
116			`wire [8:0] wayX_adr = { wb_adr_set, wb_adr_word };`
117
118			wire [`WAY_LINE_RNG] way0_load, way1_load;
119			wire [`WAY_LINE_RNG] wayX_store;
120
121			wire [31:0] way0_load_dat = way0_load[`WAY_DAT_RNG];
122			wire [31:0] way1_load_dat = way1_load[`WAY_DAT_RNG];
123			wire [3:0] way0_load_valid = way0_load[`WAY_VALID_RNG];
124			wire [3:0] way1_load_valid = way1_load[`WAY_VALID_RNG];
125
126			`wire way0_we;`
127			`wire way1_we;`
128			`reg [31:0] wayX_store_dat;`
129			`reg [3:0] wayX_store_valid;`
130
131			assign wayX_store[`WAY_DAT_RNG] = wayX_store_dat;
132			assign wayX_store[`WAY_VALID_RNG] = wayX_store_valid;
133
134			`wire [8:0] ls_wayX_adr;`
135			wire [`WAY_LINE_RNG] ls_way0_load;
136			wire [`WAY_LINE_RNG] ls_way1_load;
137			wire [`WAY_LINE_RNG] ls_wayX_store;
138			`wire ls_way0_we;`
139			`wire ls_way1_we;`
140			`reg ls_wayX_we;`
141
142			`wire way0_sel_valid = ( (~way0_load_valid & wb_sel_i) == 'b0);`
143			`wire way1_sel_valid = ( (~way1_load_valid & wb_sel_i) == 'b0);`
144			`wire wayX_sel_valid = (tag_load_match0) ? way0_sel_valid : way1_sel_valid;`
145
146			`// synthesis attribute ram_style of way0_ram is block`
147			`dpram #(`
148			`.adr_width( 9 ),`
149			`.dat_width( 36 )`
150			`) way0_ram (`
151			`.clk( clk ),`
152			`//`
153			`.adr0( wayX_adr ),`
154			`.dout0( way0_load ),`
155			`.din0( wayX_store ),`
156			`.we0( way0_we ),`
157			`//`
158			`.adr1( ls_wayX_adr ),`
159			`.dout1( ls_way0_load ),`
160			`.we1( ls_way0_we ),`
161			`.din1( ls_wayX_store )`
162			`);`
163
164			`// synthesis attribute ram_style of way1_ram is block`
165			`dpram #(`
166			`.adr_width( 9 ),`
167			`.dat_width( 36 )`
168			`) way1_ram (`
169			`.clk( clk ),`
170			`//`
171			`.adr0( wayX_adr ),`
172			`.dout0( way1_load ),`
173			`.din0( wayX_store ),`
174			`.we0( way1_we ),`
175			`//`
176			`.adr1( ls_wayX_adr ),`
177			`.dout1( ls_way1_load ),`
178			`.we1( ls_way1_we ),`
179			`.din1( ls_wayX_store )`
180			`);`
181
182			`//----------------------------------------------------------------------------`
183			`// Write/update buffer cache from wishbone side`
184			`//----------------------------------------------------------------------------`
185			`wire store_to_way0 = tag_load_lru & ~tag_load_dirty0; // store new data into way0? XXX spill_done XXX`
186			`wire store_to_way1 = ~tag_load_lru & ~tag_load_dirty1; // store new data into way1? XXX spill_done XXX`
187			`wire store_to_way = store_to_way0 \| store_to_way1;`
188
189			`reg update_lru0; //`
190			`reg update_lru1;`
191
192			`reg update_way0; //`
193			`reg update_way1;`
194
195			`assign way0_we = update_way0;`
196			`assign way1_we = update_way1;`
197			`assign tag_we = way0_we \| way1_we \| update_lru0 \| update_lru1;`
198
199			`//----------------------------------------------------------------------------`
200			`// MUX wayX_store input`
201			`//----------------------------------------------------------------------------`
202
203			`integer i;`
204			`always @(*)`
205			`begin`
206			`/*`
207			`for(i=0; i<4; i=i+1) begin`
208			`if (wb_sel_i[i]) begin`
209			`wayX_store_dat[8i+7:8i] = wb_dat_i[8i+7:8i];`
210			`wayX_store_valid[i] = 1;`
211			`end else if (update_way0) begin`
212			`wayX_store_dat[8i+7:8i] = way0_load_dat[8i+7:8i];`
213			`wayX_store_valid[i] = way0_load_valid[i];`
214			`end else begin`
215			`wayX_store_dat[8i+7:8i] = way1_load_dat[8i+7:8i];`
216			`wayX_store_valid[i] = way1_load_valid[i];`
217			`end`
218			`end`
219			`*/`
220
221			`if (wb_sel_i[0]) begin`
222			`wayX_store_dat[80+7:80] = wb_dat_i[80+7:80];`
223			`wayX_store_valid[0] = 1;`
224			`end else if (update_way0) begin`
225			`wayX_store_dat[80+7:80] = way0_load_dat[80+7:80];`
226			`wayX_store_valid[0] = way0_load_valid[0];`
227			`end else begin`
228			`wayX_store_dat[80+7:80] = way1_load_dat[80+7:80];`
229			`wayX_store_valid[0] = way1_load_valid[0];`
230			`end`
231
232			`if (wb_sel_i[1]) begin`
233			`wayX_store_dat[81+7:81] = wb_dat_i[81+7:81];`
234			`wayX_store_valid[1] = 1;`
235			`end else if (update_way0) begin`
236			`wayX_store_dat[81+7:81] = way0_load_dat[81+7:81];`
237			`wayX_store_valid[1] = way0_load_valid[1];`
238			`end else begin`
239			`wayX_store_dat[81+7:81] = way1_load_dat[81+7:81];`
240			`wayX_store_valid[1] = way1_load_valid[1];`
241			`end`
242
243			`if (wb_sel_i[2]) begin`
244			`wayX_store_dat[82+7:82] = wb_dat_i[82+7:82];`
245			`wayX_store_valid[2] = 1;`
246			`end else if (update_way0) begin`
247			`wayX_store_dat[82+7:82] = way0_load_dat[82+7:82];`
248			`wayX_store_valid[2] = way0_load_valid[2];`
249			`end else begin`
250			`wayX_store_dat[82+7:82] = way1_load_dat[82+7:82];`
251			`wayX_store_valid[2] = way1_load_valid[2];`
252			`end`
253
254			`if (wb_sel_i[3]) begin`
255			`wayX_store_dat[83+7:83] = wb_dat_i[83+7:83];`
256			`wayX_store_valid[3] = 1;`
257			`end else if (update_way0) begin`
258			`wayX_store_dat[83+7:83] = way0_load_dat[83+7:83];`
259			`wayX_store_valid[3] = way0_load_valid[3];`
260			`end else begin`
261			`wayX_store_dat[83+7:83] = way1_load_dat[83+7:83];`
262			`wayX_store_valid[3] = way1_load_valid[3];`
263			`end`
264			`end`
265
266			`always @(*)`
267			`begin`
268			`if (update_way0) begin`
269			`tag_store_set0 = wb_adr_tag;`
270			`tag_store_dirty0 = 1;`
271			`end else begin`
272			`tag_store_set0 = tag_load_set0;`
273			`tag_store_dirty0 = tag_load_dirty0;`
274			`end`
275
276			`if (update_way1) begin`
277			`tag_store_set1 = wb_adr_tag;`
278			`tag_store_dirty1 = 1;`
279			`end else begin`
280			`tag_store_set1 = tag_load_set1;`
281			`tag_store_dirty1 = tag_load_dirty1;`
282			`end`
283
284			`if (update_lru0)`
285			`tag_store_lru = 0;`
286			`else if (update_lru1)`
287			`tag_store_lru = 1;`
288			`else`
289			`tag_store_lru = tag_load_lru;`
290			`end`
291
292			`//----------------------------------------------------------------------------`
293			`// Wishbone FSM`
294			`//----------------------------------------------------------------------------`
295			`reg ls_fill;`
296			`reg ls_spill;`
297			`reg ls_way;`
298			`wire ls_busy;`
299
300			reg [`WB_TAG_RNG] ls_adr_tag;
301			reg [`WB_SET_RNG] ls_adr_set;
302			reg [`WB_WORD_RNG] ls_adr_word;
303
304			`reg [2:0] state;`
305
306			`parameter s_idle = 0;`
307			`parameter s_read = 1;`
308			`parameter s_rspill = 2;`
309			`parameter s_rfill = 3;`
310			`parameter s_write = 4;`
311			`parameter s_wspill = 5;`
312
313			`// Syncronous part of FSM`
314			`always @(posedge clk)`
315			`begin`
316			`if (reset) begin`
317			`state <= s_idle;`
318			`ls_spill <= 0;`
319			`ls_fill <= 0;`
320			`ls_way <= 0;`
321			`end else begin`
322			`ls_fill <= 0;`
323			`ls_spill <= 0;`
324
325			`case (state)`
326			`s_idle: begin`
327			`if (wb_rd)`
328			`state <= s_read;`
329
330			`if (wb_wr)`
331			`state <= s_write;`
332			`end`
333			`s_read: begin`
334			`if ((tag_load_match0 & way0_sel_valid) \| (tag_load_match1 & way1_sel_valid)) begin`
335			`state <= s_idle;`
336			`end else if (store_to_way & ~ls_busy) begin`
337			`state <= s_rfill;`
338			`ls_fill <= 1;`
339			`ls_way <= ~tag_load_lru;`
340			`ls_adr_tag <= wb_adr_tag;`
341			`ls_adr_set <= wb_adr_set;`
342			`end else if (~ls_busy) begin`
343			`state <= s_rspill;`
344			`ls_spill <= 1;`
345			`ls_way <= ~tag_load_lru;`
346			`ls_adr_set <= wb_adr_set;`
347			`if (tag_load_lru == 1)`
348			`ls_adr_tag <= tag_load_set0;`
349			`else`
350			`ls_adr_tag <= tag_load_set1;`
351			`end`
352			`end`
353			`s_rspill: begin`
354			`if (~ls_busy) begin`
355			`state <= s_rfill;`
356			`ls_fill <= 1;`
357			`ls_way <= ~tag_load_lru;`
358			`ls_adr_tag <= wb_adr_tag;`
359			`ls_adr_set <= wb_adr_set;`
360			`end`
361			`end`
362			`s_rfill: begin`
363			`if (tag_load_match & wayX_sel_valid)`
364			`state <= s_idle;`
365			`end`
366			`s_write: begin`
367			`if (tag_load_match \| store_to_way) begin`
368			`state <= s_idle;`
369			`end else if (~ls_busy) begin`
370			`state <= s_wspill;`
371			`ls_spill <= 1;`
372			`ls_way <= ~tag_load_lru;`
373			`ls_adr_set <= wb_adr_set;`
374			`if (tag_load_lru == 1)`
375			`ls_adr_tag <= tag_load_set0;`
376			`else`
377			`ls_adr_tag <= tag_load_set1;`
378			`end`
379			`end`
380			`s_wspill: begin`
381			`if (tag_load_match \| store_to_way) begin`
382			`state <= s_idle;`
383			`end`
384			`end`
385			`default:`
386			`state <= s_idle;`
387			`endcase`
388			`end`
389			`end`
390
391			`// Asyncronous part of FSM`
392			`always @(*)`
393			`begin`
394			`update_lru0 <= 0;`
395			`update_lru1 <= 0;`
396			`update_way0 <= 0;`
397			`update_way1 <= 0;`
398			`wb_dat_o <= 0;`
399			`wb_ack_o <= 0;`
400
401			`case (state)`
402			`s_idle: begin end`
403			`s_read: begin`
404			`if (tag_load_match0 & way0_sel_valid) begin`
405			`update_lru0 <= 1;`
406			`wb_dat_o <= way0_load_dat;`
407			`wb_ack_o <= 1;`
408			`end else if (tag_load_match1 & way1_sel_valid) begin`
409			`update_lru1 <= 1;`
410			`wb_dat_o <= way1_load_dat;`
411			`wb_ack_o <= 1;`
412			`end`
413			`end`
414			`s_write: begin`
415			`if (tag_load_match0 \| store_to_way0) begin`
416			`update_lru0 <= 1;`
417			`update_way0 <= 1;`
418			`wb_ack_o <= 1;`
419			`end else if (tag_load_match1 \| store_to_way1) begin`
420			`update_lru1 <= 1;`
421			`update_way1 <= 1;`
422			`wb_ack_o <= 1;`
423			`end`
424			`end`
425			`endcase`
426			`end`
427
428
429
430			`//----------------------------------------------------------------------------`
431			`// DDR Controller Engine (including clkgen, [rw]-path)`
432			`//----------------------------------------------------------------------------`
433			`reg fml_rd;`
434			`reg fml_wr;`
435			`wire fml_done;`
436			wire [`FML_ADR_RNG] fml_adr;
437			wire [`FML_DAT_RNG] fml_wdat;
438			wire [`FML_BE_RNG] fml_wbe;
439			`reg fml_wnext;`
440			`reg fml_wnext2;`
441			`wire fml_rempty;`
442			`reg fml_rnext;`
443			wire [`FML_DAT_RNG] fml_rdat;
444
445			`ddr_ctrl #(`
446			`.phase_shift( phase_shift ),`
447			`.clk_multiply( clk_multiply ),`
448			`.clk_divide( clk_divide ),`
449			`.wait200_init( wait200_init )`
450			`) ctrl0 (`
451			`.clk( clk ),`
452			`.reset( reset ),`
453			`// DDR Ports`
454			`.ddr_clk( ddr_clk ),`
455			`.ddr_clk_n( ddr_clk_n ),`
456			`.ddr_clk_fb( ddr_clk_fb ),`
457			`.ddr_ras_n( ddr_ras_n ),`
458			`.ddr_cas_n( ddr_cas_n ),`
459			`.ddr_we_n( ddr_we_n ),`
460			`.ddr_cke( ddr_cke ),`
461			`.ddr_cs_n( ddr_cs_n ),`
462			`.ddr_a( ddr_a ),`
463			`.ddr_ba( ddr_ba ),`
464			`.ddr_dq( ddr_dq ),`
465			`.ddr_dqs( ddr_dqs ),`
466			`.ddr_dm( ddr_dm ),`
467			`// FML (FastMemoryLink)`
468			`.fml_rd( fml_rd ),`
469			`.fml_wr( fml_wr ),`
470			`.fml_done( fml_done ),`
471			`.fml_adr( fml_adr ),`
472			`.fml_wdat( fml_wdat ),`
473			`.fml_wbe( fml_wbe ),`
474			`.fml_wnext( fml_wnext2 ),`
475			`.fml_rempty( fml_rempty ),`
476			`.fml_rdat( fml_rdat ),`
477	20	hharte	`.fml_rnext( fml_rnext ),`
478			`// DCM phase shift control`
479			`.ps_ready( ps_ready ),`
480			`.ps_up( ps_up ),`
481			`.ps_down( ps_down )`
482	3	hharte	`);`
483
484			`assign fml_adr = { ls_adr_tag, ls_adr_set };`
485
486			assign fml_wdat = (ls_way) ? ls_way1_load[`WAY_DAT_RNG] :
487			ls_way0_load[`WAY_DAT_RNG];
488
489			assign fml_wbe = (ls_way) ? ls_way1_load[`WAY_VALID_RNG] :
490			ls_way0_load[`WAY_VALID_RNG];
491
492			`assign ls_tag_adr = { ls_adr_set };`
493			`assign ls_wayX_adr = { ls_adr_set, ls_adr_word };`
494			`assign ls_way0_we = ls_wayX_we & ~ls_way;`
495			`assign ls_way1_we = ls_wayX_we & ls_way;`
496
497			assign ls_wayX_store[`WAY_DAT_RNG] = fml_rdat;
498			assign ls_wayX_store[`WAY_VALID_RNG] = 4'b1111;
499
500
501			`//----------------------------------------------------------------------------`
502			`// LS (Load and Store) Engine`
503			`//----------------------------------------------------------------------------`
504			`parameter l_idle = 0;`
505			`parameter l_fill = 1;`
506			`parameter l_spill = 2;`
507			`parameter l_waitdone = 3;`
508
509			`reg [2:0] ls_state;`
510			`assign ls_busy = (ls_state != l_idle) \|\| ls_fill \|\| ls_spill;`
511
512			`// Syncronous part FSM`
513			`always @(posedge clk)`
514			`begin`
515			`if (reset) begin`
516			`ls_state <= l_idle;`
517			`ls_adr_word <= 0;`
518			`fml_wr <= 0;`
519			`fml_rd <= 0;`
520			`end else begin`
521			`fml_wnext2 <= fml_wnext;`
522
523			`case (ls_state)`
524			`l_idle: begin`
525			`ls_adr_word <= 0;`
526
527			`if (ls_spill) begin`
528			`ls_state <= l_spill;`
529			`ls_adr_word <= ls_adr_word + 1;`
530			`end`
531			`if (ls_fill) begin`
532			`ls_state <= l_fill;`
533			`fml_rd <= 1;`
534			`end`
535			`end`
536			`l_spill: begin`
537			`ls_adr_word <= ls_adr_word + 1;`
538
539			`if (ls_adr_word == 3) begin`
540			`ls_state <= l_waitdone;`
541			`fml_wr <= 1;`
542			`end`
543			`end`
544			`l_waitdone: begin`
545			`ls_adr_word <= 0;`
546
547			`if (fml_done) begin`
548			`ls_state <= l_idle;`
549			`fml_wr <= 0;`
550			`end`
551			`end`
552			`l_fill: begin`
553			`if (fml_done)`
554			`fml_rd <= 0;`
555
556			`if (~fml_rempty)`
557			`ls_adr_word <= ls_adr_word + 1;`
558
559			`if (~fml_rempty & (ls_adr_word == 3))`
560			`ls_state <= l_idle;`
561			`end`
562			`endcase`
563			`end`
564			`end`
565
566			`always @(*)`
567			`begin`
568			`fml_wnext <= 0;`
569			`fml_rnext <= 0;`
570			`ls_tag_we <= 0;`
571			`ls_tag_store <= ls_tag_load;`
572			`ls_wayX_we <= 0;`
573
574			`case (ls_state)`
575			`l_idle: begin`
576			`if (ls_spill) begin`
577			`fml_wnext <= 1;`
578			`end`
579			`end`
580			`l_spill: begin`
581			`fml_wnext <= 1;`
582			`end`
583			`l_waitdone: begin`
584			`if (ls_way == 0)`
585			ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
586			`else`
587			ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
588
589			`if (fml_done)`
590			`ls_tag_we <= 1;`
591			`end`
592			`l_fill: begin`
593			`if (ls_way == 0) begin`
594			ls_tag_store[`TAG_LINE_DIRTY0_RNG] <= 0;
595			ls_tag_store[`TAG_LINE_TAG0_RNG] <= ls_adr_tag;
596			`end else begin`
597			ls_tag_store[`TAG_LINE_DIRTY1_RNG] <= 0;
598			ls_tag_store[`TAG_LINE_TAG1_RNG] <= ls_adr_tag;
599			`end`
600
601			`if (~fml_rempty) begin`
602			`ls_wayX_we <= 1;`
603			`fml_rnext <= 1;`
604			`end`
605
606			`if (~fml_rempty & (ls_adr_word == 3))`
607			`ls_tag_we <= 1;`
608			`end`
609			`endcase`
610			`end`
611
612			`always @(posedge clk)`
613			`begin`
614			`if (ls_fill)`
615			`$display ("At time %t WB_DDR fill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);`
616
617			`if (ls_spill)`
618			`$display ("At time %t WB_DDR spill cacheline: TAG = %h, SET = %h)", $time, ls_adr_tag, ls_adr_set);`
619			`end`
620
621			`endmodule`