1 |
4 |
hharte |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// $Id: wb_sram.v,v 1.1 2008-12-02 15:15:37 hharte Exp $ ////
|
4 |
|
|
//// wb_mmu.v - Simple Memory Mapping Unit with Wishbone ////
|
5 |
|
|
//// Slave interface for configuration. ////
|
6 |
|
|
//// ////
|
7 |
|
|
//// This file is part of the Vector Graphic Z80 SBC Project ////
|
8 |
|
|
//// http://www.opencores.org/projects/vg_z80_sbc/ ////
|
9 |
|
|
//// ////
|
10 |
|
|
//// Author: ////
|
11 |
|
|
//// - Howard M. Harte (hharte@opencores.org) ////
|
12 |
|
|
//// ////
|
13 |
|
|
//////////////////////////////////////////////////////////////////////
|
14 |
|
|
//// ////
|
15 |
|
|
//// Copyright (C) 2008 Howard M. Harte ////
|
16 |
|
|
//// ////
|
17 |
|
|
//// This source file may be used and distributed without ////
|
18 |
|
|
//// restriction provided that this copyright statement is not ////
|
19 |
|
|
//// removed from the file and that any derivative work contains ////
|
20 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
21 |
|
|
//// ////
|
22 |
|
|
//// This source file is free software; you can redistribute it ////
|
23 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
24 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
25 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
26 |
|
|
//// later version. ////
|
27 |
|
|
//// ////
|
28 |
|
|
//// This source is distributed in the hope that it will be ////
|
29 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
30 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
31 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
32 |
|
|
//// details. ////
|
33 |
|
|
//// ////
|
34 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
35 |
|
|
//// Public License along with this source; if not, download it ////
|
36 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
37 |
|
|
//// ////
|
38 |
|
|
//////////////////////////////////////////////////////////////////////
|
39 |
|
|
module wb_sram(
|
40 |
|
|
// Generic synchronous single-port RAM interface
|
41 |
|
|
clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
|
42 |
|
|
wb_stb_i, wb_cyc_i, wb_ack_o
|
43 |
|
|
);
|
44 |
|
|
|
45 |
|
|
//
|
46 |
|
|
// Default address and data buses width
|
47 |
|
|
//
|
48 |
|
|
parameter aw = 15; //number of address-bits
|
49 |
|
|
parameter dw = 32; //number of data-bits
|
50 |
|
|
|
51 |
|
|
//
|
52 |
|
|
// Generic synchronous single-port RAM interface
|
53 |
|
|
//
|
54 |
|
|
input clk_i;
|
55 |
|
|
input nrst_i;
|
56 |
|
|
input [aw-1:0] wb_adr_i;
|
57 |
|
|
output [dw-1:0] wb_dat_o;
|
58 |
|
|
input [dw-1:0] wb_dat_i;
|
59 |
|
|
input [3:0] wb_sel_i;
|
60 |
|
|
input wb_we_i;
|
61 |
|
|
input wb_stb_i;
|
62 |
|
|
input wb_cyc_i;
|
63 |
|
|
output reg wb_ack_o;
|
64 |
|
|
|
65 |
|
|
//
|
66 |
|
|
// generate wishbone register bank writes
|
67 |
|
|
wire wb_acc = wb_cyc_i & wb_stb_i; // WISHBONE access
|
68 |
|
|
wire wb_wr = wb_acc & wb_we_i; // WISHBONE write access
|
69 |
|
|
wire [3:0] xram_we;
|
70 |
|
|
|
71 |
|
|
// generate ack_o
|
72 |
|
|
always @(posedge clk_i)
|
73 |
|
|
wb_ack_o <= #1 wb_acc & !wb_ack_o;
|
74 |
|
|
|
75 |
|
|
wire [1:0] adr_low;
|
76 |
|
|
wire [7:0] sram_dat_o;
|
77 |
|
|
wire [7:0] sram_dat_i;
|
78 |
|
|
|
79 |
|
|
assign adr_low = wb_sel_i == 4'b0001 ? 2'b00 : wb_sel_i == 4'b0010 ? 2'b01 : wb_sel_i == 4'b0100 ? 2'b10 : 2'b11;
|
80 |
|
|
assign wb_dat_o = {sram_dat_o, sram_dat_o, sram_dat_o, sram_dat_o};
|
81 |
|
|
assign sram_dat_i = wb_sel_i == 4'b0001 ? wb_dat_i[7:0] : wb_sel_i == 4'b0010 ? wb_dat_i[15:8] : wb_sel_i == 4'b0100 ? wb_dat_i[23:16] : wb_dat_i[31:24];
|
82 |
|
|
|
83 |
|
|
// Instantiate the Monitor RAM (16K, initialized with Monitor ROM)
|
84 |
|
|
// synthesis attribute ram_style of font_ram is block
|
85 |
|
|
sram16k #(
|
86 |
|
|
.mem_file_name("../mon43/MON43x.mem"),
|
87 |
|
|
.adr_width(14),
|
88 |
|
|
.dat_width(8)
|
89 |
|
|
) sram16k0 (
|
90 |
|
|
.clk(clk_i),
|
91 |
|
|
.adr({wb_adr_i[13:2],adr_low}),
|
92 |
|
|
.dout(sram_dat_o),
|
93 |
|
|
.din(sram_dat_i),
|
94 |
|
|
.we(wb_wr)
|
95 |
|
|
);
|
96 |
|
|
|
97 |
|
|
endmodule
|
98 |
|
|
|
99 |
|
|
module sram16k
|
100 |
|
|
#(
|
101 |
|
|
parameter mem_file_name = "none",
|
102 |
|
|
parameter adr_width = 14,
|
103 |
|
|
parameter dat_width = 8
|
104 |
|
|
) (
|
105 |
|
|
input clk,
|
106 |
|
|
input [adr_width-1:0] adr,
|
107 |
|
|
input we,
|
108 |
|
|
input [dat_width-1:0] din,
|
109 |
|
|
output reg [dat_width-1:0] dout
|
110 |
|
|
);
|
111 |
|
|
|
112 |
|
|
parameter depth = (1 << adr_width);
|
113 |
|
|
|
114 |
|
|
// RAM Array
|
115 |
|
|
reg [dat_width-1:0] ram [0:depth-1];
|
116 |
|
|
|
117 |
|
|
always @(posedge clk)
|
118 |
|
|
begin
|
119 |
|
|
if (we)
|
120 |
|
|
ram[adr] <= din;
|
121 |
|
|
|
122 |
|
|
dout <= ram[adr];
|
123 |
|
|
end
|
124 |
|
|
|
125 |
|
|
//------------------------------------------------------------------
|
126 |
|
|
// Initialize contents of RAM from file
|
127 |
|
|
//------------------------------------------------------------------
|
128 |
|
|
integer i;
|
129 |
|
|
|
130 |
|
|
initial
|
131 |
|
|
begin
|
132 |
|
|
if (mem_file_name != "none")
|
133 |
|
|
begin
|
134 |
|
|
$readmemh(mem_file_name, ram);
|
135 |
|
|
end
|
136 |
|
|
else begin
|
137 |
|
|
for(i=0; i<depth; i=i+1)
|
138 |
|
|
ram[i] <= 'b0;
|
139 |
|
|
end
|
140 |
|
|
|
141 |
|
|
end
|
142 |
|
|
|
143 |
|
|
endmodule
|