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[/] [vg_z80_sbc/] [trunk/] [rtl/] [wb_uart.v] - Blame information for rev 3

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1 3 hharte
//---------------------------------------------------------------------------
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// Wishbone UART 
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//
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// Register Description:
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//
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//    0x00 UCR      [ 0 | 0 | 0 | tx_busy | 0 | 0 | rx_error | rx_avail ]
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//    0x04 DATA
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//
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//              0x08 COND
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//              0x0c CONS               | 0 0 0 0 0 0 | rx_avail | tx_busy |
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//
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//---------------------------------------------------------------------------
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module wb_uart #(
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        parameter          clk_freq = 50000000,
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        parameter          baud     = 115200
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) (
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        input              clk,
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        input              reset,
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        // Wishbone interface
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        input              wb_stb_i,
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        input              wb_cyc_i,
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        output             wb_ack_o,
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        input              wb_we_i,
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        input       [31:0] wb_adr_i,
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        input        [3:0] wb_sel_i,
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        input       [31:0] wb_dat_i,
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        output reg  [31:0] wb_dat_o,
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        // Serial Wires
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//      input              uart_rxd,
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//      output             uart_txd,
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        inout                                    ps2_clk,
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        inout                                    ps2_data,
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        input              uart1_rxd,
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        output             uart1_txd,
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        input              uart2_rxd,
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        output             uart2_txd,
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        input              uart3_rxd,
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        output             uart3_txd
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);
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//---------------------------------------------------------------------------
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// Actual UART engine
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//---------------------------------------------------------------------------
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wire [7:0] rx_data[0:3];
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wire       rx_avail[0:3];
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wire       rx_error[0:3];
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reg        rx_ack[0:3];
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wire [7:0] tx_data;
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reg        tx_wr[0:3];
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wire       tx_busy[0:3];
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wire    rx_extended;
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wire    rx_released;
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wire    rx_shift_key_on;
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wire    [7:0] rx_scan_code;
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wire    rx_data_ready;
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wire    tx_write_ack_o;
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wire    tx_error_no_keyboard_ack;
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// Instantiate the module
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ps2_keyboard_interface ps2_kbd (
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    .clk(clk),
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    .reset(reset),
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    .ps2_clk(ps2_clk),
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    .ps2_data(ps2_data),
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    .rx_extended(rx_extended),
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    .rx_released(rx_released),
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    .rx_shift_key_on(rx_shift_key_on),
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    .rx_scan_code(rx_scan_code),
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    .rx_ascii(rx_data[0]),
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    .rx_data_ready(rx_avail[0]),
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    .rx_read(rx_ack[0]),
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    .tx_data(tx_data),
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    .tx_write(tx_wr[0]),
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    .tx_write_ack_o(tx_write_ack_o),
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    .tx_error_no_keyboard_ack(tx_error_no_keyboard_ack)
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    );
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uart #(
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        .freq_hz(   clk_freq ),
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        .baud(      baud     )
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) uart1 (
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        .clk(       clk      ),
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        .reset(     reset    ),
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        //
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        .uart_rxd(  uart1_rxd ),
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        .uart_txd(  uart1_txd ),
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        //
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        .rx_data(   rx_data[1]  ),
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        .rx_avail(  rx_avail[1] ),
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        .rx_error(  rx_error[1] ),
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        .rx_ack(    rx_ack[1]   ),
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        .tx_data(   tx_data  ),
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        .tx_wr(     tx_wr[1]    ),
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        .tx_busy(   tx_busy[1]  )
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);
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uart #(
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        .freq_hz(   clk_freq ),
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        .baud(      baud     )
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) uart2 (
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        .clk(       clk      ),
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        .reset(     reset    ),
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        //
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        .uart_rxd(  uart2_rxd ),
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        .uart_txd(  uart2_txd ),
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        //
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        .rx_data(   rx_data[2]  ),
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        .rx_avail(  rx_avail[2] ),
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        .rx_error(  rx_error[2] ),
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        .rx_ack(    rx_ack[2]   ),
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        .tx_data(   tx_data  ),
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        .tx_wr(     tx_wr[2]    ),
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        .tx_busy(   tx_busy[2]  )
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);
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uart #(
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        .freq_hz(   clk_freq ),
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        .baud(      baud     )
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) uart3 (
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        .clk(       clk      ),
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        .reset(     reset    ),
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        //
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        .uart_rxd(  uart3_rxd ),
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        .uart_txd(  uart3_txd ),
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        //
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        .rx_data(   rx_data[3]  ),
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        .rx_avail(  rx_avail[3] ),
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        .rx_error(  rx_error[3] ),
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        .rx_ack(    rx_ack[3]   ),
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        .tx_data(   tx_data  ),
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        .tx_wr(     tx_wr[3]    ),
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        .tx_busy(   tx_busy[3]  )
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);
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//---------------------------------------------------------------------------
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// 
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//---------------------------------------------------------------------------
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wire [7:0] ucr = { wb_adr_i[4:3], 3'b0, rx_error[wb_adr_i[4:3]], rx_avail[wb_adr_i[4:3]], ~tx_busy[wb_adr_i[4:3]] };
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wire    key_ready = (~rx_released) & rx_avail[0];
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wire    [7:0] kbdsr = {1'b0, key_ready, 5'b0, ~key_ready};
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wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
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wire wb_wr = wb_stb_i & wb_cyc_i &  wb_we_i; // & wb_sel_i[0];
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reg  ack;
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assign wb_ack_o       = wb_stb_i & wb_cyc_i & ack;
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assign tx_data = wb_dat_i[7:0];
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always @(posedge clk)
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begin
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        if (reset) begin
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                wb_dat_o[31:8] <= 24'b0;
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                tx_wr[0]  <= 0;
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                rx_ack[0] <= 0;
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                tx_wr[1]  <= 0;
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                rx_ack[1] <= 0;
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                tx_wr[2]  <= 0;
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                rx_ack[2] <= 0;
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                tx_wr[3]  <= 0;
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                rx_ack[3] <= 0;
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                ack    <= 0;
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        end else begin
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                wb_dat_o[31:8] <= 24'b0;
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                tx_wr[0]  <= 0;
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                rx_ack[0] <= 0;
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                tx_wr[1]  <= 0;
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                rx_ack[1] <= 0;
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                tx_wr[2]  <= 0;
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                rx_ack[2] <= 0;
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                tx_wr[3]  <= 0;
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                rx_ack[3] <= 0;
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                ack    <= 0;
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                if (wb_rd & ~ack) begin
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                        ack <= 1;
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                        case (wb_adr_i[4:2])
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                        3'b000: begin
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                                wb_dat_o[7:0] <= kbdsr;
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                        end
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                        3'b001: begin
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                                wb_dat_o[7:0] <= rx_data[wb_adr_i[4:3]];
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                                rx_ack[wb_adr_i[4:3]]        <= 1;
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                        end
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                        3'b010: begin
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                                wb_dat_o[7:0] <= rx_data[wb_adr_i[4:3]];
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                                rx_ack[wb_adr_i[4:3]]        <= 1;
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                        end
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                        3'b011: begin
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                                wb_dat_o[7:0] <= ucr;
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                        end
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                        3'b100: begin
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                                wb_dat_o[7:0] <= rx_data[wb_adr_i[4:3]];
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                                rx_ack[wb_adr_i[4:3]]        <= 1;
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                        end
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                        3'b101: begin
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                                wb_dat_o[7:0] <= ucr;
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                        end
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                        3'b110: begin
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                                wb_dat_o[7:0] <= rx_data[wb_adr_i[4:3]];
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                                rx_ack[wb_adr_i[4:3]]        <= 1;
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                        end
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                        3'b111: begin
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                                wb_dat_o[7:0] <= ucr;
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                        end
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                        default: begin
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                                wb_dat_o[7:0] <= 8'b0;
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                        end
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                        endcase
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                end else if (wb_wr & ~ack ) begin
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                        ack <= 1;
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                        if ((wb_adr_i[2] == 2'b0) && ~tx_busy[wb_adr_i[4:3]]) begin
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                                tx_wr[wb_adr_i[4:3]] <= 1;
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                        end
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                end
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        end
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end
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endmodule

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