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[/] [vg_z80_sbc/] [trunk/] [rtl/] [wb_uart.v] - Blame information for rev 36

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1 3 hharte 
//---------------------------------------------------------------------------
2 27 hharte 
// Wishbone UARTs / PS/2 ASCII Keyboard Top-Level
3 3 hharte 
//
4 27 hharte 
// Register Description:
5 
//
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// KB 0x01 STATUS    [ 0 |kry| 0 | 0 | 0 | 0  | 0   |          | ~key_rdy ]
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// KB 0x01 DATA      [                  KEYBOARD DATA                     ]
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// U1 0x02 COND      [                       DATA                         ]
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// U1 0x03 CONS      [ 0 | 0 | 0 | 0 | 0 | rx_error | rx_avail | tx_ready ]
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// U2 0x04 COND      [                       DATA                         ]
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// U2 0x05 CONS      [ 0 | 0 | 0 | 0 | 0 | rx_error | rx_avail | tx_ready ]
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// U3 0x06 COND      [                       DATA                         ]
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// U3 0x07 CONS      [ 0 | 0 | 0 | 0 | 0 | rx_error | rx_avail | tx_ready ]
14 3 hharte 
//
15 
//---------------------------------------------------------------------------
16 
 
17 
module wb_uart #(
18 22 hharte 
        parameter          clk_freq = 25000000,
19 3 hharte 
        parameter          baud     = 115200
20 
) (
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        input              clk,
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        input              reset,
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        // Wishbone interface
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        input              wb_stb_i,
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        input              wb_cyc_i,
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        output             wb_ack_o,
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        input              wb_we_i,
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        input       [31:0] wb_adr_i,
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        input        [3:0] wb_sel_i,
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        input       [31:0] wb_dat_i,
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        output reg  [31:0] wb_dat_o,
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        // Serial Wires
33 22 hharte 
        inout              ps2_clk,
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        inout              ps2_data,
35 3 hharte 
        input              uart1_rxd,
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        output             uart1_txd,
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        input              uart2_rxd,
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        output             uart2_txd,
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        input              uart3_rxd,
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        output             uart3_txd
41 
);
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43 
//---------------------------------------------------------------------------
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// Actual UART engine
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//---------------------------------------------------------------------------
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wire [7:0] rx_data[0:3];
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wire       rx_avail[0:3];
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wire       rx_error[0:3];
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reg        rx_ack[0:3];
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wire [7:0] tx_data;
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reg        tx_wr[0:3];
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wire       tx_busy[0:3];
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54 
 
55 
wire    rx_extended;
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wire    rx_released;
57 27 hharte 
wire    rx_shift_key_on;
58 22 hharte 
wire    rx_ctrl_key_on;
59 3 hharte 
wire    [7:0] rx_scan_code;
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wire    rx_data_ready;
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wire    tx_write_ack_o;
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wire    tx_error_no_keyboard_ack;
63 
 
64 
// Instantiate the module
65 22 hharte 
ps2_keyboard_interface #(
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    .TRAP_SHIFT_KEYS_PP(1)
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) ps2_kbd (
68 3 hharte 
    .clk(clk),
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    .reset(reset),
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    .ps2_clk(ps2_clk),
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    .ps2_data(ps2_data),
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    .rx_extended(rx_extended),
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    .rx_released(rx_released),
74 27 hharte 
    .rx_shift_key_on(rx_shift_key_on),
75 22 hharte 
    .rx_ctrl_key_on(rx_ctrl_key_on),
76 3 hharte 
    .rx_scan_code(rx_scan_code),
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    .rx_ascii(rx_data[0]),
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    .rx_data_ready(rx_avail[0]),
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    .rx_read(rx_ack[0]),
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    .tx_data(tx_data),
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    .tx_write(tx_wr[0]),
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    .tx_write_ack_o(tx_write_ack_o),
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    .tx_error_no_keyboard_ack(tx_error_no_keyboard_ack)
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    );
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86 
uart #(
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        .freq_hz(   clk_freq ),
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        .baud(      baud     )
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) uart1 (
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        .clk(       clk      ),
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        .reset(     reset    ),
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        //
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        .uart_rxd(  uart1_rxd ),
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        .uart_txd(  uart1_txd ),
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        //
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        .rx_data(   rx_data[1]  ),
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        .rx_avail(  rx_avail[1] ),
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        .rx_error(  rx_error[1] ),
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        .rx_ack(    rx_ack[1]   ),
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        .tx_data(   tx_data  ),
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        .tx_wr(     tx_wr[1]    ),
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        .tx_busy(   tx_busy[1]  )
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);
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uart #(
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        .freq_hz(   clk_freq ),
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        .baud(      baud     )
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) uart2 (
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        .clk(       clk      ),
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        .reset(     reset    ),
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        //
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        .uart_rxd(  uart2_rxd ),
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        .uart_txd(  uart2_txd ),
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        //
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        .rx_data(   rx_data[2]  ),
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        .rx_avail(  rx_avail[2] ),
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        .rx_error(  rx_error[2] ),
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        .rx_ack(    rx_ack[2]   ),
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        .tx_data(   tx_data  ),
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        .tx_wr(     tx_wr[2]    ),
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        .tx_busy(   tx_busy[2]  )
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);
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uart #(
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        .freq_hz(   clk_freq ),
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        .baud(      baud     )
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) uart3 (
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        .clk(       clk      ),
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        .reset(     reset    ),
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        //
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        .uart_rxd(  uart3_rxd ),
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        .uart_txd(  uart3_txd ),
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        //
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        .rx_data(   rx_data[3]  ),
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        .rx_avail(  rx_avail[3] ),
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        .rx_error(  rx_error[3] ),
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        .rx_ack(    rx_ack[3]   ),
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        .tx_data(   tx_data  ),
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        .tx_wr(     tx_wr[3]    ),
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        .tx_busy(   tx_busy[3]  )
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);
142 
 
143 
//---------------------------------------------------------------------------
144 
//
145 
//---------------------------------------------------------------------------
146 22 hharte 
wire    [1:0] sel_port = wb_adr_i[2:1];
147 3 hharte 
 
148 22 hharte 
wire [7:0] ucr = { 5'b0, rx_error[sel_port], rx_avail[sel_port], ~tx_busy[sel_port] };
149 
 
150 3 hharte 
wire    key_ready = (~rx_released) & rx_avail[0];
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wire    [7:0] kbdsr = {1'b0, key_ready, 5'b0, ~key_ready};
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153 
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
154 22 hharte 
wire wb_wr = wb_stb_i & wb_cyc_i &  wb_we_i;
155 3 hharte 
 
156 
reg  ack;
157 
 
158 
assign wb_ack_o       = wb_stb_i & wb_cyc_i & ack;
159 
 
160 
assign tx_data = wb_dat_i[7:0];
161 
 
162 
always @(posedge clk)
163 
begin
164 
        if (reset) begin
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                wb_dat_o[31:8] <= 24'b0;
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                tx_wr[0]  <= 0;
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                rx_ack[0] <= 0;
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                tx_wr[1]  <= 0;
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                rx_ack[1] <= 0;
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                tx_wr[2]  <= 0;
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                rx_ack[2] <= 0;
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                tx_wr[3]  <= 0;
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                rx_ack[3] <= 0;
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                ack    <= 0;
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        end else begin
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                wb_dat_o[31:8] <= 24'b0;
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                tx_wr[0]  <= 0;
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                rx_ack[0] <= 0;
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                tx_wr[1]  <= 0;
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                rx_ack[1] <= 0;
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                tx_wr[2]  <= 0;
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                rx_ack[2] <= 0;
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                tx_wr[3]  <= 0;
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                rx_ack[3] <= 0;
185 
                ack    <= 0;
186 
 
187 
                if (wb_rd & ~ack) begin
188 
                        ack <= 1;
189 
 
190 10 hharte 
                        case (wb_adr_i[2:0])
191 3 hharte 
                        3'b000: begin
192 
                                wb_dat_o[7:0] <= kbdsr;
193 
                        end
194 
                        3'b001: begin
195 27 hharte 
                                if(rx_ctrl_key_on) begin
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                    wb_dat_o[7:0] <= { 2'b00, rx_data[sel_port][5:0] };
197 
                end else begin
198 
                    wb_dat_o[7:0] <= rx_data[sel_port];
199 22 hharte 
                end
200 
                                rx_ack[sel_port]        <= 1;
201 3 hharte 
                        end
202 
                        3'b010: begin
203 22 hharte 
                                wb_dat_o[7:0] <= rx_data[sel_port];
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                                rx_ack[sel_port]        <= 1;
205 3 hharte 
                        end
206 
                        3'b011: begin
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                                wb_dat_o[7:0] <= ucr;
208 
                        end
209 
                        3'b100: begin
210 22 hharte 
                                wb_dat_o[7:0] <= rx_data[sel_port];
211 
                                rx_ack[sel_port]        <= 1;
212 3 hharte 
                        end
213 
                        3'b101: begin
214 
                                wb_dat_o[7:0] <= ucr;
215 
                        end
216 
                        3'b110: begin
217 22 hharte 
                                wb_dat_o[7:0] <= rx_data[sel_port];
218 
                                rx_ack[sel_port]        <= 1;
219 3 hharte 
                        end
220 
                        3'b111: begin
221 
                                wb_dat_o[7:0] <= ucr;
222 
                        end
223 
 
224 
                        default: begin
225 
                                wb_dat_o[7:0] <= 8'b0;
226 
                        end
227 
                        endcase
228 
                end else if (wb_wr & ~ack ) begin
229 
                        ack <= 1;
230 
 
231 22 hharte 
                        if ((wb_adr_i[0] == 1'b0) && ~tx_busy[sel_port]) begin
232 
                                tx_wr[sel_port] <= 1;
233 3 hharte 
                        end
234 
                end
235 
        end
236 
end
237 
 
238 
 
239 
endmodule

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