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hharte |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// wb_vga.v - Wishbone wrapper and Video/Font RAM. ////
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//// ////
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//// This file is part of the Text-Mode VGA Controller Project ////
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//// http://www.opencores.org/projects/ ////
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//// ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// This controller occupies 16K of address space: ////
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//// ////
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//// 0000-0FFF - Video RAM (Character storage) ////
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//// 1000-1FFF - Font RAM (Font storage) ////
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//// 2000-2FFF - VGA Controller Registers ////
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//// 2000 - VGA OCTL ////
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//// [7] - 1=Video enable / 0=disable ////
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//// [6] - 1=Cursor enable / 0=disable ////
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//// [5] - 1=Cursor blink / 0=solid ////
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//// [4] - 1=Cursor Mode ////
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//// [2:0] - R/G/B Color Enables ////
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//// 2001 - VGA OCTL2 (unused) ////
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//// 2002 - VGA OCRX Cursor X Position ////
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//// 2003 - VGA OCRY Cursor Y Position ////
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//// 3000-3FFF - Unused ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module wb_vga(
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// VGA Interface
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clk_i, clk_50mhz_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
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wb_stb_i, wb_cyc_i, wb_ack_o,
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vga_hsync_o, vga_vsync_o, vga_r_o, vga_g_o, vga_b_o
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);
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parameter font_file_name = "fwii_8x10.ram"; // Font filename (must contain exactly 4K of data)
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parameter font_height = 10; // Number of pixels in font height
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parameter text_height = 2; // 1=80x48, 2=80x24
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//
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// Wishbone Wrapper for Text-Mode VGA Controller
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//
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input clk_i;
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input clk_50mhz_i;
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input nrst_i;
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input [13:0] wb_adr_i;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_cyc_i;
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output reg wb_ack_o;
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output vga_hsync_o;
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output vga_vsync_o;
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output vga_r_o;
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output vga_g_o;
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output vga_b_o;
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wire [7:0] vga_dat;
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wire [11:0] vga_adr;
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reg [7:0] vga_regs[0:3];
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wire [7:0] octl = vga_regs[0]; // 7=vga_en, 6=cursor_en, 2:0=color
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wire [7:0] octl2 = vga_regs[1]; // unused for now
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wire [7:0] ocrx = vga_regs[2];
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wire [7:0] ocry = vga_regs[3];
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wire [11:0] font_a;
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wire [7:0] font_d;
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wire [1:0] adr_low;
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wire [7:0] dpram_dat_o;
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wire [7:0] dpram_dat_i;
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reg clk25mhz;
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wire vga_clk = clk25mhz;
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wire video_ram_acc = wb_adr_i[13:12] == 2'b00;
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wire font_ram_acc = wb_adr_i[13:12] == 2'b01;
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wire vga_regs_acc = wb_adr_i[13:12] == 2'b10;
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wire [7:0] font_dat_o;
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wire [7:0] reg_dat_o;
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//
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// generate wishbone register bank writes
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wire wb_acc = wb_cyc_i & wb_stb_i; // WISHBONE access
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wire wb_wr = wb_acc & wb_we_i; // WISHBONE write access
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wire wb_rd = wb_acc & ~wb_we_i; // WISHBONE read access
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wire vga_ram_wr = wb_wr & video_ram_acc;
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wire font_ram_wr = wb_wr & font_ram_acc;
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wire vga_reg_wr = wb_wr & vga_regs_acc;
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// generate ack_o
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always @(posedge clk_i)
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wb_ack_o <= #1 wb_acc & !wb_ack_o;
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assign adr_low = wb_sel_i == 4'b0001 ? 2'b00 : wb_sel_i == 4'b0010 ? 2'b01 : wb_sel_i == 4'b0100 ? 2'b10 : 2'b11;
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assign wb_dat_o = video_ram_acc ? {dpram_dat_o, dpram_dat_o, dpram_dat_o, dpram_dat_o} :
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font_ram_acc ? {font_dat_o, font_dat_o, font_dat_o, font_dat_o} :
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{reg_dat_o, reg_dat_o, reg_dat_o, reg_dat_o};
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assign dpram_dat_i = wb_sel_i == 4'b0001 ? wb_dat_i[7:0] : wb_sel_i == 4'b0010 ? wb_dat_i[15:8] : wb_sel_i == 4'b0100 ? wb_dat_i[23:16] : wb_dat_i[31:24];
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always @(posedge clk_i or negedge nrst_i)
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if (~nrst_i) // reset registers
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begin
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vga_regs[0] <= 8'b10110111; // 7=vga_en, 6=cursor_en, 2:0=color
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vga_regs[1] <= 8'b00000000; // 0xA5
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vga_regs[2] <= 8'b00000000;
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vga_regs[3] <= 8'b00000000;
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end
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else if(vga_reg_wr) // wishbone write cycle
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vga_regs[adr_low] <= dpram_dat_i;
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assign reg_dat_o = vga_regs[adr_low];
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// Instantiate the VGA module
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vga80x40 # (
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.font_height(font_height),
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.text_height(text_height))
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vga_controller (
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.reset(~nrst_i),
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.clk25MHz(vga_clk),
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.TEXT_A(vga_adr),
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.TEXT_D(vga_dat),
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.FONT_A(font_a),
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.FONT_D(font_d),
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.ocrx(ocrx),
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.ocry(ocry),
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.octl(octl),
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.R(vga_r_o),
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.G(vga_g_o),
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.B(vga_b_o),
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.hsync(vga_hsync_o),
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.vsync(vga_vsync_o)
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);
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// Instantiate the Video RAM (4K)
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// synthesis attribute ram_style of video_ram is block
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vga_dpram #(
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.mem_file_name("none"),
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.adr_width(12),
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.dat_width(8)
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) video_ram (
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.clk1(clk_i),
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.clk2(vga_clk),
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//
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.adr0({wb_adr_i[11:2], adr_low}),
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.dout0(dpram_dat_o),
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.din0(dpram_dat_i),
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.we0(vga_ram_wr),
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//
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.adr1(vga_adr),
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.dout1(vga_dat),
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.din1(8'b0),
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.we1(1'b0)
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);
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// Instantiate the Font RAM (4K, initialized with font data)
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// synthesis attribute ram_style of font_ram is block
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vga_dpram #(
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.mem_file_name(font_file_name),
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.adr_width(12),
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.dat_width(8)
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) font_ram (
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.clk1(clk_i),
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.clk2(vga_clk),
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//
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.adr0({wb_adr_i[11:2], adr_low} ),
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.dout0(font_dat_o),
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.din0(dpram_dat_i),
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.we0(font_ram_wr),
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//
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.adr1(font_a),
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.dout1(font_d),
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.din1(8'b0),
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.we1(1'b0)
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);
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// Generate 25MHz Pixel Clock
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always @(posedge clk_50mhz_i or negedge nrst_i)
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if (~nrst_i)
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begin
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clk25mhz <= 1'b0;
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end else begin
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clk25mhz <= !clk25mhz;
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end
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endmodule
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