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///////////////////////////////////////////////////////////////////////////////////////////////
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////
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//// file name: z80_core_top.v
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//// description: interconnect module for z80 core.
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//// project: wb_z80 ////
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////
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//// Author: B.J. Porcella
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//// bporcella@sbcglobal.net
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////
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////
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////
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///////////////////////////////////////////////////////////////////////////////////////////////
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////
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//// Copyright (C) 2000-2002 B.J. Porcella
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//// Real Time Solutions
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////
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////
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//// This source file may be used and distributed without
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//// restriction provided that this copyright statement is not
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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//// POSSIBILITY OF SUCH DAMAGE.
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////
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///////////////////////////////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: z80_core_top.v,v 1.1 2008-12-01 02:00:10 hharte Exp $
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//
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// $Date: 2008-12-01 02:00:10 $
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// $Revision: 1.1 $
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// $Author: hharte $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2004/05/27 14:23:36 bporcella
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// Instruction test (with interrupts) runs!!!
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//
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// Revision 1.5 2004/05/21 02:51:25 bporcella
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// inst test got to the worked macro
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//
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// Revision 1.4 2004/05/18 22:31:21 bporcella
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// instruction test getting to final stages
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//
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// Revision 1.3 2004/05/13 14:58:53 bporcella
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// testbed built and verification in progress
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//
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// Revision 1.2 2004/04/27 21:38:22 bporcella
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// test lint on core
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//
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// Revision 1.1 2004/04/27 21:27:13 bporcella
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// first core build
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//
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// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
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// import first files
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//
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//
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//
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// connects modules:
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// z80_memstate2.v main state machine for z8 pc - sp and wishbone regiters
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// z80_inst_exec.v main execution engine for z80 general programming registers - alu's
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// z80_sram.v main memory (on board)
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// z80_bist_logic.v memory initialization and some simple test peripherals.
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//
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// WARNING be sure the "test peripherals" in the bist_logic do not interfere with your
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// system.
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//
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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module z80_core_top(
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wb_dat_o,
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wb_stb_o,
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wb_cyc_o,
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wb_we_o,
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wb_adr_o,
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wb_tga_o,
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wb_ack_i,
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wb_clk_i,
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wb_dat_i,
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wb_rst_i,
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`ifdef COMPILE_BIST
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bist_ack_o,
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bist_err_o,
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bist_req_i,
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`endif
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int_req_i
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);
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//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
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output [7:0] wb_dat_o;
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output wb_stb_o;
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output wb_cyc_o;
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output wb_we_o;
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output [15:0] wb_adr_o;
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output [1:0] wb_tga_o;
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//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
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input wb_ack_i;
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input wb_clk_i;
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input [7:0] wb_dat_i;
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input wb_rst_i;
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input int_req_i;
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`ifdef COMPILE_BIST
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output bist_err_o;
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output bist_ack_o;
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input bist_req_i;
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`endif
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//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0
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wire [15:0] wb_adr_o;
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wire [9:0] ir1, ir2;
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wire [15:0] nn;
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wire [15:0] sp;
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wire [7:0] ar, fr, br, cr, dr, er, hr, lr, intr;
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wire [15:0] ixr, iyr;
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wire [7:0] wb_dat_i, wb_dat_o, sdram_do, cfg_do, bist_do;
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wire [15:0] add16; // ir2 execution engine output for sp updates
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wire [15:0] adr_alu; // address alu to inst to update hl and de on block moves
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wire [7:0] alu8_out, sh_alu, bit_alu; // gotta move these to data out register
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// for memory operations.
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wire sram_addr;
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wire ce_sram;
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wire [7:0] wb_rd_dat;
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wire wb_ack;
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//-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
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//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
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`ifdef COMPILE_BIST
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wire [7:0] bist_dat_o;
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wire bist_io_ack;
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z80_bist_logic i_z80_bist_logic(
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.bist_err_o(bist_err_o),
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.bist_ack_o(bist_ack_o),
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.wb_dat_o(bist_dat_o),
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.wb_ack_o(bist_io_ack),
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.int_req_o(bist_int_req),
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.wb_adr_i(wb_adr_o),
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.wb_dat_i(wb_dat_o),
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.wb_we_i(wb_we_o),
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.wb_cyc_i(wb_cyc_o),
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.wb_stb_i(wb_stb_o),
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.wb_tga_i(wb_tga_o),
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.int_req_i(int_req_i),
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i)
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);
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`else
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wire bist_io_ack = 1'b0;
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wire [7:0] bist_dat_o = 8'b0;
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`endif
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z80_memstate2 i_z80_memstate2(
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.wb_adr_o(wb_adr_o), .wb_we_o(wb_we_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_tga_o(wb_tga_o), .wb_dat_o(wb_dat_o),
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.exec_ir2(exec_ir2),
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.exec_decbc(exec_decbc), .exec_decb(exec_decb),
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.ir1(ir1), .ir2(ir2), .ir1dd(ir1dd), .ir1fd(ir1fd), .ir2dd(ir2dd), .ir2fd(ir2fd), .nn(nn), .sp(sp),
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.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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.beq0(br_eq0), .ceq0(cr_eq0),
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.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr),
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.ixr(ixr), .iyr(iyr), .intr(intr),
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.wb_dat_i(wb_rd_dat), .wb_ack_i(wb_ack),
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.int_req_i(bist_int_req),
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.add16(add16),
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.alu8_out(alu8_out),
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.adr_alu(adr_alu),
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.blk_mv_upd_hl(blk_mv_upd_hl),
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.blk_mv_upd_de(blk_mv_upd_de),
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.sh_alu(sh_alu),
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.bit_alu(bit_alu),
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.wb_clk_i(wb_clk_i),
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.rst_i(wb_rst_i) // keep this generic - may turn out to be different from wb_rst
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);
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z80_inst_exec i_z80_inst_exec(
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.br_eq0(br_eq0),
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.cr_eq0(cr_eq0),
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.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr), .intr(intr),
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.ixr(ixr), .iyr(iyr), .add16(add16), .alu8_out(alu8_out),
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.adr_alu(adr_alu),
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.blk_mv_upd_hl(blk_mv_upd_hl),
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.blk_mv_upd_de(blk_mv_upd_de),
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.sh_alu(sh_alu),
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.bit_alu(bit_alu),
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.exec_ir2(exec_ir2),
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.exec_decbc(exec_decbc), .exec_decb(exec_decb),
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.ir2(ir2),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.nn(nn), .sp(sp),
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.ir2dd(ir2dd),
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.ir2fd(ir2fd)
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);
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//------------------- routing logic for the wishbone ------------------------
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//
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// I guess purists would prefer this logic in a lower module --- "no logic on top level"
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// Somehow I tend to think that this is the kind of logic that belongs on the top
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// level.
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assign sram_addr = 1'b0; //= ~wb_adr_o[15] & (wb_tga_o == 2'b00);
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assign ce_sram = sram_addr & wb_cyc_o & wb_stb_o;
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assign wb_rd_dat = sram_addr ? sdram_do :
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bist_io_ack ? bist_dat_o :
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wb_dat_i;
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assign wb_ack = ce_sram | bist_io_ack | wb_ack_i;
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//z80_sram #(11) i_z80_sram(
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// // Generic synchronous single-port RAM interface
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// .clk(wb_clk_i), .rst(wb_rst_i), .ce(ce_sram), .we(wb_we_o), .oe(1'b1),
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// .addr(wb_adr_o[14:0]), .di(wb_dat_o), .do(sdram_do)
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// );
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endmodule
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