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//                                                                                               //

//  file name:   inst_exec.v                                                                     //

//  description: main execution engine for wishbone z80                                          //

//  project:     wb_z80                                                                          //

//                                                                                               //

//  Author: B.J. Porcella                                                                        //

//  e-mail: bporcella@sbcglobal.net                                                              //

//                                                                                               //

//                                                                                               //

//                                                                                               //

///////////////////////////////////////////////////////////////////////////////////////////////////

//                                                                                               //

// Copyright (C) 2000-2002 B.J. Porcella                                                         //

//                         Real Time Solutions                                                   //

//                                                                                               //

//                                                                                               //

// This source file may be used and distributed without                                          //

// restriction provided that this copyright statement is not                                     //

// removed from the file and that any derivative work contains                                   //

// the original copyright notice and the associated disclaimer.                                  //

//                                                                                               //

//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY                                       //

// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED                                     //

// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS                                     //

// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR                                        //

// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,                                           //

// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES                                      //

// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE                                     //

// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR                                          //

// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF                                    //

// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT                                    //

// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT                                    //

// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE                                           //

// POSSIBILITY OF SUCH DAMAGE.                                                                   //

//                                                                                               //

//-------1---------2---------3--------Comments on file  -------------7---------8---------9--------0

//

// This file contains the data related registers of the z80 and the

// logic required to update them.  Included registers are:

//  ar   fr

//  br   cr

//  dr   er

//  hr   lr

//    ixr

//    iyr

//  intr

//

//  and the "prime" registers

//  ap  fp

//  bp  cp

//  dp  ep

//  hp  lp

//

// This logic can be considered a "slave" to the memstate sequencer (in memstate2.v).  

// as memstate sequencer executes any instruction from ir1 (the of - os pipe) the instruction

// gets transferred to ir2 - which now becomes active.  

//

// In the case of any memory type instruction (HL) , the pipeline must stall 1 tick to get the

// operand into the nn register.  This file logic needs not understand any of that --  just 

// execute when told to (ir2_val).

//

// From a block diagram standpoint this file is somewhat messy.  There are multiple ALU's and 

// multiple source multiplexors.  Part of the reason for this is hardware speed  -  the 

// various additions start pretty early in the cycle ( as not much decode logic is needed to 

// get them started.   In parallel with that - the destination selectors ( which require more

// complex decoding logic ) are "doing thier thing"  No claim that this is absolute optimum - any 

// good synthesizer should be able to make the basic structure faster when flattened.   However, 

// the intention is that even if the synthesizer is pretty primitive -- reasonably fast hardware 

// will be produced.

// 

//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0

//

//  $Id: z80_inst_exec.v,v 1.1 2008-12-01 02:00:10 hharte Exp $

//

//  $Date: 2008-12-01 02:00:10 $

//  $Revision: 1.1 $

//  $Author: hharte $

//  $Locker:  $

//  $State: Exp $

//

// Change History:

//      $Log: not supported by cvs2svn $

//      Revision 1.4  2004/05/21 02:51:25  bporcella

//      inst test  got to the worked macro

//

//      Revision 1.3  2004/05/18 22:31:21  bporcella

//      instruction test getting to final stages

//

//      Revision 1.2  2004/05/13 14:58:53  bporcella

//      testbed built and verification in progress

//

//      Revision 1.1  2004/04/27 21:27:13  bporcella

//      first core build

//

//      Revision 1.4  2004/04/19 19:13:27  bporcella

//      real lint problems pretty much fixed   --  need another look - but need to get on to other things first

//

//      Revision 1.3  2004/04/19 05:09:11  bporcella

//      fixed some lint problems  --

//

//      Revision 1.2  2004/04/18 18:50:08  bporcella

//      fixed some lint problems  --

//

//      Revision 1.1.1.1  2004/04/13 23:49:54  bporcella

//      import first files

//

//

//

//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0

module z80_inst_exec( br_eq0,

                  cr_eq0,

                  upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,

                  ar, fr, br, cr, dr, er, hr, lr, intr,

                  ixr, iyr, add16, alu8_out,  sh_alu, bit_alu,

                   exec_ir2,

                   exec_decbc, exec_decb,

                   adr_alu,

                   blk_mv_upd_hl,

                   blk_mv_upd_de,

                   ir2,

                   clk,

                   rst,

                   nn, sp,

                   ir2dd,

                   ir2fd

                   );

//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0

output          br_eq0;

output          cr_eq0;

output          upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr;

output  [7:0]   ar, fr, br, cr, dr, er, hr, lr, intr;

output  [15:0]  ixr, iyr;

output  [15:0]  add16;

output  [7:0]   alu8_out;   // used for INCs6HL7 and DECs6HL7 types ---   flags need updating

                            // also so need to do with alu8. 

output  [7:0]   sh_alu;

output  [7:0]   bit_alu;

//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0

input        exec_ir2;

input        exec_decbc;  // in general this needs to happen at different time from exec

input        exec_decb;   // in general - we don't have the EB instruction (yet) when this hits

input [9:0]  ir2;

input        clk;

input        rst;

input [15:0] nn, sp;

input        ir2dd;       // this must be ir2

input        ir2fd;

input [15:0] adr_alu;

input        blk_mv_upd_hl;

input        blk_mv_upd_de;

//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0

`include "opcodes.v"

//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0

//wire [7:0]   src_pqr;    //  arithmetic sources gven by ir2[2:0]

wire [7:0]   src_hr ;

wire [7:0]   src_lr ;

//wire [7:0]   alu_out;  // {CF. 8bit_result}

//wire         alu_cry;

//wire            c_in0, c_out7, c_in8, c_out11, cout15;

wire   [15:0]   src_a, src_b;

wire   [15:0]   add16;

wire            sf, zf, f5f, hf, f3f, pvf, nf, cf;

wire   [7:0]    daa_alu; // {cry, number}   hf goes to 0 always.

wire            daa_cry;

wire            upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_fr, upd_hr, upd_lr;

wire        c_8out3;

wire [7:0]  add_8bit;

wire  [15:0]  src_dblhr       ;

//wire          src_cb_r20      ;

wire  [7:0]  src_pqr20       ;

wire  [7:0]   src_pqr53       ;

wire  [15:0]  src_dbl         ;

wire  [7:0]   alu8_fr         ;

wire          alu8_nf         ;

wire          c_8out7         ;

wire          alu8_cry        ;

wire          alu8_pvf        ;

wire          alu8_hcry       ;

wire  [7:0]   alu8_out        ;

wire          add16_ofl       ;

wire          c_16out7        ;

wire          c_16out11       ;

wire          c_16out15       ;

wire          c_16in0         ;

wire          sh_cry          ;

wire  [7:0]   sh_alu          ;

wire          sh_alu_act      ;

wire          bit_alu_act     ;

wire  [7:0]   bit_alu         ;

wire  [7:0]   decc_alu        ;

wire  [7:0]   decb_alu        ;

wire          upd_a_alu8      ;

wire          up_a_sh_alu     ;

wire          up_a_src_pqr    ;

wire          up_a_n          ;

wire          upd_b_alu8      ;

wire          up_b_src_pqr    ;

wire          up_b_add16      ;

wire [7:0]    sh_src          ;

wire          up_c_add16       ;

wire          upd_c_alu8       ;

wire          up_c_src_pqr     ;

wire          up_d_add16       ;

wire          upd_d_alu8       ;

wire          up_d_src_pqr     ;

wire          up_e_add16       ;

wire          upd_e_alu8       ;

wire          up_e_src_pqr     ;

wire          up_h_add16       ;

wire          upd_h_alu8       ;

wire          upd_h_src_pqr    ;

wire          up_l_add16       ;

wire          upd_l_alu8       ;

wire          upd_l_src_pqr    ;

wire          upd_bc_cpi       ;

wire          upd_fr_alu8      ;

wire          upd_fr_add16     ;

wire          upd_fr_edadd16   ;

wire          upd_fr_sh        ;

wire          upd_fr_cbsh      ;

//wire          eb_blk_mv        ;

wire          ed_blk_cp        ;

wire          c_8in0           ;

//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0

reg [7:0] ar, fr, br, cr, dr, er, hr, lr, intr;

reg [7:0] ap, fp, bp, cp, dp, ep, hp, lp;

reg [15:0] ixr, iyr;

//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0

//  it appears that dd and fd as a prefix to cb has a significantly modfied fuction......

//  specifically, it is assumed that a memory operation is to be implemented (ix + d)

// ,  In fact the 

// pipeline is such that we can make a fetch for free  - so we will do that.....   the 

// prefix flags should not be set here   -- all we will know on execution is that it is a 

// cb instruction.   ----   src is always nn 

assign  src_hr = ir2dd ? ixr[15:8] :

                 ir2fd ? iyr[15:8] :

                 hr                   ;

assign  src_lr = ir2dd ? ixr[7:0] :

                 ir2fd ? iyr[7:0] :

                 lr                 ;

assign src_dblhr = ir2dd ? ixr :    // ed grp instructions (ADC HL ; SBC HL are not affected -

                   ir2fd ? iyr :    // instruction assembler assures this - ed_grp has no prefix

                   {hr, lr}      ;

//  ddcb_grp not defined  - src_cb_r20  not used.  Why these lines?  4/17/2004

//assign  src_cb_r20 = (ddcb_grp | fdcb_grp) ? nn[7:0]   :

//                             cb_grp        ? src_pqr20 :

//                             ar                        ;

assign  br_eq0 = ~|br; // for first cut do this quick and dirty.   

assign  cr_eq0 = ~|cr; // if this becomes a critical path - make these registers.

assign  src_pqr20 = {8{ir2[2:0]==REG8_B   }} & br     |

                    {8{ir2[2:0]==REG8_C   }} & cr     |

                    {8{ir2[2:0]==REG8_D   }} & dr     |

                    {8{ir2[2:0]==REG8_E   }} & er     |

                    {8{ir2[2:0]==REG8_H   }} & src_hr |

                    {8{ir2[2:0]==REG8_L   }} & src_lr |

                    {8{ir2[2:0]==REG8_MEM}} & nn[15:8] |

                    {8{ir2[2:0]==REG8_A   }} & ar      ;

assign src_pqr53 =  {8{ir2[5:3]==REG8_B   }} & br     |

                    {8{ir2[5:3]==REG8_C   }} & cr     |

                    {8{ir2[5:3]==REG8_D   }} & dr     |

                    {8{ir2[5:3]==REG8_E   }} & er     |

                    {8{ir2[5:3]==REG8_H   }} & src_hr |

                    {8{ir2[5:3]==REG8_L   }} & src_lr |

                    {8{ir2[5:3]==REG8_MEM}} & nn[15:8] |

                    {8{ir2[5:3]==REG8_A   }} & ar      ;

assign src_dbl =   {16{ir2[5:4]==2'b00}} & {br, cr}  |

                   {16{ir2[5:4]==2'b01}} & {dr, er}  |

                   {16{ir2[5:4]==2'b10}} & src_dblhr |   // HL, ixr, iyr

                   {16{ir2[5:4]==2'b11}} & sp         ;

assign sh_src =   ir2[8] & ir2dd ?  nn[15:8]   :

                  ir2[8] & ir2fd ?  nn[15:8]   :

                  ir2[8]          ?  src_pqr20  :

                                     ar          ;

// I wonder how well the synthesizer can reduce this??? - It is probably worth spending

// some time during physical design to see if a more low level description would help --

// there is somebody out there who knows  -  and there is probably a good low level description.

//

// guess its kind of important to understand precisely what the synthesizer does 

// with some of the status things we need also. 

//

//

//  The nastiest status to get is HF.  Really need 4 bit adders to do that  ( or reproduce a lot

//  of logic.)  I don't have a lot of confdence in the synthesier's ability to minimize arithmetic

//  operations   --  Its a moving target of course, but I've seen some really silly stuff come out

//  of synthesis when you use a "+" operator.   guess I will be pretty explicit here.  

//  Documentation of the HF is srange.  IN and OUT operators are defined as X  -- but 16 bit operations

//  get set by CRY from bit 11.  (Do I care??? ) well probably not but it is documented  - so should 

//  be tested i guess.   

//

//  

//  may want to re-define as a module with carry look-ahead ?  

//

//  Had a notion to define a single adder - subtractor for both 8 and 16 bit operations, but 

//  getting into source mux issues that solution scared me.....   Worry the cry flag might

//  become a worst case path.   As defined, a good chunk of the decode process can go on in 

//  parallel with the cry computation ---   with final decisions made using a small mux at 

//  the flag register.

//  ------------ 8 bit adder for accumulator ops  plus the INC DEC ops ---------------------

//  It is documented that the hf is modified by the INC and DEC ops even if ar is not the 

//  destination of result   ---   clearly hf and nf are pretty usless on a INC B but ours is 

//  not to reason why :-)  ----   well its fun to bitch about silly stuff like this.  

//  ( not as much fun to deal with instruction tests testing "features" -- or worse programmers

//   who figure out ways to use theses "features". )

//

//  8 bit adder with cry out of bit 3   used for most operations on A as well as the 

//  inc/dec instructions.   also need to get ED44 (ar <= -ar) working here

wire [7:0]  src_pqri;  // use just here and below

wire [7:0]  src_aor_cnst = ed_blk_cp ?  ar    :  // CPI CPIR CPD CPDR

                              ir2[9] ?  8'h0  :  // for ed44 -a  //ed_grp == ir2[9]

                              ir2[7] ?  ar    :

                              ir2[0] ?  8'hff :

                                        8'h00  ;

//---------------  the "standard" flag logic -----------------------------

//                 sf           zf            f5f          hf        

assign alu8_fr ={alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry,

//                 f3f          fpv           fn         fc

                 alu8_out[3], alu8_pvf, alu8_nf,  alu8_cry };

 //   excludeINC_r DEC_r        AND               XOR                    OR

assign alu8_pvf = ir2[7] & (ir2[5:3]==7'b100 | ir2[5:3]==7'b101 | ir2[5:3]==7'b110) ?

                                                                    ~^alu8_out   : // even parity

                (src_aor_cnst[7]==src_pqri[7]) & (src_aor_cnst[7]!=alu8_out[7])  ; // ofl 

assign alu8_nf = (ir2[7:3]==5'b10010)       |

                 (ir2[7:3]==5'b10011)       |

                 (ir2[7:6]==2'b00) & ir2[0] |

                 ir2[9]                      ;

assign {c_8out3, add_8bit[3:0]} = {1'b0, src_aor_cnst[3:0]} + {1'b0, src_pqri[3:0]}   + {4'b0, c_8in0};

//wire [4:0] ha_temp = {1'b0, src_aor_cnst[3:0]} + {1'b0, src_pqri[3:0]}   + {4'b0, c_8in0};

//assign c_8out3 

assign {c_8out7, add_8bit[7:4]} = {1'b0, src_aor_cnst[7:4]} + {1'b0, src_pqri[7:4]}   + {4'b0, c_8out3};

//  notice that both inputs and outputs of the adder are being selected below.

//  making ed_blk_cp high priority kind of negates the origional idea of making the

//  decodes fast here  ---   course when all is included this can't be too fast.

//  Just note for syntheses that this is a slow path that could be improved with some thought.

//         1         1          8          8        1

assign {alu8_cry, alu8_hcry, alu8_out,  src_pqri, c_8in0 }=

   ed_blk_cp ?                         {c_8out7,c_8out3,  add_8bit,   ~nn[15:8], 1'h1} :   //CPI CPIR CPD CPDR

   {19{ir2[7] & ir2[5:3]==3'b000}} & ({c_8out7,c_8out3,  add_8bit,    src_pqr20, 1'b0} )  |// a+src

   {19{ir2[7] & ir2[5:3]==5'b001}} & ({c_8out7,c_8out3,  add_8bit,    src_pqr20,   cf} )  |// a+src+cf

   {19{ir2[7] & ir2[5:3]==5'b010}} & ({~c_8out7,c_8out3,  add_8bit,   ~src_pqr20, 1'h1} )  |// a-src

   {19{ir2[7] & ir2[5:3]==5'b011}} & ({~c_8out7,c_8out3,  add_8bit,   ~src_pqr20, ~cf } )  |// a-src-cf

   {19{ir2[7] & ir2[5:3]==5'b100}} & ({1'b0   ,1'b1   , ar & src_pqr20, src_pqr20, 1'b0} )|// a&src

   {19{ir2[7] & ir2[5:3]==5'b101}} & ({1'b0   ,1'b0   , ar ^ src_pqr20, src_pqr20, 1'b0} )|// a^src

   {19{ir2[7] & ir2[5:3]==5'b110}} & ({1'b0   ,1'b0   , ar | src_pqr20, src_pqr20, 1'b0} )|// a|src

   {19{ir2[7] & ir2[5:3]==5'b111}} & ({~c_8out7,c_8out3,  add_8bit,   ~src_pqr20,  1'h1})  |// a-src

   {19{(ir2[7:6]==2'b00)& ~ir2[0] }}& ({     cf,c_8out3,  add_8bit,    src_pqr53,  1'h1}) |// inc_r main

   {19{(ir2[7:6]==2'b00)&  ir2[0] }}& ({     cf,c_8out3,  add_8bit,    src_pqr53,  1'h0}) |// dec_r

   {19{(ir2[7:6]==2'b01)          }}& ({~c_8out7,c_8out3,  add_8bit,          ~ar,  1'h1})  ;// ed44 -a

// do some hand  decoding here                                        

//  ADDsHL_BC    = 'h09,  DECsBC       = 'h0B, INCsBC       = 'h03    compair with {ir2[7:6],ir2[3:0]}

//  ADDsHL_DE    = 'h19,  DECsDE       = 'h1B  INCsDE       = 'h13    ED_SBCsHL_REG  = 6'b01__0010

//  ADDsHL_HL    = 'h29,  DECsHL       = 'h2B  INCsHL       = 'h23    ED_ADCsHL_REG  = 6'b01__1010

//  ADDsHL_SP    = 'h39,  DECsSP       = 'h3B  INCsSP       = 'h33

//  by inspection just use ir2[3:0]  -  i guess in a pinch we do't need ir2[2]  =  but let the 

//  synthesizer figure that out. - it should be able to.

//

// ---------------- 16 bit adder with bit 11 carrry out and bit 8 carry in ------------------

//

assign add16_ofl = (src_a[15] == src_b[15]) & (src_a[15] != add16[15]);

 ///tmp/lint/wb_z80/rtl/inst_exec.v(363): Warning 22014: synchronous loop without set/reset detected on signal "src_b[11:8]" (OC)

assign {c_16out7,  add16[7:0]}  = {1'b0, src_a[7:0]}   + {1'b0, src_b[7:0]   } + {8'b0, c_16in0};

assign {c_16out11, add16[11:8]} = {1'b0, src_a[11:8]}  + {1'b0, src_b[11:8]  } + {4'b0, c_16out7};

assign {c_16out15, add16[15:12]} = {1'b0, src_a[15:12]} + {1'b0, src_b[15:12]} + {4'b0, c_16out11};

assign  { src_a,     src_b, c_16in0} =         // assigning 33 bits

   {33{ir2[3:0] == 4'h9}} & {src_dblhr, src_dbl  ,1'b0 }   |  //ADD

   {33{ir2[3:0] == 4'hb}} & {16'hffff , src_dbl  ,1'b0 }   |  //DEC 

   {33{ir2[3:0] == 4'h3}} & {16'h0001 , src_dbl  ,1'b0 }   |  //INC

   {33{ir2[3:0] == 4'h2}} & {src_dblhr, ~src_dbl , ~cf }   |  //SBC

   {33{ir2[3:0] == 4'ha}} & {src_dblhr, src_dbl  , cf  }    ; //ADC

//-------------------------- sh alu --------------------------------------------------

//  shift insructions.  Think of these as 8 shift types:

//  RLC RL RRC RR SLA SLL SRA SRL  The SLL types appear to be undocumented  -- but possibly used 

//   in assembly code as they appear to have some utility  -  and by all accounts operate reliably. 

//   The first four are implemented in a single byte inaruction . (A <= sh_op A )

//   All 8  are implemented in the CB group with all registers as potential sources (and dests).

//   if ir2dd or ir2fd is prefix.....   source is always the memory. This is undocumented - but

//   may be a useful hint for simplyfing the total machine.  Destination registers

//   (if any) get a copy of the updated memory location  (This is also true of the bit set and 

//   clear instructions in the cb_grp.

assign {sh_cry, sh_alu} =  {9{ir2[5:3]==3'b000}} & {sh_src, sh_src[7] }                 | //RLC

                           {9{ir2[5:3]==3'b001}} & {sh_src[0], sh_src[0], sh_src[7:1]}  | // RRC

                           {9{ir2[5:3]==3'b010}} & {sh_src, cf  }                       | //RL 

                           {9{ir2[5:3]==3'b011}} & {sh_src[0], cf, sh_src[7:1] }        | // RR 

                           {9{ir2[5:3]==3'b100}} & {sh_src, 1'b0}                       |  //SLA

                           {9{ir2[5:3]==3'b101}} & {sh_src[0], sh_src[7], sh_src[7:1]}  |  //SRA

                           {9{ir2[5:3]==3'b110}} & {sh_src, 1'b1}                       |  //SLL

                           {9{ir2[5:3]==3'b111}} & {sh_src[0], 1'b0, sh_src[7:1]}      ;   //SRL

 // shift insts

 assign sh_alu_act = ir2[9:6] == 4'b0100;

 //CB_RLC   = 7'b01_00_000,  // these must be compaired with ir2[9:3]

 //CB_RRC   = 7'b01_00_001,  // these must be compaired with ir2[9:3]

 //CB_RL    = 7'b01_00_010,  // these must be compaired with ir2[9:3]

 //CB_RR    = 7'b01_00_011,  // these must be compaired with ir2[9:3]

 //CB_SLA   = 7'b01_00_100,  // these must be compaired with ir2[9:3]

 //CB_SRA   = 7'b01_00_101,  // these must be compaired with ir2[9:3]

 //CB_SLL   = 7'b01_00_110,  // these must be compaired with ir2[9:3]

 //CB_SRL   = 7'b01_00_111,  // these must be compaired with ir2[9:3]

//---------------------------- bit test alu ---------------------------------------

//  bit test insts

//CB_BIT   = 4'b01_01,    // these must be compaired with ir2[9:6]

//CB_RES   = 4'b01_10,    // these must be compaired with ir2[9:6]assign 

//CB_SET   = 4'b01_11,    // these must be compaired with ir2[9:6] 

assign bit_alu_act = ir2[9:6] == CB_RES |

                     ir2[9:6] == CB_SET ;

wire [7:0] bit_decode = {8{ir2[5:3] == 3'h0}} & 8'h01 |

                        {8{ir2[5:3] == 3'h1}} & 8'h02 |

                        {8{ir2[5:3] == 3'h2}} & 8'h04 |

                        {8{ir2[5:3] == 3'h3}} & 8'h08 |

                        {8{ir2[5:3] == 3'h4}} & 8'h10 |

                        {8{ir2[5:3] == 3'h5}} & 8'h20 |

                        {8{ir2[5:3] == 3'h6}} & 8'h40 |

                        {8{ir2[5:3] == 3'h7}} & 8'h80 ;

assign bit_alu = {8{ir2[9:6] == CB_BIT}} & ( sh_src & bit_decode)  |

                 {8{ir2[9:6] == CB_RES}} & ( sh_src & ~bit_decode) |

                 {8{ir2[9:6] == CB_SET}} & ( sh_src | bit_decode)   ;

//------------ dec bc alu ---------------------------------------------

//exec_decbc;  these are all we know (in general)

//exec_decb;

assign decc_alu  =  cr + 8'hff ;

assign decb_alu  =  br + ( exec_decb ? 8'hff :    // just dec b if io blk move

                              cr_eq0 ? 8'hff :    // cry out if c in this case

                                      8'h00 );   // only dec c reg this tick

// ------------------ daa alu -------------------------------------------------------

// the documentation does not cover all cases here  -- only those that matter (i suppose).

// ( documentation assumes you are operating with 2 daa'd numbers  --  but of course the

// ar can contain many values that don't fit that assumption when this instruction is executed.

// Any arbitrary instruction test may test un-documented cases.

//

// this leaves me to guess what the actual logic is  - and how to match it.   

// So I am doing that -- see what happens. If an instruction test breaks this...  I should be 

// able to fix it easily.

//

wire [3:0] ls_nbl   =  (!nf & hf)                 ?  4'h6:

                       (!nf & (ar[3:0] > 4'h9))   ?  4'h6:

                       (nf  & hf )                ?  4'ha:

                                                     4'h0;

wire [4:0] ms_nbl   =  (!nf & cf)                 ?  5'h16:    //  includes new cry

                       (!nf & (ar[3:0]  > 4'h9))  ?  5'h16:

                       (!nf & (ar[3:0] == 4'h9) &

                               (ar[3:0] > 4'h9))  ?  5'h16:

                       (nf  & !cf  &  hf )        ?  5'h0f:

                       (nf  &  cf  & !hf )        ?  5'h1a:

                       (nf  &  cf  &  hf )        ?  5'h19:

                                                     5'h00;

assign {daa_cry, daa_alu} = { ms_nbl[4], {ar + { ms_nbl[3:0], ls_nbl}}  } ;

//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0

//  update ar

assign upd_a_alu8 =

    ADDsA_B      == ir2 | SUBsB      == ir2 |  ANDsB      == ir2 | ORsB         == ir2   |

    ADDsA_C      == ir2 | SUBsC      == ir2 |  ANDsC      == ir2 | ORsC         == ir2   |

    ADDsA_D      == ir2 | SUBsD      == ir2 |  ANDsD      == ir2 | ORsD         == ir2   |

    ADDsA_E      == ir2 | SUBsE      == ir2 |  ANDsE      == ir2 | ORsE         == ir2   |

    ADDsA_H      == ir2 | SUBsH      == ir2 |  ANDsH      == ir2 | ORsH         == ir2   |

    ADDsA_L      == ir2 | SUBsL      == ir2 |  ANDsL      == ir2 | ORsL         == ir2   |

    ADDsA_6HL7   == ir2 | SUBs6HL7   == ir2 |  ANDs6HL7   == ir2 | ORs6HL7      == ir2   |

    ADDsA_A      == ir2 | SUBsA      == ir2 |  ANDsA      == ir2 | ORsA         == ir2   |

    ADCsA_B      == ir2 | SBCsB      == ir2 |  XORsB      == ir2 |

    ADCsA_C      == ir2 | SBCsC      == ir2 |  XORsC      == ir2 | INCsA        == ir2   |

    ADCsA_D      == ir2 | SBCsD      == ir2 |  XORsD      == ir2 | DECsA        == ir2   |

    ADCsA_E      == ir2 | SBCsE      == ir2 |  XORsE      == ir2 |

    ADCsA_H      == ir2 | SBCsH      == ir2 |  XORsH      == ir2 |

    ADCsA_L      == ir2 | SBCsL      == ir2 |  XORsL      == ir2 |

    ADCsA_6HL7   == ir2 | SBCs6HL7   == ir2 |  XORs6HL7   == ir2 |

    ADCsA_A      == ir2 | SBCsA      == ir2 |  XORsA      == ir2 |

    ADDsA_N      == ir2 | //      ADD A,N      ; C6 XX   ADDsA_6HL7   = 'h86

    ADCsA_N      == ir2 | //      ADC A,N      ; CE XX   ADCsA_6HL7   = 'h8E

    SUBsN        == ir2 | //      SUB N        ; D6 XX   SUBs6HL7     = 'h96

    SBCsA_N      == ir2 | //      SBC A,N      ; DE XX

    ANDsN        == ir2 | //      AND N        ; E6 XX

    XORsN        == ir2 | //      XOR N        ; EE XX

    ORsN         == ir2 ; //      OR N         ; F6 XX

assign up_a_sh_alu =

    RLCA         == ir2   | //      RLCA        ; 07

    RRCA         == ir2   | //      RRCA        ; 0F

    RRA          == ir2   | //      RRA          ; 1F

    RLA          == ir2   ; //      RLA          ; 17

assign up_a_src_pqr =

    LDsA_B       == ir2 |    //      LD A,B       ; 78

    LDsA_C       == ir2 |    //      LD A,C       ; 79

    LDsA_D       == ir2 |    //      LD A,D       ; 7A

    LDsA_E       == ir2 |    //      LD A,E       ; 7B

    LDsA_H       == ir2 |    //      LD A,H       ; 7C

    LDsA_L       == ir2 |    //      LD A,L       ; 7D

    LDsA_6HL7    == ir2 |    //      LD A,(HL)    ; 7E

    LDsA_A       == ir2 ;    //      LD A,A       ; 7F

assign up_a_n =

    LDsA_N       == ir2 | //      LD A,N       ; 3E XX

    LDsA_6BC7    == ir2 | //      LD A,(BC)    ; 0A

    LDsA_6DE7    == ir2 | //      LD A,(DE)    ; 1A

    LDsA_6NN7    == ir2 | //      LD A,(NN)    ; 3A XX XX

    INsA_6N7     == ir2 | //      IN A,(N)     ; DB XX        

    (ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_A) ;

//EXsAF_AFp    = 10'h08,//      EX AF,AF'    ; 08

//EXX          = 10'hD9,//      EXX          ; D9

//DAA          = 10'h27,//      DAA          ; 27

//CPL          = 10'h2F,//      CPL          ; 2F   a <= ~a

//POPsAF       = 10'hF1,//      POP AF       ; F1

//  don't forget these beauties  not affected by prefixes

//ED_RRD       =  'h67//      RRD        ;  

//ED_RLD       =  'h6F//      RLD        ; ED 6F   nibble roates A (HL)

//ED_NEG         =    5'b01___100, // A<= -A   compair with {ir2[9:6],ir2[2:0]}                

//------------------------------- ar ------------------------------------------