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1 3 hharte
////////////////////////////////////////////////////////////////////////////////////////////////////
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//                                                                                               //
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//  file name:   memstate2.v                                                                     //
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//  description: memory opertions for  z80                                                       //
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//  project:     wb_z80                                                                          //
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//                                                                                               //
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//  Author: B.J. Porcella                                                                        //
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//  e-mail: bporcella@sbcglobal.net                                                              //
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//                                                                                               //
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//                                                                                               //
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//                                                                                               //
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///////////////////////////////////////////////////////////////////////////////////////////////////
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//                                                                                               //
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// Copyright (C) 2000-2002 B.J. Porcella                                                         //
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//                         Real Time Solutions                                                   //
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//                                                                                               //
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//                                                                                               //
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// This source file may be used and distributed without                                          //
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// restriction provided that this copyright statement is not                                     //
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// removed from the file and that any derivative work contains                                   //
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// the original copyright notice and the associated disclaimer.                                  //
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//                                                                                               //
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//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY                                       //
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED                                     //
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS                                     //
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR                                        //
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,                                           //
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES                                      //
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE                                     //
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR                                          //
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF                                    //
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// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT                                    //
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT                                    //
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE                                           //
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// POSSIBILITY OF SUCH DAMAGE.                                                                   //
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//                                                                                               //
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//-------1---------2---------3--------Comments on file  -------------7---------8---------9--------0
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// The memory state controller controls the wb bus, and provides address sequencing.
39
// Insructions are fetched in order (using PC) until the istate machine indicates that 
40
// a complete instruction is in the first pipline stage (ir1). In general, operands are being
41
// fetched (stored) to satisfy ir1 while concurrently instructions are being executed from ir2.
42
// this situation can result in a number of potential hazards.   As an example, if the ir2
43
// instruction changes the flag register and the ir1 instruction is a conditional jump, 
44
// a hazard is generated by the hazard logic, and execution of the ir1 operation is delayed 
45
// until the completion of the flag update.
46
//
47
// Reset starts execution at 0.  
48
// The PC and SP are described in this file.   modifications to other index registers - 
49
// HL IX and IY are computed here -- 
50
// For the block moves address updates are computed here   -- and commanded here.
51
// Strobes for the second address update are generally co-incident with count updates, but
52
// we provide seperate strobe update lines for clarity.
53
//
54
//  BASIC ARCHITECTURE OF THIS FILE   pc  and sp not shown, but are inputs to src mux.
55
//                    _____           and may be updated from adder output.
56
//                   |     |
57
//                   |     |          pc-1 register is required to implement relative jumps.
58
//                   |     |                     
59
//      _____        |lit  |      |\             
60
//     |     |       |     |      |  \           
61
//     |     |       |src2 |      |    \          _____          _____ 
62
//     |     |       |     |----->|     |        |     |        |     |
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//     |src  |       |_____|      |adder|------->|     |        |     |
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//     |mux  |                    |     |        |     |        |     |
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//     |     |------------------->|    /         |2/1  |------->|wb   |
66
//     |     |              |     |  /           |mux  |        |adr  |
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//     |_____|              |     |/             |     |        |     |
68
//                           ------------------->|     |        |     |
69
//                                               |_____|        |_____|
70
//
71
//
72
//
73
//
74
//  Operand Stores:
75
//  At first cut, I thought I'ld execute operand stores immediately from the memory sequencer
76
//  (essentially before ir2 got the store data).  While this might be modestly faster in 
77
//  systems that take multiple clocks to complete a memory store, On consideration, I decided 
78
//  to forgo the extra speed for conceptual simplicity....   execute operand stores on op_ph1,
79
//  and let the inst_exec engine suply the operand.
80
//
81
//  On second thought, above is not only wastful of time, but also inconsistent with the overall
82
//  schems of things - and so somewhat more complex. If we simply execute the OS from ir1, 
83
//  There is less state to contdend with, as well as extra speed.
84
//
85
//  Block Moves fundamentally execute from ir2.  We initiate the first operand fetch from ir1.
86
//
87
//  3/18/2004 Second time through.   In impleenting the execution logic it became clear that
88
//  there were "minor" problems with the handling of the DD and FD prefix insts (especially
89
//  DDCD and FDCB  ---  collectively called PFxCB below.  On review, I had to question the
90
//  value of "breaking up" the ir0 execution engine between the istate sequencer and the 
91
//  memstate sequencer.   While I dislike state sequencers of much more than 16 states  --  
92
//  the interaction between these sequencers was becomming harder to track than a single
93
//  state macine.   Thus - this file is getting re-worked.   I will call it memstate2 (at least
94
//  for awhile) as I wish to keep the old file around.  I want to show (in the state machine
95
//  logic) what the next memory operation is....   guess the best method consistent with my
96
//  documentation practices is to define a register (mem_op)  = { if, wb_we_o, wb_cyc_o }.  
97
//  This will require auxillary logic for computing the address ---  but most of the decodes
98
//  required will be there anyway.   
99
//  On further reflection, I think I will bite-the-bullet and use an always to define next_state.
100
//  I don't like to use always to define wires, but I also want to document the setting of 
101
//  exec_ir2 in the same place - that is 3 different things.  
102
//  
103
//  Hazards:
104
//  There are 2 kinds of hazards:  mem_hazard => we are storing into the next instruction location
105
//                                 reg_hazard => we are modifying a register (ir2) that we are using
106
//                                                here (ir1)
107
//  In the former case, we throw out the instruction that arrives on the next tick, and restart the
108
//  instruction pipeline,   In the latter case, we simply wait a tick for the ir2 operaton to 
109
//  complete before starting the ir1 operation  
110
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//
112
//  $Id: z80_memstate2.v,v 1.1 2008-12-01 02:00:10 hharte Exp $
113
//
114
//  $Date: 2008-12-01 02:00:10 $
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//  $Revision: 1.1 $
116
//  $Author: hharte $
117
//  $Locker:  $
118
//  $State: Exp $
119
//
120
// Change History:
121
//      $Log: not supported by cvs2svn $
122
//      Revision 1.8  2007/10/12 17:08:43  bporcella
123
//      added fix for IN bug found by howard
124
//
125
//      Revision 1.7  2007/10/02 20:25:12  bporcella
126
//      fixed bugs and augmented instruction test.
127
//      ex   de hl     bug fixed                               thanks Howard Harte
128
//      ret   condition            (ret not taken bug)   thanks -  Stephen Warren
129
//
130
//      Revision 1.6  2004/06/03 20:29:35  bporcella
131
//      some fixes found in synthesis
132
//
133
//      Revision 1.5  2004/05/27 14:23:36  bporcella
134
//      Instruction test (with interrupts) runs!!!
135
//
136
//      Revision 1.4  2004/05/21 02:51:25  bporcella
137
//      inst test  got to the worked macro
138
//
139
//      Revision 1.3  2004/05/18 22:31:21  bporcella
140
//      instruction test getting to final stages
141
//
142
//      Revision 1.2  2004/05/13 14:58:53  bporcella
143
//      testbed built and verification in progress
144
//
145
//      Revision 1.1  2004/04/27 21:27:13  bporcella
146
//      first core build
147
//
148
//      Revision 1.8  2004/04/19 19:13:28  bporcella
149
//      real lint problems pretty much fixed   --  need another look - but need to get on to other things first
150
//
151
//      Revision 1.7  2004/04/19 05:09:11  bporcella
152
//      fixed some lint problems  --
153
//
154
//      Revision 1.6  2004/04/18 18:50:09  bporcella
155
//      fixed some lint problems  --
156
//
157
//      Revision 1.5  2004/04/17 15:18:02  bporcella
158
//      4th lint try
159
//      Miha claims reports are now correct
160
//
161
//      Revision 1.4  2004/04/16 18:16:57  bporcella
162
//      try lint
163
//
164
//      Revision 1.3  2004/04/16 17:06:54  bporcella
165
//      no code change  -  added a comment and test lint
166
//
167
//      Revision 1.2  2004/04/16 16:21:04  bporcella
168
//      no code change  -  added a comment and test lint
169
//
170
//      Revision 1.1.1.1  2004/04/13 23:50:19  bporcella
171
//      import first files
172
//
173
//
174
//
175
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
176
module z80_memstate2(wb_adr_o, wb_we_o, wb_cyc_o, wb_stb_o, wb_tga_o, wb_dat_o,
177
                exec_ir2,
178
                exec_decbc, exec_decb,
179
                ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,
180
 
181
                upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
182
                beq0, ceq0,
183
                ar, fr, br, cr, dr, er, hr, lr, intr,
184
                ixr, iyr,
185
                wb_dat_i, wb_ack_i, wb_clk_i,
186
                int_req_i,
187
                add16,
188
                alu8_out,
189
                adr_alu,
190
                blk_mv_upd_hl,
191
                blk_mv_upd_de,
192
                sh_alu,
193
                bit_alu,
194
                rst_i
195
 
196
 
197
);
198
 
199
//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
200
// mod only to checkout lint
201
// mod again for lint check  --   first check pretty wierd
202
// 3rd lint try
203
// 4th lint try
204
output [15:0]  wb_adr_o;
205
output         wb_we_o;
206
output         wb_cyc_o;
207
output         wb_stb_o;
208
//output         wb_lock;  // bit set and clear insts should be atomic - could matter sometime
209
output [1:0]   wb_tga_o;
210
output [7:0]   wb_dat_o;   // from nn
211
output [15:0]  adr_alu;    // 4/18/2004??  why? 5/20  to update hl on 
212
                           // block moves silly
213
 
214
output         blk_mv_upd_hl;
215
output         blk_mv_upd_de;
216
output         exec_ir2;
217
output [9:0]   ir1, ir2;
218
output         ir1dd, ir2dd;
219
output          ir1fd, ir2fd;
220
output [15:0]   nn;
221
output [15:0]   sp;
222
output          exec_decbc, exec_decb;
223
 
224
 
225
 
226
 
227
//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
228
input           upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr;
229
 
230
input           beq0, ceq0;
231
input [7:0]     ar, fr, br, cr, dr, er, hr, lr, intr;
232
input [15:0]    ixr, iyr;
233
input [7:0]     wb_dat_i;
234
input           wb_ack_i, wb_clk_i, rst_i;
235
input           int_req_i;
236
input [15:0]    add16;         //  ir2 execution engine output for sp updates
237
input [7:0]     alu8_out;
238
input [7:0]     sh_alu;        // rmw shifts
239
input [7:0]     bit_alu;
240
//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
241
`include "opcodes.v"            //  states of the main memory sequencer
242
 
243
 
244
parameter   TAG_IO    = 2'b01,   // need to review general wb usage to undrstand how best to 
245
            TAG_INT   = 2'b10;   // document this.
246
            //                   12na // 1 is ir1 2 is ir2 n is nn gets memory a is activate ir2
247
parameter   IPIPE_NOP       = 4'b0000,   //  guess I could define single bits and add them up
248
            IPIPE_A2        = 4'b0001,   //  would keep from getting lint bitching -- but heck
249
            IPIPE_ENN       = 4'b0010,   //  I'm married -> an expert at ignoring such stuff :-)
250
            IPIPE_ENNA2     = 4'b0011,
251
            IPIPE_EN2       = 4'b0100,
252
            IPIPE_EN2A2     = 4'b0101,
253
            IPIPE_ENNEN2    = 4'b0110,
254
            IPIPE_ENNEN2A2  = 4'b0111,
255
            IPIPE_EN1       = 4'b1000,
256
            IPIPE_EN1A2     = 4'b1001,
257
            IPIPE_BOGUS     = 4'b1010,  // no reason (yet) to load both n and ir1
258
            IPIPE_BOUS2     = 4'b1011,
259
            IPIPE_EN12      = 4'b1100,
260
            IPIPE_EN12A2    = 4'b1101,
261
            IPIPE_BOGUS3    = 4'b1110,
262
            IPIPE_BOGUS4    = 4'b1111;
263
 
264
//  well at first cut I tried to make this 2 state macines both less than 16 states.
265
//  this is 56 states at first cut.   Assignemnt is subject to change.
266
//  10/11/2007   I really need some comments about the states.  Lots of stuff here to 
267
//               pick up from scratch.
268
// ------  mem state decoder state machine states --------------------------------
269
parameter       DEC_IDLE      = 6'h00,
270
                DEC_HALT      = 6'h01,   //  note that we can service interrupts while "halted"          
271
                DEC_IF1       = 6'h02,   //  start the instruction pipe with MEM_IFPP1              
272
                DEC_IF2       = 6'h03,   //  store the active read in ir1 and start another MEM_IFPP1             
273
                DEC_IF2A      = 6'h04,   //  start a MEM_IFPP1  (but ir1 already has next instruction)            
274
                DEC_EXEC      = 6'h05,   //  PRIME ir1 decode state.  decode first byte of EACH inst here         
275
                DEC_CB        = 6'h06,   //  PRIME decode yields I1_CB        
276
                DEC_DDFD      = 6'h07,   //  PRIME decode yields I1_DDFD  (DD or FD group)          
277
                DEC_ED        = 6'h08,   //  PRIME decode yields I1_ED         
278
                DEC_EDNN1     = 6'h09,   //  Immediate states           
279
                DEC_EDNN2     = 6'h0a,
280
                DEC_EDRD1     = 6'h0b,
281
                DEC_EDRD2     = 6'h0c,
282
                DEC_EDWR      = 6'h0d,
283
                DEC_EDBCP1    = 6'h0e,
284
                DEC_EDBCP2    = 6'h0f,
285
                DEC_EDBCP3    = 6'h10,
286
                DEC_EDBIN1    = 6'h11,
287
                DEC_EDBIN2    = 6'h12,
288
                DEC_EDBIN3    = 6'h13,
289
                DEC_EDBOUT1   = 6'h14,
290
                DEC_EDBOUT2   = 6'h15,
291
                DEC_EDBOUT3   = 6'h16,
292
                DEC_EDBMV1    = 6'h17,
293
                DEC_EDBMV2    = 6'h18,
294
                DEC_EDBMV3    = 6'h19,
295
                DEC_N         = 6'h1a,  //  PRIME decode yields DEC_N  (next byte is immediate data byte)
296
                DEC_NIN       = 6'h1b,
297
                DEC_NN        = 6'h1c,  //  PRIME decode yields DEC_NN (2 immediate data bytes follow)
298
                DEC_NNCALL1   = 6'h1d,
299
                DEC_NNCALL2   = 6'h1e,
300
                DEC_NNOS1     = 6'h1f,
301
                DEC_NNOS2     = 6'h20,
302
                DEC_NNOS3     = 6'h21,
303
                DEC_NNOF1     = 6'h22,
304
                DEC_NNOF2     = 6'h23,
305
                DEC_NNOF3     = 6'h24,
306
                DEC_NNOF4     = 6'h25,
307
                DEC_DDOS      = 6'h26,
308
                DEC_DDOF      = 6'h27,
309
                DEC_OF        = 6'h28,  //  PRIME decode yields  I1_OF  
310
                DEC_POP       = 6'h29,  //  PRIME decode yields  I1_POP
311
                DEC_PUSH      = 6'h2a,  //  PRIME decode yields  I1_PUSH
312
                DEC_RMW       = 6'h2b,  //  PRIME decode yields  I1_RMW
313
                DEC_RMW2      = 6'h2c,
314
                DEC_CBM       = 6'h2d,
315
                DEC_PFxCB     = 6'h2e,
316
                DEC_PFxCB2    = 6'h2f,
317
                DEC_PFxCB3    = 6'h30,
318
                DEC_PFxCB4    = 6'h31,
319
                DEC_INT1      = 6'h32,
320
                DEC_INT2      = 6'h33,
321
                DEC_INT3      = 6'h34,
322
                DEC_INT4      = 6'h35,
323
                DEC_INT5      = 6'h36,
324
                DEC_RET       = 6'h37,  //  PRIME decode yields
325
                DEC_NNJMP     = 6'h38,
326
                DEC_DDN       = 6'h39,
327
                DEC_RET2      = 6'h3a,
328
                DEC_EXSPHL    = 6'h3b,
329
                DEC_RMWDD1    = 6'h3c,
330
                DEC_RMWDD2    = 6'h3d,
331
                DEC_INT6      = 6'h3e ;
332
//  initial decode assignemnts.   These assignemens are made to wires on an initial decode
333
//  to help document next state transitions
334
parameter      I1_CB    = 4'h0,
335
               I1_DDFD  = 4'h1,
336
               I1_ED    = 4'h2,
337
               I1_JMP   = 4'h3,
338
               I1_N     = 4'h4,
339
               I1_NN    = 4'h5,
340
               I1_OF    = 4'h6,
341
               I1_OS    = 4'h7,
342
               I1_POP   = 4'h8,
343
               I1_PUSH  = 4'h9,
344
               I1_RET   = 4'ha,
345
               I1_RMW   = 4'hb,
346
               I1_RST   = 4'hc,
347
               I1_R2R   = 4'hd,
348
               I1_JMPR  = 4'he,
349
               I1_HALT  = 4'hf;
350
 
351
 
352
// A note here on the choices of mnemonics.....   in general, the target registers of 
353
// memory ops are specified by an instruction register  (ir1 for stores ir2 for loads).
354
// so Menomics in general are specifying the address source.   However, there are exceptions.
355
//
356
parameter       MEM_NOP      = 5'h00,
357
                MEM_IFPP1    = 5'h01,
358
                MEM_OS1      = 5'h02,      //  only invoked on I1 OS  multiple address sources and data sources
359
                MEM_OF1      = 5'h03,     //  Address from HL  unless   LD A,(BC) or LD A,(DE)  (used for rmw)
360
                MEM_OFSP     = 5'h04,     //  works for both POP and RET 
361
                MEM_OSSP     = 5'h05,     //  if DEC_EXEC  op from ir1  else msb nn  (implies we store from lsb nn)
362
                                          //  used in CALL also.  
363
                MEM_OFIXpD   = 5'h06,     //  used for prefix op fetches  - all single bytes
364
                MEM_OSIXpD   = 5'h07,     //  data source is same as MEM_OS1
365
                MEM_OSADR    = 5'h08,     //  used (at lesat)  for prefixed rmw --  perhaps others.
366
 
367
                MEM_CALL     = 5'h09,     // pc<=nn, nn<=pc, wb_adr_o<=sp   OS 
368
                MEM_OSNN     = 5'h0a,     //  if DEC_EXEC  op from ir1  else msb nn
369
                MEM_OFNN     = 5'h0b,     // striaghtfoward
370
                MEM_OFADRP1  = 5'h0c,     // used (at least) when double ops above
371
                MEM_OSADRP1  = 5'h0d,     //  ""              ""              ""
372
 
373
                MEM_RST     = 5'h0e,     // 
374
                MEM_REL2PC  = 5'h0f,     // special address transfer for jmp rel
375
                MEM_JMPHL    = 5'h10,     // another special jump transfer
376
                MEM_IFNN     = 5'h11,        //  used by call and return
377
 
378
 
379
                MEM_OFHL_PM  = 5'h12,             // special block move ops  
380
                MEM_OSHL_PM  = 5'h13,             // special block move ops
381
                MEM_OSDE_PM  = 5'h14,             // special block move ops
382
 
383
                MEM_IOF_C    = 5'h15,             // special i/o ops
384
                MEM_IOS_C    = 5'h16,             // operand is ar
385
                MEM_IOF_N    = 5'h17,
386
                MEM_IOS_N    = 5'h18,
387
                MEM_OS_HL_N  = 5'h19,
388
 
389
                MEM_OSSP_PCM2 = 5'h1a,              // int code  (call 
390
                //MEM_OSSP_P   = 5'h1b,              //
391
                MEM_INTA     = 5'h1c,
392
                MEM_IFINT    = 5'h1d,
393
                MEM_DECPC    = 5'h1e ;
394
 
395
 
396
 
397
 
398
 
399
 
400
 
401
 
402
 
403
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0
404
 
405
 
406
wire        cb_mem;
407
wire        wb_rdy_nhz;
408
wire        dec_blk_inc;
409
wire        we_next;
410
wire        hazard;
411
wire        wb_int;
412
wire [15:0] hl, de, bc;
413
wire [3:0]  mem_exec_dec;
414
 
415
// don't forget that as 1r1 is executed it is transferred to ir2.  Anything I need to know
416
// about subsequent operations must be stored.
417
//               6              5              4                15
418
// assign {next_dec_state, next_mem_state, next_pipe_state} = next_state;
419
wire  [5:0]        next_dec_state;
420
wire  [4:0]        next_mem_state;
421
wire  [3:0]        next_pipe_state;
422
wire               ed_dbl_rd;
423
wire  [15:0]       hl_or_ixiy;
424
 
425
// hharte
426
wire ed_blk_mv;
427
wire ed_blk_in;
428
wire ed_blk_out;
429
wire  [15:0] mux21;
430
 
431
//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0
432
 
433
reg [15:0]   pc;
434
reg [15:0]   sp;
435
reg [15:0]   wb_adr_o;
436
reg          wb_we_o;
437
reg          wb_cyc_o;
438
reg          wb_stb_o;
439
//reg          wb_lock; Not used (yet  -- don't delete) 
440
reg [1:0]    wb_tga_o;
441
 
442
reg          blk_inc_flg;
443
reg [9:0]    ir1, ir2;
444
reg          ir1dd, ir2dd;
445
reg          ir1fd, ir2fd;
446
reg [15:0]   nn;
447
 
448
reg   [14:0]       next_state;      // a wire assigned in an alowys loop.
449
 
450
reg   [5:0]  dec_state;    // the register set each clock from next_dec_state;
451
 
452
//reg          of16_reg,  os16_reg, rmw8_reg, call_reg, ret_reg, ioi;
453
//reg          push_reg;
454
//reg          pop_reg;
455
reg          inst_haz;
456
reg          exec_ir2;
457
reg          blk_rpt_flg;
458
reg          blk_io_flg;
459
reg          flag_os1;
460
reg          int_en, en_int_next;
461
reg          wb_irq_sync;
462
reg          ex_tos_hl;    // special flag to help implement EXs6SP7_HL
463
//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
464
//
465
// ir is 10 bits most significant codes ir1[9:8] = { EDgrp, CBgrp }  DDgrp and FDgrp are modifiers
466
 
467
assign  blk_mv_upd_hl = next_mem_state == MEM_OFHL_PM & wb_rdy_nhz|
468
                        next_mem_state == MEM_OSHL_PM & wb_rdy_nhz ;
469
assign  blk_mv_upd_de = next_mem_state == MEM_OSDE_PM & wb_rdy_nhz;
470
// this term not active for compairs as it mucks with flag register in a "blk_mv" way.
471
// we use exec_ir2 to do everything  in blk compairs - on the inst_exec file.  
472
assign  exec_decbc =  (dec_state == DEC_ED) & (  ed_blk_mv) & wb_rdy_nhz |
473
                      (dec_state == DEC_EDBMV3)   & wb_rdy_nhz           ;
474
 
475
assign  exec_decb = (dec_state == DEC_ED) & ( ed_blk_in | ed_blk_out) & wb_rdy_nhz|
476
                    (dec_state == DEC_EDBIN3)    & wb_rdy_nhz                     |
477
                    (dec_state == DEC_EDBOUT3)   & wb_rdy_nhz                      ;
478
assign wb_dat_o = nn[15:8];
479
 
480
wire   sf, zf, f5f, hf, f3f, pvf, nf, cf;
481
assign { sf, zf, f5f, hf, f3f, pvf, nf, cf} = fr;  //  no load on f5f, f3f  ok  hf nf used in inst_exec.v
482
 
483
 
484
assign hl = {hr, lr};
485
assign de = {dr, er};
486
assign bc = {br, cr};
487
 
488
assign hl_or_ixiy = ir1dd ? ixr :
489
                    ir1fd ? iyr :
490
                            hl   ;
491
//  this "groups" the instructions to determine first memory operation
492
 
493
parameter  I1DCNT = 4;  // parameter used below simply to make possible change easier.
494
assign mem_exec_dec =
495
    {I1DCNT {CBgrp        == ir1}} & I1_CB  |//       CBgrp is rotates and bi
496
    {I1DCNT {DDgrp        == ir1}} & I1_DDFD|//      DDgrp   
497
    {I1DCNT {FDgrp        == ir1}} & I1_DDFD|//      FDgrp          FD
498
    {I1DCNT {EDgrp        == ir1}} & I1_ED  |//      EDgrp          ED
499
    {I1DCNT {JPsHL        == ir1}} & I1_JMP |//      JP HL        ; E9 // doc
500
    {I1DCNT {ADCsA_N      == ir1}} & I1_N   |//      ADC A,N      ; CE XX
501
    {I1DCNT {ADDsA_N      == ir1}} & I1_N   |//      ADD A,N      ; C6 XX
502
    {I1DCNT {ANDsN        == ir1}} & I1_N   |//      AND N        ; E6 XX
503
    {I1DCNT {CPsN         == ir1}} & I1_N   |//      CP N         ; FE XX
504
    {I1DCNT {INsA_6N7     == ir1}} & I1_N   |//      IN A,(N)     ; DB XX
505
    {I1DCNT {JRs$t2       == ir1}} & I1_JMPR|//      JR $+2       ; 18 XX
506
    {I1DCNT {JRsC_$t2     == ir1}} & I1_JMPR|//      JR C,$+2     ; 38 XX
507
    {I1DCNT {JRsNC_$t2    == ir1}} & I1_JMPR|//      JR NC,$+2    ; 30 XX
508
    {I1DCNT {JRsZ_$t2     == ir1}} & I1_JMPR|//      JR Z,$+2     ; 28 XX
509
    {I1DCNT {JRsNZ_$t2    == ir1}} & I1_JMPR|//      JR NZ,$+2    ; 20 XX
510
    {I1DCNT {LDs6HL7_N    == ir1}} & I1_N   |//      LD (HL),N    ; 36 XX
511
    {I1DCNT {LDsA_N       == ir1}} & I1_N   |//      LD A,N       ; 3E XX
512
    {I1DCNT {LDsB_N       == ir1}} & I1_N   |//      LD B,N       ; 06 XX
513
    {I1DCNT {LDsC_N       == ir1}} & I1_N   |//      LD C,N       ; 0E XX
514
    {I1DCNT {LDsD_N       == ir1}} & I1_N   |//      LD D,N       ; 16 XX
515
    {I1DCNT {LDsE_N       == ir1}} & I1_N   |//      LD E,N       ; 1E XX
516
    {I1DCNT {LDsH_N       == ir1}} & I1_N   |//      LD H,N       ; 26 XX
517
    {I1DCNT {LDsL_N       == ir1}} & I1_N   |//      LD L,N       ; 2E XX
518
    {I1DCNT {ORsN         == ir1}} & I1_N   |//      OR N         ; F6 XX
519
    {I1DCNT {OUTs6N7_A    == ir1}} & I1_N   |//      OUT (N),A    ; D3 XX
520
    {I1DCNT {SBCsA_N      == ir1}} & I1_N   |//      SBC A,N      ; DE XX
521
    {I1DCNT {SUBsN        == ir1}} & I1_N   |//      SUB N        ; D6 XX
522
    {I1DCNT {XORsN        == ir1}} & I1_N   |//      XOR N        ; EE XX
523
    {I1DCNT {CALLsC_NN    == ir1}} & I1_NN  |//      CALL C,NN    ; DC XX XX
524
    {I1DCNT {CALLsNC_NN   == ir1}} & I1_NN  |//      CALL NC,NN   ; D4 XX XX
525
    {I1DCNT {CALLsNN      == ir1}} & I1_NN  |//      CALL NN      ; CD XX XX
526
    {I1DCNT {CALLsNZ_NN   == ir1}} & I1_NN  |//      CALL NZ,NN   ; C4 XX XX
527
    {I1DCNT {CALLsPE_NN   == ir1}} & I1_NN  |//      CALL PE,NN   ; EC XX XX
528
    {I1DCNT {CALLsPO_NN   == ir1}} & I1_NN  |//      CALL PO,NN   ; E4 XX XX
529
    {I1DCNT {CALLsP_NN    == ir1}} & I1_NN  |//      CALL P,NN    ; F4 XX XX
530
    {I1DCNT {CALLsZ_NN    == ir1}} & I1_NN  |//      CALL Z,NN    ; CC XX XX
531
    {I1DCNT {CALLsM_NN    == ir1}} & I1_NN  |//      CALL M,NN    ; FC XX XX
532
    {I1DCNT {JP           == ir1}} & I1_NN  |//      JP           ; C3 XX XX
533
    {I1DCNT {JPsC         == ir1}} & I1_NN  |//      JP C         ; DA XX XX
534
    {I1DCNT {JPsM         == ir1}} & I1_NN  |//      JP M,        ; FA XX XX
535
    {I1DCNT {JPsNC        == ir1}} & I1_NN  |//      JP NC,       ; D2 XX XX
536
    {I1DCNT {JPsNZ        == ir1}} & I1_NN  |//      JP NZ        ; C2 XX XX
537
    {I1DCNT {JPsP         == ir1}} & I1_NN  |//      JP P         ; F2 XX XX
538
    {I1DCNT {JPsPE        == ir1}} & I1_NN  |//      JP PE,       ; EA XX XX
539
    {I1DCNT {JPsPO        == ir1}} & I1_NN  |//      JP PO        ; E2 XX XX
540
    {I1DCNT {JPsZ         == ir1}} & I1_NN  |//      JP Z         ; CA XX XX
541
    {I1DCNT {LDs6NN7_A    == ir1}} & I1_NN  |//      LD (NN),A    ; 32 XX XX
542
    {I1DCNT {LDs6NN7_HL   == ir1}} & I1_NN  |//      LD (NN),HL   ; 22 XX XX
543
    {I1DCNT {LDsA_6NN7    == ir1}} & I1_NN  |//      LD A,(NN)    ; 3A XX XX
544
    {I1DCNT {LDsBC_NN     == ir1}} & I1_NN  |//      LD BC,NN     ; 01 XX XX
545
    {I1DCNT {LDsDE_NN     == ir1}} & I1_NN  |//      LD DE,NN     ; 11 XX XX
546
    {I1DCNT {LDsHL_6NN7   == ir1}} & I1_NN  |//      LD HL,(NN)   ; 2A XX XX
547
    {I1DCNT {LDsHL_NN     == ir1}} & I1_NN  |//      LD HL,NN     ; 21 XX XX
548
    {I1DCNT {LDsSP_NN     == ir1}} & I1_NN  |//      LD SP,NN     ; 31 XX XX
549
    {I1DCNT {ADCsA_6HL7   == ir1}} & I1_OF  |//      ADC A,(HL)   ; 8E
550
    {I1DCNT {ADDsA_6HL7   == ir1}} & I1_OF  |//      ADD A,(HL)   ; 86
551
    {I1DCNT {ANDs6HL7     == ir1}} & I1_OF  |//      AND (HL)     ; A6
552
    {I1DCNT {CPs6HL7      == ir1}} & I1_OF  |//      CP (HL)      ; BE
553
    {I1DCNT {LDsA_6BC7    == ir1}} & I1_OF  |//      LD A,(BC)    ; 0A
554
    {I1DCNT {LDsA_6DE7    == ir1}} & I1_OF  |//      LD A,(DE)    ; 1A
555
    {I1DCNT {LDsA_6HL7    == ir1}} & I1_OF  |//      LD A,(HL)    ; 7E
556
    {I1DCNT {LDsB_6HL7    == ir1}} & I1_OF  |//      LD B,(HL)    ; 46
557
    {I1DCNT {LDsC_6HL7    == ir1}} & I1_OF  |//      LD C,(HL)    ; 4E
558
    {I1DCNT {LDsD_6HL7    == ir1}} & I1_OF  |//      LD D,(HL)    ; 56
559
    {I1DCNT {LDsE_6HL7    == ir1}} & I1_OF  |//      LD E,(HL)    ; 5E
560
    {I1DCNT {LDsH_6HL7    == ir1}} & I1_OF  |//      LD H,(HL)    ; 66
561
    {I1DCNT {LDsL_6HL7    == ir1}} & I1_OF  |//      LD L,(HL)    ; 6E
562
    {I1DCNT {ORs6HL7      == ir1}} & I1_OF  |//      OR (HL)      ; B6
563
    {I1DCNT {SBCs6HL7     == ir1}} & I1_OF  |//      SBC (HL)     ; 9E
564
    {I1DCNT {SUBs6HL7     == ir1}} & I1_OF  |//      SUB (HL)     ; 96
565
    {I1DCNT {XORs6HL7     == ir1}} & I1_OF  |//      XOR (HL)     ; AE
566
    {I1DCNT {LDs6BC7_A    == ir1}} & I1_OS  |//      LD (BC),A    ; 02 
567
    {I1DCNT {LDs6DE7_A    == ir1}} & I1_OS  |//      LD (DE),A    ; 12
568
    {I1DCNT {LDs6HL7_A    == ir1}} & I1_OS  |//      LD (HL),A    ; 77
569
    {I1DCNT {LDs6HL7_B    == ir1}} & I1_OS  |//      LD (HL),B    ; 70
570
    {I1DCNT {LDs6HL7_C    == ir1}} & I1_OS  |//      LD (HL),C    ; 71
571
    {I1DCNT {LDs6HL7_D    == ir1}} & I1_OS  |//      LD (HL),D    ; 72
572
    {I1DCNT {LDs6HL7_E    == ir1}} & I1_OS  |//      LD (HL),E    ; 73
573
    {I1DCNT {LDs6HL7_H    == ir1}} & I1_OS  |//      LD (HL),H    ; 74
574
    {I1DCNT {LDs6HL7_L    == ir1}} & I1_OS  |//      LD (HL),L    ; 75
575
    {I1DCNT {POPsAF       == ir1}} & I1_POP |//      POP AF       ; F1
576
    {I1DCNT {POPsBC       == ir1}} & I1_POP |//      POP BC       ; C1
577
    {I1DCNT {POPsDE       == ir1}} & I1_POP |//      POP DE       ; D1
578
    {I1DCNT {POPsHL       == ir1}} & I1_POP |//      POP HL       ; E1
579
    {I1DCNT {PUSHsAF      == ir1}} & I1_PUSH|//      PUSH AF      ; F5
580
    {I1DCNT {PUSHsBC      == ir1}} & I1_PUSH|//      PUSH BC      ; C5
581
    {I1DCNT {PUSHsDE      == ir1}} & I1_PUSH|//      PUSH DE      ; D5
582
    {I1DCNT {PUSHsHL      == ir1}} & I1_PUSH|//      PUSH HL      ; E5
583
    {I1DCNT {ADCsA_A      == ir1}} & I1_R2R |//      ADC A,A      ; 8F
584
    {I1DCNT {ADCsA_B      == ir1}} & I1_R2R |//      ADC A,B      ; 88
585
    {I1DCNT {ADCsA_C      == ir1}} & I1_R2R |//      ADC A,C      ; 89
586
    {I1DCNT {ADCsA_D      == ir1}} & I1_R2R |//      ADC A,D      ; 8A
587
    {I1DCNT {ADCsA_E      == ir1}} & I1_R2R |//      ADC A,E      ; 8B
588
    {I1DCNT {ADCsA_H      == ir1}} & I1_R2R |//      ADC A,H      ; 8C
589
    {I1DCNT {ADCsA_L      == ir1}} & I1_R2R |//      ADC A,L      ; 8D
590
    {I1DCNT {ADDsA_A      == ir1}} & I1_R2R |//      ADD A,A      ; 87
591
    {I1DCNT {ADDsA_B      == ir1}} & I1_R2R |//      ADD A,B      ; 80
592
    {I1DCNT {ADDsA_C      == ir1}} & I1_R2R |//      ADD A,C      ; 81
593
    {I1DCNT {ADDsA_D      == ir1}} & I1_R2R |//      ADD A,D      ; 82
594
    {I1DCNT {ADDsA_E      == ir1}} & I1_R2R |//      ADD A,E      ; 83
595
    {I1DCNT {ADDsA_H      == ir1}} & I1_R2R |//      ADD A,H      ; 84
596
    {I1DCNT {ADDsA_L      == ir1}} & I1_R2R |//      ADD A,L      ; 85
597
    {I1DCNT {ADDsHL_BC    == ir1}} & I1_R2R |//      ADD HL,BC    ; 09
598
    {I1DCNT {ADDsHL_DE    == ir1}} & I1_R2R |//      ADD HL,DE    ; 19
599
    {I1DCNT {ADDsHL_HL    == ir1}} & I1_R2R |//      ADD HL,HL    ; 29
600
    {I1DCNT {ADDsHL_SP    == ir1}} & I1_R2R |//      ADD HL,SP    ; 39
601
    {I1DCNT {ANDsA        == ir1}} & I1_R2R |//      AND A        ; A7
602
    {I1DCNT {ANDsB        == ir1}} & I1_R2R |//      AND B        ; A0
603
    {I1DCNT {ANDsC        == ir1}} & I1_R2R |//      AND C        ; A1
604
    {I1DCNT {ANDsD        == ir1}} & I1_R2R |//      AND D        ; A2
605
    {I1DCNT {ANDsE        == ir1}} & I1_R2R |//      AND E        ; A3
606
    {I1DCNT {ANDsH        == ir1}} & I1_R2R |//      AND H        ; A4
607
    {I1DCNT {ANDsL        == ir1}} & I1_R2R |//      AND L        ; A5
608
    {I1DCNT {CCF          == ir1}} & I1_R2R |//      CCF          ; 3F
609
    {I1DCNT {CPL          == ir1}} & I1_R2R |//      CPL          ; 2F
610
    {I1DCNT {CPsA         == ir1}} & I1_R2R |//      CP A         ; BF
611
    {I1DCNT {CPsB         == ir1}} & I1_R2R |//      CP B         ; B8
612
    {I1DCNT {CPsC         == ir1}} & I1_R2R |//      CP C         ; B9
613
    {I1DCNT {CPsD         == ir1}} & I1_R2R |//      CP D         ; BA
614
    {I1DCNT {CPsE         == ir1}} & I1_R2R |//      CP E         ; BB
615
    {I1DCNT {CPsH         == ir1}} & I1_R2R |//      CP H         ; BC
616
    {I1DCNT {CPsL         == ir1}} & I1_R2R |//      CP L         ; BD
617
    {I1DCNT {DAA          == ir1}} & I1_R2R |//      DAA          ; 27
618
    {I1DCNT {DECsA        == ir1}} & I1_R2R |//      DEC A        ; 3D
619
    {I1DCNT {DECsB        == ir1}} & I1_R2R |//      DEC B        ; 05
620
    {I1DCNT {DECsBC       == ir1}} & I1_R2R |//      DEC BC       ; 0B
621
    {I1DCNT {DECsC        == ir1}} & I1_R2R |//      DEC C        ; 0D
622
    {I1DCNT {DECsD        == ir1}} & I1_R2R |//      DEC D        ; 15
623
    {I1DCNT {DECsDE       == ir1}} & I1_R2R |//      DEC DE       ; 1B
624
    {I1DCNT {DECsE        == ir1}} & I1_R2R |//      DEC E        ; 1D
625
    {I1DCNT {DECsH        == ir1}} & I1_R2R |//      DEC H        ; 25
626
    {I1DCNT {DECsHL       == ir1}} & I1_R2R |//      DEC HL       ; 2B
627
    {I1DCNT {DECsL        == ir1}} & I1_R2R |//      DEC L        ; 2D
628
    {I1DCNT {DECsSP       == ir1}} & I1_R2R |//      DEC SP       ; 3B
629
    {I1DCNT {DI           == ir1}} & I1_R2R |//      DI           ; F3
630
    {I1DCNT {DJNZs$t2     == ir1}} & I1_JMPR|//      DJNZ $+2     ; 10 XX
631
    {I1DCNT {EI           == ir1}} & I1_R2R |//      EI           ; FB
632
    {I1DCNT {EXX          == ir1}} & I1_R2R |//      EXX          ; D9
633
    {I1DCNT {EXsAF_AFp    == ir1}} & I1_R2R |//      EX AF,AF'    ; 08
634
    {I1DCNT {EXsDE_HL     == ir1}} & I1_R2R |//      EX DE,HL     ; EB
635
    {I1DCNT {HALT         == ir1}} & I1_HALT |//      HALT         ; 76
636
    {I1DCNT {INCsA        == ir1}} & I1_R2R |//      INC A        ; 3C
637
    {I1DCNT {INCsB        == ir1}} & I1_R2R |//      INC B       ; 04
638
    {I1DCNT {INCsBC       == ir1}} & I1_R2R |//      INC BC      ; 03
639
    {I1DCNT {INCsC        == ir1}} & I1_R2R |//      INC C       ; 0C
640
    {I1DCNT {INCsD        == ir1}} & I1_R2R |//      INC D        ; 14
641
    {I1DCNT {INCsDE       == ir1}} & I1_R2R |//      INC DE       ; 13
642
    {I1DCNT {INCsE        == ir1}} & I1_R2R |//      INC E        ; 1C
643
    {I1DCNT {INCsH        == ir1}} & I1_R2R |//      INC H        ; 24
644
    {I1DCNT {INCsHL       == ir1}} & I1_R2R |//      INC HL       ; 23
645
    {I1DCNT {INCsL        == ir1}} & I1_R2R |//      INC L        ; 2C
646
    {I1DCNT {INCsSP       == ir1}} & I1_R2R |//      INC SP       ; 33
647
    {I1DCNT {LDsA_A       == ir1}} & I1_R2R |//      LD A,A       ; 7F
648
    {I1DCNT {LDsA_B       == ir1}} & I1_R2R |//      LD A,B       ; 78
649
    {I1DCNT {LDsA_C       == ir1}} & I1_R2R |//      LD A,C       ; 79
650
    {I1DCNT {LDsA_D       == ir1}} & I1_R2R |//      LD A,D       ; 7A
651
    {I1DCNT {LDsA_E       == ir1}} & I1_R2R |//      LD A,E       ; 7B
652
    {I1DCNT {LDsA_H       == ir1}} & I1_R2R |//      LD A,H       ; 7C
653
    {I1DCNT {LDsA_L       == ir1}} & I1_R2R |//      LD A,L       ; 7D
654
    {I1DCNT {LDsB_A       == ir1}} & I1_R2R |//      LD B,A       ; 47
655
    {I1DCNT {LDsB_B       == ir1}} & I1_R2R |//      LD B,B       ; 40
656
    {I1DCNT {LDsB_C       == ir1}} & I1_R2R |//      LD B,C       ; 41
657
    {I1DCNT {LDsB_D       == ir1}} & I1_R2R |//      LD B,D       ; 42
658
    {I1DCNT {LDsB_E       == ir1}} & I1_R2R |//      LD B,E       ; 43
659
    {I1DCNT {LDsB_H       == ir1}} & I1_R2R |//      LD B,H       ; 44
660
    {I1DCNT {LDsB_L       == ir1}} & I1_R2R |//      LD B,L       ; 45
661
    {I1DCNT {LDsC_A       == ir1}} & I1_R2R |//      LD C,A       ; 4F
662
    {I1DCNT {LDsC_B       == ir1}} & I1_R2R |//      LD C,B       ; 48
663
    {I1DCNT {LDsC_C       == ir1}} & I1_R2R |//      LD C,C       ; 49
664
    {I1DCNT {LDsC_D       == ir1}} & I1_R2R |//      LD C,D       ; 4A
665
    {I1DCNT {LDsC_E       == ir1}} & I1_R2R |//      LD C,E       ; 4B
666
    {I1DCNT {LDsC_H       == ir1}} & I1_R2R |//      LD C,H       ; 4C
667
    {I1DCNT {LDsC_L       == ir1}} & I1_R2R |//      LD C,L       ; 4D
668
    {I1DCNT {LDsD_A       == ir1}} & I1_R2R |//      LD D,A       ; 57
669
    {I1DCNT {LDsD_B       == ir1}} & I1_R2R |//      LD D,B       ; 50
670
    {I1DCNT {LDsD_C       == ir1}} & I1_R2R |//      LD D,C       ; 51
671
    {I1DCNT {LDsD_D       == ir1}} & I1_R2R |//      LD D,D       ; 52
672
    {I1DCNT {LDsD_E       == ir1}} & I1_R2R |//      LD D,E       ; 53
673
    {I1DCNT {LDsD_H       == ir1}} & I1_R2R |//      LD D,H       ; 54
674
    {I1DCNT {LDsD_L       == ir1}} & I1_R2R |//      LD D,L       ; 55
675
    {I1DCNT {LDsE_A       == ir1}} & I1_R2R |//      LD E,A       ; 5F
676
    {I1DCNT {LDsE_B       == ir1}} & I1_R2R |//      LD E,B       ; 58
677
    {I1DCNT {LDsE_C       == ir1}} & I1_R2R |//      LD E,C       ; 59
678
    {I1DCNT {LDsE_D       == ir1}} & I1_R2R |//      LD E,D       ; 5A
679
    {I1DCNT {LDsE_E       == ir1}} & I1_R2R |//      LD E,E       ; 5B
680
    {I1DCNT {LDsE_H       == ir1}} & I1_R2R |//      LD E,H       ; 5C
681
    {I1DCNT {LDsE_L       == ir1}} & I1_R2R |//      LD E,L       ; 5D
682
    {I1DCNT {LDsH_A       == ir1}} & I1_R2R |//      LD H,A       ; 67
683
    {I1DCNT {LDsH_B       == ir1}} & I1_R2R |//      LD H,B       ; 60
684
    {I1DCNT {LDsH_C       == ir1}} & I1_R2R |//      LD H,C       ; 61
685
    {I1DCNT {LDsH_D       == ir1}} & I1_R2R |//      LD H,D       ; 62
686
    {I1DCNT {LDsH_E       == ir1}} & I1_R2R |//      LD H,E       ; 63
687
    {I1DCNT {LDsH_H       == ir1}} & I1_R2R |//      LD H,H       ; 64
688
    {I1DCNT {LDsH_L       == ir1}} & I1_R2R |//      LD H,L       ; 65
689
    {I1DCNT {LDsL_A       == ir1}} & I1_R2R |//      LD L,A       ; 6F
690
    {I1DCNT {LDsL_B       == ir1}} & I1_R2R |//      LD L,B       ; 68
691
    {I1DCNT {LDsL_C       == ir1}} & I1_R2R |//      LD L,C       ; 69
692
    {I1DCNT {LDsL_D       == ir1}} & I1_R2R |//      LD L,D       ; 6A
693
    {I1DCNT {LDsL_E       == ir1}} & I1_R2R |//      LD L,E       ; 6B
694
    {I1DCNT {LDsL_H       == ir1}} & I1_R2R |//      LD L,H       ; 6C
695
    {I1DCNT {LDsL_L       == ir1}} & I1_R2R |//      LD L,L       ; 6D
696
    {I1DCNT {LDsSP_HL     == ir1}} & I1_R2R |//      LD SP,HL     ; F9
697
    {I1DCNT {NOP          == ir1}} & I1_R2R |//      NOP         ; 00
698
    {I1DCNT {ORsA         == ir1}} & I1_R2R |//      OR A         ; B7
699
    {I1DCNT {ORsB         == ir1}} & I1_R2R |//      OR B         ; B0
700
    {I1DCNT {ORsC         == ir1}} & I1_R2R |//      OR C         ; B1
701
    {I1DCNT {ORsD         == ir1}} & I1_R2R |//      OR D         ; B2
702
    {I1DCNT {ORsE         == ir1}} & I1_R2R |//      OR E         ; B3
703
    {I1DCNT {ORsH         == ir1}} & I1_R2R |//      OR H         ; B4
704
    {I1DCNT {ORsL         == ir1}} & I1_R2R |//      OR L         ; B5
705
    {I1DCNT {RLA          == ir1}} & I1_R2R |//      RLA          ; 17
706
    {I1DCNT {RLCA         == ir1}} & I1_R2R |//      RLCA        ; 07
707
    {I1DCNT {RRA          == ir1}} & I1_R2R |//      RRA          ; 1F
708
    {I1DCNT {RRCA         == ir1}} & I1_R2R |//      RRCA        ; 0F
709
    {I1DCNT {SBCsA        == ir1}} & I1_R2R |//      SBC A        ; 9F
710
    {I1DCNT {SBCsB        == ir1}} & I1_R2R |//      SBC B        ; 98
711
    {I1DCNT {SBCsC        == ir1}} & I1_R2R |//      SBC C        ; 99
712
    {I1DCNT {SBCsD        == ir1}} & I1_R2R |//      SBC D        ; 9A
713
    {I1DCNT {SBCsE        == ir1}} & I1_R2R |//      SBC E        ; 9B
714
    {I1DCNT {SBCsH        == ir1}} & I1_R2R |//      SBC H        ; 9C
715
    {I1DCNT {SBCsL        == ir1}} & I1_R2R |//      SBC L        ; 9D
716
    {I1DCNT {SCF          == ir1}} & I1_R2R |//      SCF          ; 37
717
    {I1DCNT {SUBsA        == ir1}} & I1_R2R |//      SUB A        ; 97
718
    {I1DCNT {SUBsB        == ir1}} & I1_R2R |//      SUB B        ; 90
719
    {I1DCNT {SUBsC        == ir1}} & I1_R2R |//      SUB C        ; 91
720
    {I1DCNT {SUBsD        == ir1}} & I1_R2R |//      SUB D        ; 92
721
    {I1DCNT {SUBsE        == ir1}} & I1_R2R |//      SUB E        ; 93
722
    {I1DCNT {SUBsH        == ir1}} & I1_R2R |//      SUB H        ; 94
723
    {I1DCNT {SUBsL        == ir1}} & I1_R2R |//      SUB L        ; 95
724
    {I1DCNT {XORsA        == ir1}} & I1_R2R |//      XOR A        ; AF
725
    {I1DCNT {XORsB        == ir1}} & I1_R2R |//      XOR B        ; A8
726
    {I1DCNT {XORsC        == ir1}} & I1_R2R |//      XOR C        ; A9
727
    {I1DCNT {XORsD        == ir1}} & I1_R2R |//      XOR D        ; AA
728
    {I1DCNT {XORsE        == ir1}} & I1_R2R |//      XOR E        ; AB
729
    {I1DCNT {XORsH        == ir1}} & I1_R2R |//      XOR H        ; AC
730
    {I1DCNT {XORsL        == ir1}} & I1_R2R |//      XOR L        ; AD
731
    {I1DCNT {RET          == ir1}} & I1_RET |//      RET          ; C9
732
    {I1DCNT {RETsC == ir1 & cf  }} & I1_RET |//      RET C        ; D8
733
    {I1DCNT {RETsM == ir1 & sf  }} & I1_RET |//      RET M        ; F8
734
    {I1DCNT {RETsNC== ir1 & ~cf }} & I1_RET |//      RET NC       ; D0
735
    {I1DCNT {RETsP == ir1 & ~sf }} & I1_RET |//      RET P        ; F0
736
    {I1DCNT {RETsPE== ir1 & pvf }} & I1_RET |//      RET PE       ; E8
737
    {I1DCNT {RETsPO== ir1 & ~pvf}} & I1_RET |//      RET PO       ; E0
738
    {I1DCNT {RETsNZ== ir1 & ~zf }} & I1_RET |//      RET NZ       ; C0
739
    {I1DCNT {RETsZ == ir1 & zf  }} & I1_RET |//      RET Z        ; C8
740
 
741
    {I1DCNT {RETsC == ir1 & ~cf }} & I1_R2R |//      RET C        ; D8 r2r should work as all codes 
742
    {I1DCNT {RETsM == ir1 & ~sf }} & I1_R2R |//      RET M        ; F8 should be nop in ir2
743
    {I1DCNT {RETsNC== ir1 & cf  }} & I1_R2R |//      RET NC       ; D0
744
    {I1DCNT {RETsP == ir1 & sf  }} & I1_R2R |//      RET P        ; F0
745
    {I1DCNT {RETsPE== ir1 & ~pvf}} & I1_R2R |//      RET PE       ; E8
746
    {I1DCNT {RETsPO== ir1 & pvf }} & I1_R2R |//      RET PO       ; E0
747
    {I1DCNT {RETsNZ== ir1 & zf  }} & I1_R2R |//      RET NZ       ; C0
748
    {I1DCNT {RETsZ == ir1 & ~zf }} & I1_R2R |//      RET Z        ; C8
749
 
750
    {I1DCNT {EXs6SP7_HL   == ir1}} & I1_POP |//      EX (SP),HL   ; E3
751
    {I1DCNT {DECs6HL7     == ir1}} & I1_RMW |//      DEC (HL)     ; 35
752
    {I1DCNT {INCs6HL7     == ir1}} & I1_RMW |//      INC (HL)     ; 34
753
    {I1DCNT {RSTs0        == ir1}} & I1_RST |//      RST 0        ; C7
754
    {I1DCNT {RSTs10H      == ir1}} & I1_RST |//      RST 10H      ; D7
755
    {I1DCNT {RSTs18H      == ir1}} & I1_RST |//      RST 18H      ; DF
756
    {I1DCNT {RSTs20H      == ir1}} & I1_RST |//      RST 20H      ; E7
757
    {I1DCNT {RSTs28H      == ir1}} & I1_RST |//      RST 28H      ; EF       
758
    {I1DCNT {RSTs30H      == ir1}} & I1_RST |//      RST 30H      ; F7
759
    {I1DCNT {RSTs38H      == ir1}} & I1_RST |//      RST 38H      ; FF
760
    {I1DCNT {RSTs8H       == ir1}} & I1_RST ;//      RST 8H       ; CF 
761
 
762
//--------  CB decodes -----------------------
763
 
764
//  First cut below
765
//           CB_RLC   = 7'b01_00_000,  // these must be compaired with ir[9:3]
766
//           CB_RRC   = 7'b01_00_001,  // these must be compaired with ir[9:3]
767
//           CB_RL    = 7'b01_00_010,  // these must be compaired with ir[9:3]
768
//           CB_RR    = 7'b01_00_011,  // these must be compaired with ir[9:3]
769
//           CB_SLA   = 7'b01_00_100,  // these must be compaired with ir[9:3]
770
//           CB_SRA   = 7'b01_00_101,  // these must be compaired with ir[9:3]
771
//           CB_SLL   = 7'b01_00_110,  // these must be compaired with ir[9:3]
772
//           CB_SRL   = 7'b01_00_111,  // these must be compaired with ir[9:3]
773
 
774
//           CB_BIT   = 4'b01_01,    // these must be compaired with ir[9:6]
775
//           CB_RES   = 4'b01_10,    // these must be compaired with ir[9:6]
776
//           CB_SET   = 4'b01_11,    // these must be compaired with ir[9:6]
777
 
778
// note these are all read-modify-writ except CB_BIT
779
assign cb_mem =  (CB_MEM  == ir1[2:0]);   // this must be compaired with ir[2:0] 
780
 
781
//  The ED Group
782
// These are the "unique instructions in the 46, 47 rows that NEED? to be implemented
783
// Not sure I want to worry about all undocumented stuff in these rows - hard to believe
784
// It will matter.(IM modes are very system dependent  - hard to believe even a programmer
785
// would use undocumented instructions to muck with this stuff)
786
// reg 2 reg simply executed by ir2 logic
787
//           ED_IMs0      =  10'h246//      IM 0       ; ED 46   set IM0
788
//           ED_LDsI_A    =  10'h247//      LD I,A     ; ED 47   move a to I
789
//           ED_IMs1      =  10'h256//      IM 1       ; ED 56   set IM1
790
//           ED_LDsA_I    =  10'h257//      LD A,I     ; ED 57   move I to A
791
//           ED_IMs2      =  10'h25E//      IM 2       ; ED 5E   set IM2
792
//           ED_RRD       =  10'h267//      RRD        ; ED 67   nibble roates A HL
793
//           ED_RLD       =  10'h26F//      RLD        ; ED 6F   nibble roates A HL
794
 
795
//  set (or clear) repeat flag at  DEC_EB.
796
//  set (or clear) inc flag at     DEC_EB.
797
//  seperate flows for LD, CP, IN, OUT.
798
//           ED_LDI       == ir1//      LDI        ; ED A0    These are block move 
799
//           ED_CPI       == ir1//      CPI        ; ED A1    type insts that don't repeat
800
//           ED_INI       == ir1//      INI        ; ED A2
801
//           ED_OUTI      == ir1//      OUTI       ; ED A3
802
//           ED_LDD       == ir1//      LDD        ; ED A8
803
//           ED_CPD       == ir1//      CPD        ; ED A9
804
//           ED_IND       == ir1//      IND        ; ED AA
805
//           ED_OUTD      == ir1//      OUTD       ; ED AB
806
wire dec_blk_rpt =
807
           ED_LDIR      == ir1 |//      LDIR       ; ED B0    These are block move 
808
           ED_CPIR      == ir1 |//      CPIR       ; ED B1    type insts that DO repeat
809
           ED_INIR      == ir1 |//      INIR       ; ED B2
810
           ED_OTIR      == ir1 |//      OTIR       ; ED B3
811
           ED_LDDR      == ir1 |//      LDDR       ; ED B8
812
           ED_CPDR      == ir1 |//      CPDR       ; ED B9
813
           ED_INDR      == ir1 |//      INDR       ; ED BA
814
           ED_OTDR      == ir1 ;//      OTDR       ; ED BB
815
// hharte
816
assign ed_blk_mv =  ED_LDIR      == ir1 |  ED_LDI       == ir1 |
817
                  ED_LDDR      == ir1 |  ED_LDD       == ir1 ;
818
wire ed_blk_cp =  ED_CPIR      == ir1 |  ED_CPI       == ir1 |
819
                  ED_CPDR      == ir1 |  ED_CPD       == ir1 ;
820
assign ed_blk_in =  ED_INIR      == ir1 |  ED_INI      == ir1 |
821
                  ED_INDR      == ir1 |  ED_IND      == ir1 ;
822
 
823
assign ed_blk_out = ED_OTIR      == ir1 |  ED_OUTI      == ir1 |
824
                  ED_OTDR      == ir1 |  ED_OUTD      == ir1 ;
825
 
826
wire dec_blk_io = ed_blk_in | ed_blk_out;
827
 
828
wire blk_done =  ~blk_rpt_flg |  beq0 & ceq0 | blk_io_flg & beq0;
829
wire blk_cpi_done = ~blk_rpt_flg | ({br, cr} == 16'h1);
830
assign dec_blk_inc =  ED_LDIR      == ir1 |
831
                      ED_CPIR      == ir1 |
832
                      ED_INIR      == ir1 |
833
                      ED_OTIR      == ir1 |
834
                      ED_LDI       == ir1 |
835
                      ED_CPI       == ir1 |
836
                      ED_INI       == ir1 |
837
                      ED_OUTI      == ir1 ;
838
 
839
 
840
//The ED70 instruction reads from I/O port C, 
841
//but does not store the result.
842
//It just affects the flags.  Hard to test.    like the other IN x,(C) instruction. 
843
//
844
//ED71 simply outs the value 0 to I/O port C.
845
//  This suggests that we should decode as follows:
846
//  I hope if I don't get all the IM duplicates right it won't be a tragedy
847
//        
848
//        ED_INsREG_6C7  =    7'b1001___000, // compair with {ir[9:6],ir[2:0]}
849
//        ED_OUTs6C7_REG =    7'b1001___001, // compair with {ir[9:6],ir[2:0]}
850
//        ED_SBCsHL_REG  =    8'b1001__0010, // compair with {ir[9:6],ir[3:0]}
851
//        ED_ADCsHL_REG  =    8'b1001__1010, // compair with {ir[9:6],ir[3:0]}
852
//        ED_LDs6NN7_REG =    8'b1001__0011, // compair with {ir[9:6],ir[3:0]}  REG = BC,DE,HL,SP                   
853
//        ED_LDsREG_6NN7 =    8'b1001__1011, // compair with {ir[9:6],ir[3:0]}  REG = BC,DE,HL,SP
854
//        ED_NEG         =    7'b1001___100, // compair with {ir[9:6],ir[2:0]}  all A<= -A                  
855
//        ED_RETN        =    7'b1001___101, // compair with {ir[9:6],ir[2:0]} and !reti
856
 
857
wire ed_in_reg  = ED_INsREG_6C7   ==  {ir1[9:6],ir1[2:0]};
858
wire ed_out_reg = ED_OUTs6C7_REG  ==  {ir1[9:6],ir1[2:0]};
859
 
860
wire ed_nn = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} |
861
             ED_LDsREG_6NN7 == {ir1[9:6],ir1[3:0]}  ;
862
 
863
//  we use all these to enable interrupts
864
wire ed_retn = ED_RETN == {ir1[9:6],ir1[2:0]};
865
wire ed_rmw = ED_RRD == ir1 |  // ED 67   nibble roates A (HL)
866
              ED_RLD == ir1  ; // ED 6F   nibble roates A (HL)
867
 
868
assign ed_dbl_rd =  ED_LDsREG_6NN7 == {ir1[9:6],ir1[3:0]};
869
 
870
 
871
// assign   cb_mem = CB_MEM = ir1[2:0];                 // CB_MEM  = 3'h110,    
872
 
873
 
874
 
875
 
876
wire jmpr_true =
877
    JRs$t2       == ir1           |
878
    JRsC_$t2     == ir1  & fr[0]  |
879
    JRsNC_$t2    == ir1  & ~fr[0] |
880
    JRsZ_$t2     == ir1  & fr[6]  |
881
    JRsNZ_$t2    == ir1  & ~fr[6] |
882
    DJNZs$t2     == ir1  & (br != 8'h1);
883
wire jmpr =
884
    JRs$t2       == ir1   |
885
    JRsC_$t2     == ir1   |
886
    JRsNC_$t2    == ir1   |
887
    JRsZ_$t2     == ir1   |
888
    JRsNZ_$t2    == ir1   |
889
    DJNZs$t2     == ir1;
890
 
891
 
892
//assign { sf, zf. f5f, hf, f3f, pvf, nf, cf} = fr;              
893
wire callnn_true   =  CALLsC_NN    == ir1  & cf  |
894
                      CALLsNC_NN   == ir1  & ~cf |
895
                      CALLsNN      == ir1        |
896
                      CALLsNZ_NN   == ir1  & ~zf |
897
                      CALLsPE_NN   == ir1  & pvf |
898
                      CALLsPO_NN   == ir1  & ~pvf|
899
                      CALLsP_NN    == ir1  & ~sf |
900
                      CALLsZ_NN    == ir1  &  zf |
901
                      CALLsM_NN    == ir1  &  sf  ;
902
 
903
wire  jmpnn_true  =  JPsC         == ir1  & cf  |
904
                     JPsNC        == ir1  & ~cf |
905
                     JP           == ir1        |
906
                     JPsNZ        == ir1  & ~zf |
907
                     JPsPE        == ir1  & pvf |
908
                     JPsPO        == ir1  & ~pvf|
909
                     JPsP         == ir1  & ~sf |
910
                     JPsZ         == ir1  &  zf |
911
                     JPsM         == ir1  &  sf  ;
912
 
913
// PUSHsAF      == ir1
914
// PUSHsBC      == ir1
915
// PUSHsDE      == ir1
916
// PUSHsHL      == ir1
917
 
918
wire os_a  =  LDs6BC7_A    == ir1 |  //      LD (BC),A    ; 02
919
              LDs6DE7_A    == ir1 |  //      LD (DE),A    ; 12
920
              LDs6HL7_A    == ir1 |  //      LD (HL),A    ; 77
921
              LDs6NN7_A    == ir1 |  //      LD (NN),A    ; 32 XX XX
922
              PUSHsAF      == ir1 |
923
              OUTs6N7_A    == ir1 |
924
              (ED_OUTs6C7_REG ==  {ir1[9:6],ir1[2:0]}) & REG8_A == ir1[5:3] ;
925
 
926
wire os_b = LDs6HL7_B      == ir1                                       |  // LD (HL),B    ; 70
927
            ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_BC == ir1[5:4] |
928
            PUSHsBC        == ir1                                       |  // PUSH BC
929
            ED_OUTs6C7_REG ==  {ir1[9:6],ir1[2:0]} & REG8_B == ir1[5:3] ;
930
 
931
wire os_c = LDs6HL7_C    == ir1                                         |  //      LD (HL),C    ; 71
932
            ED_OUTs6C7_REG ==  {ir1[9:6],ir1[2:0]} & REG8_C == ir1[5:3] ;
933
 
934
wire os_d = LDs6HL7_D    == ir1                                         |  //      LD (HL),D    ; 72
935
            PUSHsDE      == ir1                                         |  //      PUSH DE
936
            ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_DE == ir1[5:4] |
937
            ED_OUTs6C7_REG ==  {ir1[9:6],ir1[2:0]} & REG8_D == ir1[5:3] ;
938
 
939
 
940
wire os_e = LDs6HL7_E    == ir1                                     |  //      LD (HL),E    ; 73
941
            ED_OUTs6C7_REG ==  {ir1[9:6],ir1[2:0]} & REG8_E == ir1[5:3] ;
942
 
943
wire os_h = LDs6HL7_H    == ir1                                         |  //      LD (HL),H    ; 74
944
            PUSHsHL      == ir1                                         |  // need this here for hazard detect
945
            ED_OUTs6C7_REG ==  {ir1[9:6],ir1[2:0]} & REG8_H == ir1[5:3] ;
946
 
947
wire os_l = LDs6HL7_L    == ir1                                     |  //      LD (HL),L    ; 75
948
            ED_OUTs6C7_REG ==  {ir1[9:6],ir1[2:0]} & REG8_L == ir1[5:3] ;
949
 
950
 
951
// these need special treatment of nn register, but as each is an NN type, there 
952
// is no risk of a hazard.
953
wire os_bc = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_BC == ir1[5:4];
954
wire os_de = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_DE == ir1[5:4];
955
wire os_sp = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_SP == ir1[5:4];
956
 
957
 
958
wire os_hl =   LDs6NN7_HL   == ir1 & ~(ir1dd | ir2dd)                        |
959
               ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_HL == ir1[5:4] ;
960
 
961
wire os_ixr =  LDs6NN7_HL   == ir1 & ir1dd;
962
wire os_iyr =  LDs6NN7_HL   == ir1 & ir1fd;
963
 
964
 
965
// wire os_sp = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_SP == ir1[5:4]; not used ?
966
 
967
// wire os_f  =  PUSHsAF     == ir1 ;                                        
968
 
969
 
970
//---------------- inst hazard ----------------------------------------------------------
971
//
972
// On some reflection, I don't think I'm going to worry about this immediately - it 
973
// should be easy to kludge in a fix if necessary  -- and there are more important things
974
// todo.  It is a very bad programming practice to muck with the instruction stream in any
975
// case --  I have to believe most target applications do not do this -- although I'll probably
976
// get hit pretty early with a instruction test that does.   Oh well  -- if that happens we fix
977
// it.   
978
// Well --  think some here --  the hazard is because of a change in design. 
979
//  If used to any extent..  Somebody WILL
980
//  want this to act the same way as the origional - even if the programming is "poor".
981
//  >>>>>>>> bite the bullet and do it.
982
//
983
// if we do an operand store and the address == pc-1 its an inst hazard, We need to execute the 
984
// store decrement pc and re-fetch.  This is a high priority interrupt. 
985
// what about multi-byte stores  - like LDs6NN7_A  or LDs6NN7_HL - i guess we  do an IF - to start
986
// the pipe before the os -- same logic.   
987
// 
988
 
989
 
990
//-----------------data hazard ----------------------------------------------------------
991
//
992
// Issues here have evolved to a degree as the design progressed.  However the 
993
// Key has always been that for each instruction (no matter how complex) there 
994
// is only a single state in which the previous instruction can also be active
995
// and that is the DEC_EXEC state.  If there is a data hazard, we need to delay
996
// execution of that state until the ir2 execution completes (which it always does
997
// in a single tick).  Note that only the RET instructions test the flag register
998
// on DEC_EXEC.
999
//
1000
// WARNING:  be very careful about this.  Data hazard logic is very difficult to 
1001
// verify as there are so many instruction pairs to test.
1002
//
1003
//  Situations  1) operand stores from ir1 when register is updated in ir2
1004
//              2) flag tests when fr is being updated
1005
//              3) sp issues  see below  LDsSP_HL  DECsSP  INCsSP
1006
//     ANY OTHERS ???
1007
//              4) Indirect addressing -(HL) (BC) (DE) when address registers are updated
1008
// 
1009
// upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
1010
wire  use_hl_exec =  LDsSP_HL == ir1      |  INCs6HL7     == ir1  |
1011
                     ADCsA_6HL7   == ir1  |  SBCs6HL7     == ir1  |
1012
                     ADDsA_6HL7   == ir1  |  SUBs6HL7     == ir1  |
1013
                     ANDs6HL7     == ir1  |  XORs6HL7     == ir1  |
1014
                     CPs6HL7      == ir1  |  LDs6HL7_A    == ir1  |
1015
                     LDsA_6HL7    == ir1  |  LDs6HL7_B    == ir1  |
1016
                     LDsB_6HL7    == ir1  |  LDs6HL7_C    == ir1  |
1017
                     LDsC_6HL7    == ir1  |  LDs6HL7_D    == ir1  |
1018
                     LDsD_6HL7    == ir1  |  LDs6HL7_E    == ir1  |
1019
                     LDsE_6HL7    == ir1  |  LDs6HL7_H    == ir1  |
1020
                     LDsH_6HL7    == ir1  |  LDs6HL7_L    == ir1  |
1021
                     LDsL_6HL7    == ir1  |  JPsHL        == ir1  |
1022
                     ORs6HL7      == ir1  |  DECs6HL7     == ir1  |
1023
                     PUSHsHL      == ir1;
1024
wire  use_bc_exec =  LDsA_6BC7    == ir1 |
1025
                     LDs6BC7_A    == ir1 |
1026
                     PUSHsBC      == ir1  ;
1027
wire  use_de_exec =  LDs6DE7_A    == ir1 |
1028
                     LDsA_6DE7    == ir1 |
1029
                     PUSHsDE      == ir1  ;
1030
 
1031
wire  use_sp_exec =  MEM_OFSP == next_mem_state |
1032
                     MEM_OSSP == next_mem_state  ;
1033
wire  upd_sp_exec  = DECsSP == ir2 |
1034
                     INCsSP == ir2   ;
1035
 
1036
wire use_fr_exec = ( RETsC        == ir1  |
1037
                     RETsM        == ir1  |
1038
                     RETsNC       == ir1  |
1039
                     RETsP        == ir1  |
1040
                     RETsPE       == ir1  |
1041
                     RETsPO       == ir1  |
1042
                     RETsNZ       == ir1  |
1043
                     RETsZ        == ir1  |
1044
                     PUSHsAF      == ir1   ) ;
1045
 
1046
assign hazard =  (dec_state == DEC_EXEC  & exec_ir2 ) & ( upd_fr & use_fr_exec      |
1047
                                                          upd_ar & os_a             |
1048
                                                          upd_br & os_b             |
1049
                                                          upd_br & use_bc_exec      |
1050
                                                          upd_cr & os_c             |
1051
                                                          upd_cr & use_bc_exec      |
1052
                                                          upd_dr & os_d             |
1053
                                                          upd_dr & use_de_exec      |
1054
                                                          upd_er & os_e             |
1055
                                                          upd_er & use_de_exec      |
1056
                                                          upd_hr & os_h             |
1057
                                                          upd_lr & os_l             |
1058
                                                          upd_hr & use_hl_exec      |
1059
                                                          upd_lr & use_hl_exec      |
1060
                                                          upd_sp_exec & use_sp_exec   );
1061
//----------------- inst hazard logic ------------------------------------------
1062
 
1063
 
1064
 
1065
always @(posedge wb_clk_i or posedge rst_i)
1066
    if (rst_i) inst_haz <= 1'b0;
1067
    else if  (we_next & (pc - 16'h1) == mux21)  inst_haz <= 1'b1;
1068
    else if  (dec_state == DEC_EXEC)  inst_haz <= 1'b0;   // highest priority interrupt
1069
 
1070
 
1071
 
1072
 
1073
 
1074
 
1075
// does not include extension stuff as we are mostly looking for hazards here
1076
// course we do use these terms to build more decodes
1077
//
1078
wire  opadr_bc  =  LDsA_6BC7  == ir1 | LDs6BC7_A == ir1;
1079
wire  opadr_de  =  LDsA_6DE7  == ir1 | LDs6DE7_A == ir1;
1080
wire  opadr_hl  =  LDsB_6HL7  == ir1 | ORs6HL7    == ir1 | LDs6HL7_B == ir1 |
1081
                   LDsD_6HL7  == ir1 | LDsC_6HL7  == ir1 | LDs6HL7_C == ir1 |
1082
                   LDsH_6HL7  == ir1 | LDsE_6HL7  == ir1 | LDs6HL7_D == ir1 |
1083
                   ADDsA_6HL7 == ir1 | LDsL_6HL7  == ir1 | LDs6HL7_E == ir1 |
1084
                   SUBs6HL7   == ir1 | LDsA_6HL7  == ir1 | LDs6HL7_H == ir1 |
1085
                   ANDs6HL7   == ir1 | ADCsA_6HL7 == ir1 | LDs6HL7_L == ir1 |
1086
                   XORs6HL7   == ir1 | SBCs6HL7   == ir1 | CPs6HL7   == ir1 ;
1087
 
1088
//assign  use_a = os_a;
1089
//assign  use_b = os_b  | opadr_bc;
1090
//assign  use_c = os_c  | opadr_bc;
1091
//assign  use_d = os_d  | opadr_de;
1092
//assign  use_e = os_e  | opadr_de;
1093
//assign  use_h = os_h  | opadr_hl;
1094
//assign  use_l = os_l  | opadr_hl;
1095
 
1096
 
1097
// old logic not used
1098
//assign   use_flags = c_jmp8 | c_jmp4 | c_call | c_ret;
1099
 
1100
 
1101
 
1102
//wire bc_eq0 = beq0 & ceq0;
1103
//  ???  not used ?  why defined ?  I simply re-wrote the test   re-name 
1104
//assign rpt_blk_mv = (blk_mv_reg )  & !bc_eq0     |
1105
//                    (blk_cmp_reg) & !bc_eq0 & (nn[7:0] != 8'h0)  |
1106
//                    (blk_in_reg | blk_out_reg) & !b_eq0 ;
1107
 
1108
 
1109
 
1110
 
1111
 
1112
 
1113
 
1114
//  BASIC ARCHITECTURE OF THIS FILE   pc  and sp not shown, but are inputs to src mux.
1115
//                    _____           and may be updated from adder output.
1116
//                   |     |
1117
//                   |     |          pc-1 register is required to implement relative jumps.
1118
//                   |     |                     
1119
//      _____        |lit  |      |\             
1120
//     |     |       |     |      |  \           
1121
//     |     |       |src2 |      |    \          _____          _____ 
1122
//     |     |       |     |----->|     |        |     |        |     |
1123
//     |src  |       |_____|      |adder|------->|     |        |     |
1124
//     |mux  |                    |     |        |     |        |     |
1125
//     |     |------------------->|    /         |2/1  |------->|wb   |
1126
//     |     |              |     |  /           |mux  |        |adr  |
1127
//     |_____|              |     |/             |     |        |     |
1128
//                           ------------------->|     |        |     |
1129
//                                               |_____|        |_____|
1130
//  MEM_NOP  
1131
//  MEM_IFPP1   MEM_OFIXpD     MEM_CALL    MEM_RST     MEM_OFHL_PM    MEM_IOF_C  
1132
//  MEM_OS1,    MEM_OSIXpD     MEM_OSNN,   MEM_REL2PC   MEM_OSHL_PM    MEM_IOS_C  
1133
//  MEM_OF1,    MEM_OSADR      MEM_OFNN    MEM_JMPHL     MEM_OSDE_PM    MEM_IOF_N  
1134
//  MEM_OFSP    MEM_OSSP_PCM2  MEM_OFADRP1 MEM_IFNN      MEM_INTA       MEM_IOS_N  
1135
//  MEM_OSSP    MEM_OSSP_P     MEM_OSADRP1 MEM_IFINT     MEM_OS_HL_N
1136
//                                                       
1137
 
1138
wire src_sp = next_mem_state == MEM_OFSP                     |
1139
              next_mem_state == MEM_OSSP                     |
1140
              next_mem_state == MEM_OSSP_PCM2                |
1141
              next_mem_state == MEM_CALL                       ;
1142
wire src_pc =  next_mem_state ==   MEM_IFPP1   |
1143
               next_mem_state ==  MEM_REL2PC  ;
1144
 
1145
wire src_nn =  next_mem_state ==   MEM_IFNN |
1146
               next_mem_state ==   MEM_OSNN |
1147
               next_mem_state ==   MEM_OFNN  ;
1148
 
1149
 
1150
wire src_de  = dec_state == DEC_EXEC & LDsA_6DE7 == ir1  |      // MEM_OS1  MEM_OF1
1151
               dec_state == DEC_EXEC & LDs6DE7_A == ir1  |     // are both true at this time
1152
               next_mem_state == MEM_OSDE_PM               ;
1153
wire src_bc =  dec_state == DEC_EXEC & LDsA_6BC7 == ir1  |
1154
               dec_state == DEC_EXEC & LDs6BC7_A == ir1  |
1155
               next_mem_state ==MEM_IOF_C                |
1156
               next_mem_state ==MEM_IOS_C                 ;
1157
 
1158
 
1159
//  don't forget that hl source can be modified by prefix
1160
//  this gets messy as we use wb_adr_o for some of these.
1161
//
1162
wire src_hl =   next_mem_state == MEM_OF1  &
1163
                                   !src_de & !src_bc & !src_sp  |
1164
                next_mem_state == MEM_OS1  &
1165
                                   !src_de & !src_bc         |
1166
                next_mem_state == MEM_OFHL_PM                |
1167
                next_mem_state == MEM_OSHL_PM                |
1168
                next_mem_state == MEM_OS_HL_N                |
1169
                next_mem_state == MEM_JMPHL  & !( ir1dd | ir1fd);
1170
 
1171
wire src_ix =  next_mem_state == MEM_OFIXpD  &  ir1dd |
1172
               next_mem_state == MEM_JMPHL   &  ir1dd |
1173
               next_mem_state == MEM_OSIXpD  &  ir1dd  ;
1174
 
1175
wire src_iy =  next_mem_state == MEM_OFIXpD  &  ir1fd |
1176
               next_mem_state == MEM_JMPHL   &  ir1fd |
1177
               next_mem_state == MEM_OSIXpD  &  ir1fd  ;
1178
 
1179
wire src_adr = next_mem_state == MEM_OFADRP1  |
1180
               next_mem_state == MEM_OSADRP1  |
1181
               next_mem_state == MEM_NOP      |
1182
               next_mem_state == MEM_OSADR     ;
1183
 
1184
wire src_io = next_mem_state == MEM_IOF_N  |
1185
               next_mem_state == MEM_IOS_N   ;
1186
 
1187
wire src_int = next_mem_state == MEM_IFINT ;
1188
 
1189
wire [15:0]  src_mux =   {16{ src_sp  }} & sp                 |
1190
                         {16{ src_pc  }} & pc                 |
1191
                         {16{ src_nn  }} & nn                 |
1192
                         {16{ src_hl  }} & hl                 |
1193
                         {16{ src_de  }} & de                 |
1194
                         {16{ src_bc  }} & bc                 |
1195
                         {16{ src_ix  }} & ixr                |
1196
                         {16{ src_iy  }} & iyr                |
1197
                         {16{ src_adr }} & wb_adr_o           |
1198
                         {16{ src_int }} & {intr, nn[15:8] }  |
1199
                         {16{ src_io }} & { br, nn[15:8] }  ;
1200
 
1201
wire block_mv_inc = (dec_state == DEC_ED) ? dec_blk_inc : blk_inc_flg; // flag set at DEC_ED
1202
 
1203
 
1204
 
1205
wire inc    =     next_mem_state ==MEM_OFADRP1                |
1206
                  next_mem_state ==MEM_OSADRP1                |
1207
                  next_mem_state ==MEM_OFHL_PM & block_mv_inc |
1208
                  next_mem_state ==MEM_OSHL_PM & block_mv_inc |
1209
                  next_mem_state ==MEM_OSDE_PM & block_mv_inc |
1210
                  next_mem_state ==MEM_OFSP                   |
1211
                  next_mem_state ==MEM_IFPP1                  |
1212
                  next_mem_state ==MEM_JMPHL                  |
1213
                  next_mem_state ==MEM_IFINT                  |
1214
                  next_mem_state ==MEM_IFNN                   |
1215
                  next_mem_state ==MEM_OFNN                   |
1216
                  next_mem_state ==MEM_OSNN                   |
1217
                  next_mem_state ==MEM_RST                     ;
1218
                  //next_mem_state ==MEM_OSSP_P                  ;
1219
 
1220
wire dec    =     next_mem_state ==MEM_OFHL_PM & ~block_mv_inc |
1221
                  next_mem_state ==MEM_OSHL_PM & ~block_mv_inc |
1222
                  next_mem_state ==MEM_OSDE_PM & ~block_mv_inc |
1223
                  next_mem_state ==MEM_OSSP_PCM2               |
1224
                  next_mem_state ==MEM_CALL                    |
1225
                  next_mem_state == MEM_OSSP                    ;
1226
 
1227
 
1228
wire reln    =    next_mem_state ==  MEM_REL2PC   |
1229
                  next_mem_state ==  MEM_OFIXpD    |
1230
                   next_mem_state ==  MEM_OSIXpD    ;
1231
 
1232
wire  [15:0] src2    = {16{ inc    }}  & 16'h0001               |
1233
                       {16{ dec    }}  & 16'hffff               |
1234
                       {16{ reln    }}  & {{8{nn[15]}},nn[15:8]}|
1235
                       {16{~(reln | inc | dec)}} & 16'h0    ;// lint complains that this signal
1236
                                                             // has no load  -YES it is not needed -
1237
                                                             // more for information --  amazing complaint though
1238
 
1239
wire [15:0]  adr_alu     = src2 + src_mux;
1240
 
1241
 
1242
wire  pre_inc_dec =    next_mem_state ==  MEM_CALL      |
1243
                       //next_mem_state ==  MEM_OSSP_P  |
1244
                       next_mem_state ==  MEM_REL2PC    |
1245
                       next_mem_state ==  MEM_OFIXpD    |
1246
                       next_mem_state ==  MEM_OSIXpD    |
1247
                       next_mem_state ==  MEM_OFADRP1   |
1248
                       next_mem_state ==  MEM_OSADRP1   |
1249
                       next_mem_state ==  MEM_OSSP_PCM2 |
1250
                       next_mem_state ==  MEM_OSSP     ;
1251
 
1252
 
1253
assign  mux21 =  pre_inc_dec ? adr_alu : src_mux;
1254
 
1255
assign wb_rdy_nhz = (!wb_cyc_o | wb_ack_i ) & ~hazard;   //  wishbone ready with no hazard
1256
wire   wb_rdy     = !wb_cyc_o | wb_ack_i;
1257
 
1258
assign we_next = next_mem_state == MEM_OS1        |
1259
                 next_mem_state == MEM_OSSP       |
1260
                 next_mem_state == MEM_OSIXpD     |
1261
                 next_mem_state == MEM_OSADR      |
1262
                 next_mem_state == MEM_OSSP_PCM2  |
1263
                 //next_mem_state == MEM_OSSP_P     |
1264
                 next_mem_state == MEM_CALL       |
1265
                 next_mem_state == MEM_OSNN       |
1266
                 next_mem_state == MEM_OSADRP1    |
1267
                 next_mem_state == MEM_OSHL_PM    |
1268
                 next_mem_state == MEM_OSDE_PM    |
1269
                 next_mem_state == MEM_OS_HL_N    |
1270
                 next_mem_state == MEM_IOS_C      |
1271
                 next_mem_state == MEM_IOS_N       ;
1272
 
1273
 
1274
//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
1275
// we do this just to save virtual paper below.
1276
//  IMPORTANT  next_dec_state  -- gets registered - mostly used in next tick.
1277
//             next_mem_state --- gets further decoded -- lots of terms - most related to next tick 
1278
//             next_pipe_state - generall represents enables for regs on trailing edge of this tick
1279
// 
1280
//              6              5              4                15
1281
assign {next_dec_state, next_mem_state, next_pipe_state} = next_state;
1282
 
1283
always @(ir1 or wb_int or inst_haz  or dec_state or mem_exec_dec or cb_mem or ed_nn or
1284
         ed_blk_cp  or ed_blk_in or ed_blk_out or ed_retn or ed_blk_mv or ed_dbl_rd or blk_done or
1285
         fr or jmpr_true or callnn_true or jmpnn_true or
1286
         ed_rmw or ed_in_reg or blk_cpi_done or jmpr or ex_tos_hl or ed_out_reg)
1287
 
1288
begin
1289
    case (dec_state)
1290
        DEC_IDLE:       next_state = {DEC_IF1, MEM_NOP, IPIPE_NOP};
1291
 
1292
        DEC_HALT:
1293
            if (wb_int)      next_state = {DEC_INT1,MEM_NOP   ,IPIPE_NOP};// stay here until interrupt or reset
1294
            else             next_state = {DEC_HALT,MEM_NOP   ,IPIPE_NOP};
1295
        DEC_IF1 :            next_state = {DEC_IF2 ,MEM_IFPP1 ,IPIPE_NOP};
1296
        DEC_IF2 :            next_state = {DEC_EXEC,MEM_IFPP1 ,IPIPE_EN1};
1297
        DEC_IF2A:            next_state = {DEC_EXEC,MEM_IFPP1 ,IPIPE_NOP};
1298
        DEC_EXEC:
1299
            if      (inst_haz)    next_state = {DEC_IF1, MEM_DECPC , IPIPE_NOP};
1300
            else if (wb_int)      next_state = {DEC_INT1,MEM_NOP   ,IPIPE_NOP};
1301
            else
1302
                case (mem_exec_dec) // full case but can all tools understand ? just make a default
1303
                I1_CB   : next_state = {DEC_CB,   MEM_IFPP1, IPIPE_EN1};// IF2_NOP -> nn <= (MEM)
1304
                I1_DDFD : next_state = {DEC_DDFD, MEM_IFPP1, IPIPE_EN1};// gets real inst     
1305
                I1_ED   : next_state = {DEC_ED,   MEM_IFPP1, IPIPE_EN1};
1306
                I1_JMP  : next_state = {DEC_IF2,  MEM_JMPHL, IPIPE_NOP};
1307
                I1_N    : next_state = {DEC_N,    MEM_IFPP1, IPIPE_ENNEN2};
1308
                I1_NN   : next_state = {DEC_NN,   MEM_IFPP1, IPIPE_ENN};
1309
                I1_OF   : next_state = {DEC_OF,   MEM_OF1,   IPIPE_EN12};//transfer, don't activate
1310
                I1_OS   : next_state = {DEC_IF2A,  MEM_OS1,   IPIPE_EN1}; // -> ir2_NOP
1311
                I1_POP  : next_state = {DEC_POP,  MEM_OFSP,  IPIPE_EN12};
1312
                I1_PUSH : next_state = {DEC_PUSH, MEM_OSSP,  IPIPE_EN12};
1313
                I1_RET  : next_state = {DEC_RET,  MEM_OFSP,  IPIPE_EN12};
1314
                I1_RMW  : next_state = {DEC_RMW,  MEM_OF1,   IPIPE_EN12};//can't gronk ir1  - blow off if
1315
                I1_RST  : next_state = {DEC_NNCALL2,  MEM_OSSP_PCM2, IPIPE_NOP};
1316
                I1_R2R  : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2};
1317
                I1_JMPR : next_state = {DEC_N,    MEM_NOP,   IPIPE_ENNEN2A2};
1318
                I1_HALT : next_state = {DEC_HALT, MEM_NOP  , IPIPE_EN2};
1319
                default : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R  
1320
                endcase
1321
        DEC_CB: if (cb_mem) next_state = {DEC_CBM, MEM_OF1, IPIPE_EN12};
1322
                else        next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2};
1323
        DEC_DDFD:   // except for CB and EB these all act the same H and L get modified by prefix
1324
            case (mem_exec_dec)
1325
            I1_CB   : next_state = {DEC_PFxCB,MEM_IFPP1, IPIPE_ENN};// IF2_NOP -> nn <= (MEM)
1326
            I1_DDFD : next_state = {DEC_DDFD, MEM_IFPP1, IPIPE_EN1};
1327
            I1_ED   : next_state = {DEC_ED,   MEM_IFPP1, IPIPE_EN1};//How do we clear the prefix?
1328
            I1_JMP  : next_state = {DEC_IF2,  MEM_JMPHL, IPIPE_NOP};
1329
            I1_N    : next_state = {DEC_DDN,  MEM_IFPP1, IPIPE_ENN};
1330
            I1_NN   : next_state = {DEC_NN,   MEM_IFPP1, IPIPE_ENN};
1331
            I1_OF   : next_state = {DEC_DDOF, MEM_IFPP1, IPIPE_ENN};  // d to nn - need to get d
1332
                                                                      // LD A,(BC) LD A,(DE) will
1333
                                                                      // become ix+d - do we care ?
1334
                                                                      // i hope not
1335
                                                                      // 5/13/04 the dd mods the index op
1336
                                                                      //  but NOT the operand  -- gotta kill
1337
                                                                      //  the prefix on these
1338
            I1_OS   : next_state = {DEC_DDOS, MEM_IFPP1, IPIPE_ENN};  // d to nn
1339
            I1_POP  : next_state = {DEC_POP,  MEM_OFSP,  IPIPE_EN12};
1340
            I1_PUSH : next_state = {DEC_PUSH, MEM_OSSP,  IPIPE_EN12};
1341
            I1_RET  : next_state = {DEC_RET,  MEM_OFSP,  IPIPE_EN12};
1342
            I1_RMW  : next_state = {DEC_RMWDD1,  MEM_IFPP1,  IPIPE_ENNEN2};
1343
            I1_RST  : next_state = {DEC_NNCALL2,  MEM_OSSP_PCM2, IPIPE_NOP};  // just dump next inst
1344
            I1_R2R  : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R
1345
            I1_JMPR : next_state = {DEC_N,    MEM_NOP,   IPIPE_ENNEN2A2};
1346
            I1_HALT : next_state = {DEC_HALT, MEM_NOP  , IPIPE_EN2};
1347
            default : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R  
1348
            endcase
1349
        DEC_ED:
1350
            if (ed_nn)            next_state = {DEC_EDNN1,  MEM_IFPP1,   IPIPE_ENNEN2};
1351
            // we need to set inc and io and repeat flags on this state for continued block
1352
            // processing  --   keep the states of this machine somewhat manageable.
1353
            else if (ed_rmw )     next_state = {DEC_RMW,    MEM_OF1,     IPIPE_EN12}; // RLD RRD
1354
            else if (ed_blk_cp )  next_state = {DEC_EDBCP1, MEM_OFHL_PM, IPIPE_EN12};// MEM_OFHL_PM triggers --BC
1355
            else if (ed_blk_in )  next_state = {DEC_EDBIN1, MEM_IOF_C,   IPIPE_EN12};// MEM_IOF_C triggers --B
1356
            else if (ed_blk_out)  next_state = {DEC_EDBOUT1,MEM_OFHL_PM, IPIPE_EN12};
1357
            else if (ed_blk_mv )  next_state = {DEC_EDBMV1, MEM_OFHL_PM, IPIPE_EN12};
1358
            else if (ed_retn   )  next_state = {DEC_RET,    MEM_OFSP,    IPIPE_EN12};// see int logic below
1359
            else if (ed_in_reg )  next_state = {DEC_EDRD2,  MEM_IOF_C,   IPIPE_EN12};
1360
            else if (ed_out_reg ) next_state = {DEC_IF2A,   MEM_IOS_C,   IPIPE_EN12};
1361
            else                  next_state = {DEC_EXEC, MEM_IFPP1,    IPIPE_EN12A2};
1362
                   // double register reads and writes here    
1363
        DEC_EDNN1:                next_state = {DEC_EDNN2, MEM_IFPP1,     IPIPE_ENN}; // address to nn
1364
        DEC_EDNN2:
1365
            if (ed_dbl_rd)      next_state = {DEC_EDRD1, MEM_OFNN,    IPIPE_EN12};
1366
            else                next_state = {DEC_EDWR,  MEM_OSNN,    IPIPE_EN12};// OSNN selects data ok?
1367
        DEC_EDRD1:              next_state = {DEC_EDRD2, MEM_OFADRP1,  IPIPE_ENN};  // 1st byte 2n         
1368
        DEC_EDRD2:              next_state = {DEC_EXEC,   MEM_IFPP1,   IPIPE_ENNA2}; // 2nd byte 2nn
1369
        DEC_EDWR:               next_state = {DEC_IF2A,   MEM_OSADRP1,  IPIPE_NOP};
1370
 
1371
        //  ED  block compair
1372
        //  Got a tricky problem here.....   fr is updated in a different manner for cpi and 
1373
        //  we really can't test blk_done here (bc is updated on this tick).  So make the test 
1374
        //  for done be bc==1 and use enna2 for everything.   Course this begs the question if 
1375
        //  this approach is not best for all block moves ?????  
1376
        DEC_EDBCP1:
1377
            if (blk_cpi_done) next_state = {DEC_EXEC, MEM_IFPP1,IPIPE_ENNA2};
1378
            else if(wb_int)   next_state = {DEC_INT1, MEM_NOP, IPIPE_ENNA2};
1379
            else              next_state = {DEC_EDBCP2, MEM_NOP,  IPIPE_ENNA2};//set flags 
1380
        DEC_EDBCP2:                 next_state = {DEC_EDBCP3, MEM_NOP,     IPIPE_NOP};//wait for fr. alu_out is slow 
1381
        DEC_EDBCP3: if (fr[6])      next_state = {DEC_EXEC  , MEM_IFPP1,   IPIPE_NOP};
1382
                    else            next_state = {DEC_EDBCP1, MEM_OFHL_PM, IPIPE_NOP};
1383
 
1384
        DEC_EDBIN1:                  next_state = {DEC_EDBIN2, MEM_NOP,   IPIPE_ENN};
1385
        DEC_EDBIN2: if (blk_done)    next_state = {DEC_IF2A,  MEM_OSHL_PM,IPIPE_NOP}; // implies nn
1386
                    else if (wb_int) next_state = {DEC_INT1,  MEM_OSHL_PM,IPIPE_NOP};
1387
                    else             next_state = {DEC_EDBIN3,MEM_OSHL_PM,IPIPE_NOP};//set flags 
1388
        DEC_EDBIN3:                  next_state = {DEC_EDBIN1, MEM_IOF_C,   IPIPE_NOP};
1389
 
1390
        DEC_EDBOUT1:                 next_state = {DEC_EDBOUT2, MEM_NOP,   IPIPE_ENN};
1391
        DEC_EDBOUT2:if (blk_done)    next_state = {DEC_IF2A,  MEM_IOS_C,IPIPE_NOP};
1392
                    else if (wb_int) next_state = {DEC_INT1,  MEM_IOS_C,IPIPE_NOP}; // DEC_EDBOUT: if (blk_rpt)
1393
                    else             next_state = {DEC_EDBOUT3,MEM_IOS_C,IPIPE_NOP};
1394
 
1395
        DEC_EDBOUT3:                 next_state = {DEC_EDBOUT1,MEM_OFHL_PM, IPIPE_NOP};
1396
 
1397
        DEC_EDBMV1:                  next_state = {DEC_EDBMV2, MEM_NOP,   IPIPE_ENN};
1398
        DEC_EDBMV2: if (blk_done)    next_state = {DEC_IF2A,  MEM_OSDE_PM,IPIPE_NOP};
1399
                    else if (wb_int) next_state = {DEC_INT1,  MEM_OSDE_PM,IPIPE_NOP}; //DEC_EDBOUT: if (blk_rpt)
1400
                    else             next_state = {DEC_EDBMV3,MEM_OSDE_PM,IPIPE_NOP};
1401
 
1402
        DEC_EDBMV3:                  next_state = {DEC_EDBMV1,MEM_OFHL_PM, IPIPE_NOP};
1403
 
1404
        DEC_N:
1405
            if (INsA_6N7== ir1)      next_state = {DEC_NIN,  MEM_IOF_N, IPIPE_EN12};
1406
            else if (OUTs6N7_A==ir1) next_state = {DEC_IF2A,  MEM_IOS_N, IPIPE_EN1};
1407
            else if (LDs6HL7_N==ir1) next_state = {DEC_IF2A,  MEM_OS_HL_N, IPIPE_EN12};
1408
            else if (jmpr_true)      next_state = {DEC_IF1,  MEM_REL2PC, IPIPE_NOP};
1409
            else if (jmpr)           next_state = {DEC_IF2,  MEM_IFPP1,  IPIPE_NOP};
1410
            else                     next_state = {DEC_EXEC, MEM_IFPP1,  IPIPE_EN12A2};//r2r 
1411
        DEC_DDN:
1412
            if (INsA_6N7== ir1)      next_state = {DEC_NIN,  MEM_IOF_N, IPIPE_EN12};
1413
            else if (OUTs6N7_A==ir1) next_state = {DEC_IF2A,  MEM_IOS_N, IPIPE_EN1};
1414
            else if (LDs6HL7_N==ir1) next_state = {DEC_IF1,  MEM_OSIXpD, IPIPE_ENN};
1415
            else                     next_state = {DEC_EXEC, MEM_IFPP1,  IPIPE_EN12A2};//r2r 
1416
 
1417
        //DEC_NIN:                     next_state = {DEC_IF2,  MEM_IFPP1,    IPIPE_ENNA2};
1418
        //  bjp 10/11/2007  have ir1 set - next inst gets started  should goto DEC_EXEC
1419
        DEC_NIN:                     next_state = {DEC_EXEC,  MEM_IFPP1,    IPIPE_ENNA2};
1420
        //ISSUES: LDsSP_NN - load commanded from ir2 decode?  and mechaninsm for updating PC on
1421
        //        JMP and CALL
1422
        //  on CALL   We have IFNN for JMP  
1423
        //   For CALL  Use MEM_CALL to transfer pc<=nn, nn<=pc, adr<=sp then MEM_OSSP then IFPP1
1424
        //   For  LDsSP_NN  yes  update from ir2 decode.                    
1425
        DEC_NN:
1426
            if      (callnn_true)     next_state = {DEC_NNCALL1, MEM_NOP, IPIPE_ENN};// this gets new adr in nn
1427
                                                                                     //if we store from nn we can't do
1428
                                                                                     // a mem op now
1429
 
1430
            else if (jmpnn_true)      next_state = {DEC_NNJMP,  MEM_NOP,  IPIPE_ENN};    // gotta get nn before we can 
1431
                                                                                         // transfer to adr.
1432
            else if (LDs6NN7_A==ir1)  next_state = {DEC_NNOS3,   MEM_IFPP1,  IPIPE_ENN};
1433
            else if (LDs6NN7_HL==ir1) next_state = {DEC_NNOS1,   MEM_IFPP1,  IPIPE_ENN};
1434
            else if (LDsA_6NN7==ir1)  next_state = {DEC_NNOF3,    MEM_IFPP1,  IPIPE_ENN};
1435
            else if (LDsHL_6NN7==ir1) next_state = {DEC_NNOF1,    MEM_IFPP1,  IPIPE_ENN};
1436
            else                      next_state = { DEC_IF2, MEM_IFPP1, IPIPE_ENNEN2A2};
1437
 
1438
        DEC_NNCALL1:        next_state = {DEC_NNCALL2, MEM_CALL ,  IPIPE_NOP};
1439
        DEC_NNCALL2:        next_state = {DEC_IF1,    MEM_OSSP,   IPIPE_NOP};//A1 activates r2r xfers from ir1
1440
        DEC_NNJMP:        next_state = {DEC_IF2,     MEM_IFNN  , IPIPE_NOP};
1441
 
1442
        // ISSUE:  we blow out ir1 here - so need to keep some status to execute OSNN2.
1443
        //  general solution  if not DEC_EXEC we get op frmo nn high byte. 
1444
        //  note that first MEM_OSNN trabsferrs nn to wb_adr_o.
1445
        DEC_NNOS1:           next_state = {DEC_NNOS2,   MEM_OSNN,   IPIPE_EN1};
1446
        DEC_NNOS2:           next_state = {DEC_IF2A,    MEM_OSADRP1,   IPIPE_NOP};
1447
        DEC_NNOS3:           next_state = {DEC_IF2A,    MEM_OSNN,   IPIPE_EN1};
1448
 
1449
        DEC_NNOF1:           next_state = {DEC_NNOF2,  MEM_OFNN, IPIPE_EN12};
1450
        DEC_NNOF2:           next_state = {DEC_NNOF4,  MEM_OFADRP1, IPIPE_ENN};
1451
        DEC_NNOF3:           next_state = {DEC_NNOF4,  MEM_OFNN, IPIPE_EN12};
1452
        DEC_NNOF4: if (ex_tos_hl) next_state = {DEC_EXSPHL,   MEM_NOP, IPIPE_ENNA2};
1453
                   else           next_state = {DEC_EXEC,   MEM_IFPP1, IPIPE_ENNA2};
1454
 
1455
        DEC_DDOS:            next_state = {DEC_IF2A, MEM_OSIXpD, IPIPE_EN12};
1456
        DEC_DDOF:            next_state = {DEC_OF  , MEM_OFIXpD,  IPIPE_EN12};
1457
 
1458
 
1459
        DEC_OF:              next_state = {DEC_EXEC,  MEM_IFPP1 , IPIPE_ENNA2};
1460
        DEC_POP:             next_state = {DEC_NNOF4,  MEM_OFSP, IPIPE_ENN };
1461
        DEC_PUSH:            next_state = {DEC_IF2A ,  MEM_OSSP, IPIPE_NOP };
1462
 
1463
 
1464
        DEC_RET:             next_state = { DEC_RET2, MEM_OFSP, IPIPE_ENN };
1465
        DEC_RET2:            next_state = { DEC_NNJMP, MEM_NOP, IPIPE_ENN };
1466
                                                                 //  blow off a tick so we don't gronk adr
1467
        DEC_RMW:             next_state = {DEC_RMW2,  MEM_NOP,   IPIPE_ENNA2}; //activate
1468
        DEC_RMW2:            next_state = {DEC_IF2A ,  MEM_OSADR, IPIPE_NOP }; // from nn
1469
 
1470
 
1471
        //  IF memory -- rmw  else these are all reg 2 reg
1472
        DEC_CBM: if (CB_BIT==ir1[9:6]) next_state = {DEC_IF2, MEM_IFPP1,   IPIPE_ENNA2};
1473
                 else                 next_state = {DEC_RMW2 ,  MEM_NOP,  IPIPE_ENNA2};
1474
 
1475
        // The DDCB anf FDCB all assume memory operands 
1476
        // These beauties always rmw memory.  If a register op is default, they also 
1477
        // update the register.  Programmers think of this as 2 ops for the price of 1.
1478
        // unfortunately it is 2 ops for the price of 4.-- its not the number of lines 
1479
        // of assembler code that count but the number of bytes assembled. Oh well I signed
1480
        // up for this......  and had a notion of what I was getting into.
1481
        //
1482
        DEC_PFxCB:     next_state = { DEC_PFxCB2, MEM_IFPP1,  IPIPE_EN1}; // this gets inst
1483
        DEC_PFxCB2:    next_state = { DEC_PFxCB3, MEM_OFIXpD, IPIPE_EN12}; //next inst - get op 
1484
        DEC_PFxCB3:    next_state = { DEC_PFxCB4, MEM_NOP,    IPIPE_ENNA2};
1485
        DEC_PFxCB4:    next_state = { DEC_IF2A,   MEM_OSADR,  IPIPE_NOP};  //execute ir2
1486
 
1487
        //  crap   gotta subtract 2  (we always increment pc 2 times relative to the inst
1488
        //  that got interrupted. also can't push and dec pc without 2 adders.
1489
        //  choices:  1) fix up pc in 2 ticks 2) fix in 1 tick 3) add adder and do it fast
1490
        //   if there's anyone who knows is there anyone who cares.   
1491
        //   guess I'll do it fast  --   just a 16 bit subtractor.  heck silicon is 
1492
        //   cheap.  
1493
        DEC_INT1:       next_state = {DEC_INT2, MEM_OSSP_PCM2, IPIPE_NOP};   //must derement PC
1494
        DEC_INT2:       next_state = {DEC_INT3, MEM_OSSP,   IPIPE_NOP};      //was MEM_OSSP_P   why? comment out
1495
        DEC_INT3:       next_state = {DEC_INT4, MEM_INTA,     IPIPE_NOP};
1496
        DEC_INT4:       next_state = {DEC_INT5, MEM_NOP,      IPIPE_ENN};
1497
        DEC_INT5:       next_state = {DEC_INT6,  MEM_IFINT,  IPIPE_NOP}; // really a pointer fetch -  but treat a a jmpnn
1498
        DEC_INT6:       next_state = {DEC_RET2, MEM_IFPP1,   IPIPE_ENN};
1499
        DEC_EXSPHL:     next_state = {DEC_PUSH, MEM_OSSP,     IPIPE_NOP};
1500
        DEC_RMWDD1:     next_state = {DEC_RMW,  MEM_OFIXpD,   IPIPE_EN1};
1501
        default:        next_state = {DEC_IDLE, MEM_NOP,      IPIPE_NOP};
1502
    endcase
1503
end
1504
 
1505
 
1506
always @(posedge wb_clk_i or posedge rst_i)
1507
    if (rst_i) dec_state <= DEC_IDLE;
1508
    else   if (wb_rdy_nhz )   dec_state <= next_dec_state;
1509
 
1510
 
1511
//-----------------------instruction register #1 ----------------------------------
1512
//  //         next_pipe_state         {ir1,ir2,nn,act_ir2}
1513
 
1514
wire update_prefix = dec_state == DEC_EXEC  | dec_state == DEC_DDFD | dec_state == DEC_PFxCB;
1515
wire iext_ed =  update_prefix & (ir1[7:0]==8'hed);
1516
wire iext_cb =  update_prefix & (ir1[7:0]==8'hcb);
1517
always @(posedge wb_clk_i or posedge rst_i)
1518
    if (rst_i) ir1 <=   NOP;
1519
    else if (wb_rdy_nhz & next_pipe_state[3]) ir1 <=  {iext_ed, iext_cb, wb_dat_i} ;
1520
 
1521
//----------- prefix states -----------------------------------------
1522
//  strings of prefix insts are ignored up to last one.  Also dded and fded are ignored 
1523
//  but ddcd and fdcd are defined prefix sets.
1524
//
1525
always @(posedge wb_clk_i)
1526
    if  (wb_rdy_nhz & next_dec_state == DEC_EXEC) {ir1dd, ir1fd } <= 2'b0;
1527
    else if ( wb_rdy_nhz & update_prefix )
1528
        {ir1dd, ir1fd } <= {  (ir1[7:0]==8'hdd ) | ir1dd & (ir1[7:0]!=8'hed) & (ir1[7:0]!=8'hfd),
1529
                              (ir1[7:0]==8'hfd ) | ir1fd & (ir1[7:0]!=8'hed) & (ir1[7:0]!=8'hdd) };
1530
 
1531
//------------------- inst reg #2 -----------------------------------
1532
//  This stuff is key to the data hazard logic.  Hazards arise only AFTER activation of 
1533
//  a previous instruction.  Fundamentally all state changes related to ir1 may be 
1534
//  delayed eithor by a delay in wb response, or by a hazard.  Ir2 state changes
1535
//  are keyed off exec_ir2 - and always happen immediately.  ( exec_ir2 always is 
1536
//  immediately reset - unless of course a new instruction is transferred and executed.
1537
//
1538
//
1539
//
1540
always @(posedge wb_clk_i or posedge rst_i)
1541
    if (rst_i) ir2 <= 10'h0;
1542
    else if (wb_rdy_nhz & next_pipe_state[2]) ir2 <= ir1;
1543
 
1544
wire kill_prefix = next_mem_state == MEM_OFIXpD;
1545
always @(posedge wb_clk_i or posedge rst_i)
1546
    if (rst_i)
1547
    begin
1548
        ir2dd <= 1'b0;
1549
        ir2fd <= 1'b0;
1550
    end
1551
    else if (wb_rdy_nhz & next_pipe_state[2])
1552
    begin
1553
        ir2dd <= ir1dd & ~kill_prefix;
1554
        ir2fd <= ir1fd & ~kill_prefix;
1555
    end
1556
 
1557
always @(posedge wb_clk_i )
1558
    if (wb_rdy_nhz & next_pipe_state[0]) exec_ir2 <= 1'b1;
1559
    else                                 exec_ir2 <= 1'b0;
1560
//-------------- special instruction flag ---------------------------
1561
// need this because the POP flow we use gronks ir1 early.  I guess we could use
1562
// ir2, but keeping the dec_state sequencer independent from ir2 seems like a good idea.
1563
//
1564
 
1565
always @(posedge wb_clk_i)
1566
    if ((dec_state == DEC_EXEC) | (dec_state == DEC_DDFD))
1567
                            ex_tos_hl <= (ir1 == EXs6SP7_HL);
1568
 
1569
 
1570
 
1571
 
1572
//--------------- block move flags ------------------------
1573
always @(posedge wb_clk_i)
1574
    if (dec_state == DEC_ED)           blk_inc_flg <= dec_blk_inc;
1575
    else if (dec_state == DEC_EXEC)    blk_inc_flg <= 1'b0;
1576
always @(posedge wb_clk_i)
1577
    if (dec_state == DEC_ED)           blk_rpt_flg <= dec_blk_rpt;
1578
    else if (dec_state == DEC_EXEC)    blk_rpt_flg <= 1'b0;
1579
    else if (dec_state == DEC_INT1)    blk_rpt_flg <= 1'b0;
1580
 
1581
always @(posedge wb_clk_i)
1582
    if (dec_state == DEC_ED)           blk_io_flg <= dec_blk_io;
1583
    else if (dec_state == DEC_EXEC)    blk_io_flg <= 1'b0;
1584
 
1585
 
1586
//-------------------------- memory interface stuff ----------------------------
1587
 
1588
 
1589
// --  wb_adr_o  4/30/04  to wb_rdy_nhz   -- hazard gronks this otherwise
1590
always @(posedge wb_clk_i) if (wb_rdy_nhz) wb_adr_o <= mux21;
1591
 
1592
// --  wb_we_o; 
1593
 
1594
always @(posedge wb_clk_i or posedge rst_i)
1595
    if (rst_i)         wb_we_o <= 1'b0;
1596
    else if (wb_rdy_nhz) wb_we_o <= we_next;
1597
 
1598
 
1599
 
1600
// --  wb_cyc_o
1601
// below is old logic  -- appears not needed
1602
//wire no_wb_start = mem_idle | mem_halt | mem_op3 & blk_cmp_reg | mem_op1 & rmw_reg;
1603
wire no_mem_start =  (next_mem_state == MEM_NOP) | (next_mem_state == MEM_REL2PC);
1604
always @(posedge wb_clk_i or posedge rst_i)
1605
    if (rst_i)         wb_cyc_o <= 1'b0;
1606
    else if (wb_rdy_nhz) wb_cyc_o <= ~no_mem_start;
1607
 
1608
// --  wb_stb_o; 
1609
 
1610
always @(posedge wb_clk_i or posedge rst_i)
1611
    if (rst_i)         wb_stb_o <= 1'b0;
1612
    else if (wb_rdy_nhz) wb_stb_o <= ~no_mem_start  ;
1613
 
1614
 
1615
// --  wb_lock  lets not worry about lock unless somebody thinks it matters.
1616
 
1617
// --  wb_tga_o
1618
always @(posedge wb_clk_i or posedge rst_i)
1619
    if (rst_i)         wb_tga_o <= 2'b0;
1620
    else if (wb_rdy_nhz)
1621
    begin
1622
        if (next_mem_state == MEM_IOF_C |
1623
            next_mem_state == MEM_IOS_C |
1624
            next_mem_state == MEM_IOF_N |
1625
            next_mem_state == MEM_IOS_N     ) wb_tga_o <= TAG_IO;
1626
 
1627
        else if (next_mem_state == MEM_INTA ) wb_tga_o <= TAG_INT;
1628
        else                                  wb_tga_o <= 2'b0   ;
1629
    end
1630
 
1631
//------------ the input-output data register  (nn) -----------------------------------------
1632
//  basicaly we store lsb's folowed by msb's 
1633
//  input is always to msb (of input regiser) first (if a 2 byte operand, lsb<=msb before transfer)
1634
//   this gets nn to position { msb, lsb } before we execute 2 byte transfer.
1635
//
1636
//  if we don't update - we byte swap as well as
1637
//  when we read
1638
//  IMPORTANT  We store from MSB's so that on block moves read and write from same place.
1639
//  this makes the output look somewhat bass-ackwards   but who is looking?
1640
// 
1641
//  There is probably a simpler way to do this.   Unfortunately there are a lot of 
1642
//  dependencies here.   Ill continue as planned till it proves untractable.
1643
//  Issue is that we are using ir1 to provide the op specification  --  but in general
1644
//  ir1 gets gronked before 2nd store (if it happens) -  so we need to capture both
1645
//  data first time  OSIXpD OS1    OSSP, and   MEM_OSNN
1646
//
1647
// on consideration lets make a flag  flag_firstos  that gets set on first store after
1648
// DEC_EXEC
1649
// ISSUE reads both here and in ir1 need to execute on wb_ack_i ? 
1650
// I recall wb_ack_i must stay active until a change in cycle  ?
1651
//  need to review wb spec.
1652
//
1653
//issue:  how is EXs6SP7_HL implemented  --  it is known as a rmw  - and only trick for this file is
1654
// that nn must be properly updates with ir2
1655
// 5/17/04  Sure didn't get EXs6SP7_HL right first time through.   After some serious thought
1656
//  decided to hop onto the POP flow with this  --- POP - exchange - PUSH   biggest trick 
1657
//  is modified SP updating.
1658
 
1659
// 4/30/04 changed else if  (we_next) we had a hazard and this term
1660
//  seemed to be gronking nn.  see if it works now.  Pretty tricky stuff.
1661
always @(posedge wb_clk_i or posedge rst_i)
1662
    if       (rst_i)                                 flag_os1 <= 1'b0;
1663
    else if  ((DEC_EXEC == next_dec_state) & wb_rdy) flag_os1 <= 1'b0;
1664
    else if  ( we_next & wb_rdy_nhz  )               flag_os1 <= 1'b1;
1665
 
1666
wire ir2_cb_shift =  (ir2[9:6] == 4'b01_00) ; // I'll hand or the 8 defined terms here
1667
wire ir2_cb_bit   =  (ir2[9:6] ==  CB_RES ) |
1668
                     (ir2[9:6] ==  CB_SET )  ;
1669
 
1670
wire [15:0] dec_const  = (DEC_INT1 == dec_state) & blk_rpt_flg ? 16'h3 :
1671
                         (DEC_INT1 == dec_state)               ? 16'h2 :
1672
                                                                 16'h1  ;
1673
 
1674
wire [15:0] pc_123 = pc -  dec_const;
1675
 
1676
//  bjp comment   --   logic here is getting pretty slow  --- the else if's are out of 
1677
//  line   need to get this cleaned up for synthesis  --  but first get it logically 
1678
//  correct.
1679
always @(posedge wb_clk_i or posedge rst_i)
1680
    if (rst_i)  nn <= 6'h00;
1681
    else if (wb_rdy_nhz)
1682
    begin
1683
        // This term forces the second store data in any flow to be from nn[7:0]
1684
        // LOL   better not do this for block repeat flows
1685
        if ( we_next & flag_os1 & ~blk_rpt_flg)              nn <= { nn[7:0], nn[15:8] } ;
1686
 
1687
        else if( next_mem_state == MEM_CALL)                 nn <= {pc};
1688
        else if( next_mem_state == MEM_OSSP_PCM2)            nn <= {pc_123};
1689
        else if(EXs6SP7_HL== ir2 & ir2dd & exec_ir2)         nn <= ixr;
1690
        else if(EXs6SP7_HL== ir2 & ir2fd & exec_ir2)         nn <= iyr;
1691
        else if(EXs6SP7_HL== ir2         & exec_ir2)          nn <= hl;
1692
        else if((INCs6HL7==ir2 | DECs6HL7==ir2) & exec_ir2)   nn[15:8] <= alu8_out;
1693
        else if( ir2_cb_shift & MEM_OSADR == next_mem_state ) nn[15:8] <= sh_alu;
1694
        else if( ir2_cb_bit   & MEM_OSADR == next_mem_state ) nn[15:8] <= bit_alu;
1695
        else if( ED_RRD == ir2 & MEM_OSADR == next_mem_state) nn[15:8] <= {ar[3:0], nn[15:12]};
1696
        else if( ED_RLD == ir2 & MEM_OSADR == next_mem_state) nn[15:8] <= {nn[11:8], ar[3:0] };
1697
 
1698
        else if (next_pipe_state[1])  nn  <= { wb_dat_i, nn[15:8] };   // ENN overides os stuff 
1699
        // these are the general cases with ir1 providing register specification
1700
        // let PUSH have priority  (we need os_h for some indexed stores  under ir1dd)  
1701
        else if (we_next & ir1 == PUSHsHL)  nn   <= hl_or_ixiy;   // use for PUSHsHL
1702
        else if(we_next & ( next_mem_state == MEM_OS1     |
1703
                            next_mem_state == MEM_OSIXpD  |
1704
                            next_mem_state == MEM_OSSP    |
1705
                            next_mem_state == MEM_IOS_N   |
1706
                            next_mem_state == MEM_IOS_C   |
1707
                            next_mem_state == MEM_OSNN     ) )
1708
            // oh my god  -- operands go out in different order to stack than they
1709
            // do to normal stores. Oh well, guess that makes ordering consistent in
1710
            // memory
1711
            begin
1712
                 if (os_a)     nn       <= {ar, fr };  // use for PUSHsAF 
1713
                 if (os_b)     nn       <= {br, cr };  // use for PUSHsBC
1714
                 if (os_c)     nn[15:8] <= cr;
1715
                 if (os_d)     nn       <= {dr, er };  // use for PUSHsDE
1716
                 if (os_e)     nn[15:8] <=  er;
1717
                 if (os_h)     nn       <= {hr, lr };
1718
                 if (os_l)     nn[15:8] <= lr;
1719
                 if (os_bc)    nn       <= {cr, br };
1720
                 if (os_de)    nn       <= {er, dr };
1721
                 if (os_sp)    nn       <= {sp[7:0], sp[15:8] };
1722
                 if (os_hl)    nn       <= {lr, hr };
1723
                 if (os_ixr)   nn       <= {ixr[7:0], ixr[15:8] };
1724
                 if (os_iyr)   nn       <= {iyr[7:0], iyr[15:8] };
1725
            end
1726
        // 4/19/2004 previously no if here - if not needed we don't need next_pipe_state[1] eithor
1727
    end
1728
 
1729
 
1730
 
1731
//-------------------  pc  and sp ----------------------------------------------------
1732
always @(posedge wb_clk_i or posedge rst_i)
1733
    if (rst_i)   pc <= 16'h0;
1734
    else if (wb_rdy_nhz)
1735
    begin
1736
        if (next_mem_state == MEM_DECPC) pc <= pc - 16'h1;  // decrementer could perhaps be shared.
1737
        if (next_mem_state == MEM_IFPP1) pc <= adr_alu;
1738
        if (next_mem_state == MEM_CALL ) pc <= nn;         //Use MEM_CALL to exchange pc<=>nn
1739
        if (next_mem_state == MEM_RST) pc <= adr_alu;
1740
        if (next_mem_state == MEM_JMPHL) pc <= adr_alu;
1741
        if (next_mem_state == MEM_OSSP_PCM2) pc <= { 10'h0, ir1[5:3], 3'h0} ;
1742
        if (next_mem_state == MEM_IFNN ) pc <= adr_alu;    //on jumps get adr+1 in pc immediately. 
1743
        if (next_mem_state == MEM_REL2PC) pc <= adr_alu;
1744
        if (next_mem_state == MEM_IFINT) pc <= adr_alu;  // like a jump  need adr+1 here
1745
    end
1746
 
1747
//---------------------------------- sp -----------------------------------------------------
1748
//
1749
// with pc updates are always made from ir1  as the PC is so critical to instruction flow.
1750
// (this of course creates the possibility of an "inst_hazard" - where data is stored in an 
1751
//   instruction already fetched - see below)
1752
// with sp the situation is not so simple. 
1753
// Issues - especially regarding hazards.  
1754
//
1755
//     LDsSP_NN     this should be done from ir2 - no hazard as active state is ALWAYS IF2
1756
//                
1757
//     ADDsHL_SP    The add is a pre-add so sp cannot be modified before inst is executed from ir2
1758
//     DECsSP       Just do it with ir1 at DEC_EXEC   gotcha need -- IFPP1 in general use ir2 -> hazard
1759
//     EXs6SP7_HL    rmw - no change to sp - no issue here
1760
//     INCsSP       Just do it with ir1 at DEC_EXEC          gotcha  -- IFPP1  use ir2 -> hazard
1761
//     LDsSP_HL     do from ir1 and use standard hazard logic  (if H or L is being 
1762
//                    updated -- wait)
1763
//       
1764
//     ED_LDs6NN7_REG   REG== SP     // needs to be done from ir2
1765
//     ED_LDsREG_6NN7   REG== SP     //  do from ir2 - no hazard as executed on IF2 - refill pipe
1766
wire ed_ld_spreg = (ED_LDsREG_6NN7 == {ir2[9:6],ir2[3:0]}) & (ir2[5:4] == DBL_REG_SP);
1767
 
1768
always @(posedge wb_clk_i )
1769
begin
1770
    if (exec_ir2 )   //  this has priority of course 
1771
        begin
1772
            if (LDsSP_NN   == ir2)   sp <= nn;
1773
            if (ed_ld_spreg)         sp <= nn;
1774
            if (  DECsSP   == ir2 )  sp <= add16;
1775
            if (  INCsSP   == ir2 )  sp <= add16;
1776
        end
1777
    if (wb_rdy_nhz)  //the no hazard term should kill these if any abvove is happening in parallel
1778
    begin
1779
         if (  LDsSP_HL == ir1 & dec_state == DEC_EXEC)  sp <= hl_or_ixiy;
1780
         if (  LDsSP_HL == ir1 & dec_state == DEC_DDFD)  sp <= hl_or_ixiy;
1781
         if (next_mem_state == MEM_OFSP      ) sp <= adr_alu;
1782
         if (next_mem_state == MEM_OSSP      ) sp <= adr_alu;
1783
         if (next_mem_state == MEM_OSSP_PCM2 ) sp <= adr_alu;
1784
         //if (next_mem_state == MEM_OSSP_P    ) sp <= adr_alu;
1785
         if (next_mem_state == MEM_CALL      ) sp <= adr_alu;
1786
    end
1787
end
1788
 
1789
//-------------------- int logic ----------------------------------------
1790
//  We have a wishbone interrupt system  -  which i guess does not preclude a 
1791
//  non-maskable interrupt......   but bottom line is that such an interrupt is 
1792
//  definately out of favor with current system thinking.   Within an embedded system
1793
//  ( the target application here ) a single interrupt controller  capable of handeling
1794
//   as many interrupts as desired is the best choice.  
1795
//  Therefore we enable only mode 2 interrupts and a single enable ff.
1796
//
1797
//  This begs the question of what to do with the "RETI" instruction  -- ED4D.  We opt to 
1798
//  enable interrupts with this instruction (and all its "aliases").
1799
//
1800
always @(posedge wb_clk_i or posedge rst_i)
1801
    if (rst_i)                   int_en <= 1'b0;
1802
    else if (wb_rdy_nhz)
1803
    begin
1804
        if      ((dec_state == DEC_EXEC) & (DI== ir1))  int_en <= 1'b0;
1805
        else if ((dec_state == DEC_EXEC) & en_int_next) int_en <= 1'b1;
1806
        if      (dec_state == DEC_INT1)                 int_en <= 1'b0;
1807
    end
1808
 
1809
 
1810
always @(posedge wb_clk_i or posedge rst_i)
1811
    if (rst_i)                                      en_int_next <=1'b0;
1812
    else if (wb_rdy_nhz)
1813
    begin
1814
        if ((dec_state == DEC_EXEC) & (EI== ir1))       en_int_next <=1'b1;
1815
        else if ((dec_state == DEC_RET ) & (ED_RETI == ir2)) en_int_next <=1'b1;
1816
        else if (dec_state == DEC_EXEC)                 en_int_next <=1'b0;
1817
    end
1818
 
1819
always @(posedge wb_clk_i)
1820
    wb_irq_sync <= int_req_i;
1821
 
1822
assign  wb_int = wb_irq_sync & int_en;
1823
 
1824
endmodule
1825
 

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