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[/] [vga_lcd/] [tags/] [beta/] [fifo.vhd] - Blame information for rev 62

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--
-- File fifo.vhd (universal FIFO)
-- Author : Richard Herveille
-- rev.: 0.1 May 04th, 2001
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity FIFO is
        generic(
                DEPTH : natural := 128;
                WIDTH : natural := 32
        );
        port(
                clk : in std_logic;                           -- clock input
                aclr : in std_logic := '1';                   -- active low asynchronous clear
                sclr : in std_logic := '0';                   -- active high synchronous clear
 
                D : in std_logic_vector(WIDTH -1 downto 0);   -- Data input
                wreq : in std_logic;                          -- write request
 
                Q : out std_logic_vector(WIDTH -1 downto 0);  -- Data output
                rreq : in std_logic;                          -- read request
 
                empty,                                        -- FIFO is empty
                hfull,                                        -- FIFO is half full
                full : out std_logic                          -- FIFO is full
        );
end entity FIFO;
 
architecture structural of FIFO is
        -- bitcount, return no.of bits required for 'n'
        function bitcount(n : in natural) return natural is
                variable tmp : unsigned(32 downto 1);
                variable cnt : integer;
        begin
                tmp := conv_unsigned(n, 32);
                cnt := 32;
 
                while ( (tmp(cnt) = '0') and (cnt > 0) ) loop
                        cnt := cnt -1;
                end loop;
 
                return natural(cnt);
        end function bitcount;
 
        constant ADEPTH : natural := bitcount(DEPTH -1); -- 256 entries: range 255 downto 0
 
        type mem_type is array (DEPTH -1 downto 0) of std_logic_vector(WIDTH -1 downto 0);
        signal mem : mem_type; -- VHDL '87 syntax
 
        signal rptr, wptr : unsigned(ADEPTH -1 downto 0);
        signal fifo_cnt : unsigned(ADEPTH downto 0);
begin
        -- read pointer
        gen_rd_ptr: process(clk, aclr)
        begin
                if (aclr = '0') then
                        rptr <= (others => '0');
                elsif (clk'event and clk = '1') then
                        if (sclr = '1') then
                                rptr <= (others => '0');
                        elsif (rreq = '1') then
                                rptr <= rptr +1;
                        end if;
                end if;
        end process gen_rd_ptr;
 
        -- write pointer
        gen_wr_ptr: process(clk, aclr)
        begin
                if (aclr = '0') then
                        wptr <= (others => '0');
                elsif (clk'event and clk = '1') then
                        if (sclr = '1') then
                                wptr <= (others => '0');
                        elsif (wreq = '1') then
                                wptr <= wptr +1;
                        end if;
                end if;
        end process gen_wr_ptr;
 
        -- memory array operations
        gen_mem: process(clk)
        begin
                if (clk'event and clk = '1') then
                        if (wreq = '1') then
                                mem(conv_integer(wptr)) <= D; -- store D in memory array
                        end if;
                end if;
        end process gen_mem;
        Q <= mem(conv_integer(rptr));    -- assign output
 
        -- number of words in fifo
        gen_fifo_cnt: process(clk, aclr, fifo_cnt, wreq, rreq)
                variable count : unsigned(ADEPTH downto 0);
        begin
                count := fifo_cnt;
 
                if (wreq = '1') then
                        count := count +1;
                end if;
                if (rreq = '1') then
                        count := count -1;
                end if;
 
                if (aclr = '0') then
                        fifo_cnt <= (others => '0');
                elsif (clk'event and clk = '1') then
                        if (sclr = '1') then
                                fifo_cnt <= (others => '0');
                        else
                                fifo_cnt <= count;
                        end if;
                end if;
        end process gen_fifo_cnt;
 
        -- status flags
        empty <= '1' when (fifo_cnt = 0) else '0';
        hfull <= fifo_cnt(ADEPTH -1);
        full  <= fifo_cnt(ADEPTH);
end architecture structural;

Line No.	Rev	Author	Line
1	2	rherveille	`--`
2			`-- File fifo.vhd (universal FIFO)`
3			`-- Author : Richard Herveille`
4			`-- rev.: 0.1 May 04th, 2001`
5			`--`
6
7			`library ieee;`
8			`use ieee.std_logic_1164.all;`
9			`use ieee.std_logic_arith.all;`
10
11			`entity FIFO is`
12			`generic(`
13			`DEPTH : natural := 128;`
14			`WIDTH : natural := 32`
15			`);`
16			`port(`
17			`clk : in std_logic; -- clock input`
18			`aclr : in std_logic := '1'; -- active low asynchronous clear`
19			`sclr : in std_logic := '0'; -- active high synchronous clear`
20
21			`D : in std_logic_vector(WIDTH -1 downto 0); -- Data input`
22			`wreq : in std_logic; -- write request`
23
24			`Q : out std_logic_vector(WIDTH -1 downto 0); -- Data output`
25			`rreq : in std_logic; -- read request`
26
27			`empty, -- FIFO is empty`
28			`hfull, -- FIFO is half full`
29			`full : out std_logic -- FIFO is full`
30			`);`
31			`end entity FIFO;`
32
33			`architecture structural of FIFO is`
34			`-- bitcount, return no.of bits required for 'n'`
35			`function bitcount(n : in natural) return natural is`
36			`variable tmp : unsigned(32 downto 1);`
37			`variable cnt : integer;`
38			`begin`
39			`tmp := conv_unsigned(n, 32);`
40			`cnt := 32;`
41
42			`while ( (tmp(cnt) = '0') and (cnt > 0) ) loop`
43			`cnt := cnt -1;`
44			`end loop;`
45
46			`return natural(cnt);`
47			`end function bitcount;`
48
49			`constant ADEPTH : natural := bitcount(DEPTH -1); -- 256 entries: range 255 downto 0`
50
51			`type mem_type is array (DEPTH -1 downto 0) of std_logic_vector(WIDTH -1 downto 0);`
52			`signal mem : mem_type; -- VHDL '87 syntax`
53
54			`signal rptr, wptr : unsigned(ADEPTH -1 downto 0);`
55			`signal fifo_cnt : unsigned(ADEPTH downto 0);`
56			`begin`
57			`-- read pointer`
58			`gen_rd_ptr: process(clk, aclr)`
59			`begin`
60			`if (aclr = '0') then`
61			`rptr <= (others => '0');`
62			`elsif (clk'event and clk = '1') then`
63			`if (sclr = '1') then`
64			`rptr <= (others => '0');`
65			`elsif (rreq = '1') then`
66			`rptr <= rptr +1;`
67			`end if;`
68			`end if;`
69			`end process gen_rd_ptr;`
70
71			`-- write pointer`
72			`gen_wr_ptr: process(clk, aclr)`
73			`begin`
74			`if (aclr = '0') then`
75			`wptr <= (others => '0');`
76			`elsif (clk'event and clk = '1') then`
77			`if (sclr = '1') then`
78			`wptr <= (others => '0');`
79			`elsif (wreq = '1') then`
80			`wptr <= wptr +1;`
81			`end if;`
82			`end if;`
83			`end process gen_wr_ptr;`
84
85			`-- memory array operations`
86			`gen_mem: process(clk)`
87			`begin`
88			`if (clk'event and clk = '1') then`
89			`if (wreq = '1') then`
90			`mem(conv_integer(wptr)) <= D; -- store D in memory array`
91			`end if;`
92			`end if;`
93			`end process gen_mem;`
94			`Q <= mem(conv_integer(rptr)); -- assign output`
95
96			`-- number of words in fifo`
97			`gen_fifo_cnt: process(clk, aclr, fifo_cnt, wreq, rreq)`
98			`variable count : unsigned(ADEPTH downto 0);`
99			`begin`
100			`count := fifo_cnt;`
101
102			`if (wreq = '1') then`
103			`count := count +1;`
104			`end if;`
105			`if (rreq = '1') then`
106			`count := count -1;`
107			`end if;`
108
109			`if (aclr = '0') then`
110			`fifo_cnt <= (others => '0');`
111			`elsif (clk'event and clk = '1') then`
112			`if (sclr = '1') then`
113			`fifo_cnt <= (others => '0');`
114			`else`
115			`fifo_cnt <= count;`
116			`end if;`
117			`end if;`
118			`end process gen_fifo_cnt;`
119
120			`-- status flags`
121			`empty <= '1' when (fifo_cnt = 0) else '0';`
122			`hfull <= fifo_cnt(ADEPTH -1);`
123			`full <= fifo_cnt(ADEPTH);`
124			`end architecture structural;`

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[/] [vga_lcd/] [tags/] [beta/] [fifo.vhd] - Blame information for rev 62