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rherveille |
--
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-- File pgen.vhd, Video Pixel Generator
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-- Project: VGA
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-- Author : Richard Herveille
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-- rev.: 0.1 April 19th, 2001
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--
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity Pgen is
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port(
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mclk : in std_logic; -- master clock
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pclk : in std_logic; -- pixel clock
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ctrl_Ven : in std_logic; -- VideoEnable signal
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-- horizontal timing settings
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ctrl_HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg)
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Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels)
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Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels)
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Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line)
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Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line)
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-- vertical timing settings
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ctrl_VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg)
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Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines)
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Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines)
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Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame)
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Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame)
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ctrl_CSyncL : in std_logic; -- composite sync pulse polarization level
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ctrl_BlankL : in std_logic; -- blank signal polarization level
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-- status outputs
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eoh, -- end of horizontal
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eov, -- end of vertical
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Gate : out std_logic; -- vertical AND horizontal gate (logical AND function)
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-- pixel control outputs
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Hsync, -- horizontal sync pulse
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Vsync, -- vertical sync pulse
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Csync, -- composite sync: Hsync OR Vsync (logical OR function)
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Blank : out std_logic -- blank signals
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);
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end entity Pgen;
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architecture dataflow of Pgen is
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--
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-- Component declarations
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--
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component tgen is
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- horizontal timing settings
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HSyncL : in std_logic; -- horizontal sync pulse polarization level (pos/neg)
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Thsync : in unsigned(7 downto 0); -- horizontal sync pulse width (in pixels)
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Thgdel : in unsigned(7 downto 0); -- horizontal gate delay (in pixels)
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Thgate : in unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line)
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Thlen : in unsigned(15 downto 0); -- horizontal length (number of pixels per line)
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-- vertical timing settings
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VSyncL : in std_logic; -- vertical sync pulse polarization level (pos/neg)
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Tvsync : in unsigned(7 downto 0); -- vertical sync width (in lines)
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Tvgdel : in unsigned(7 downto 0); -- vertical gate delay (in lines)
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Tvgate : in unsigned(15 downto 0); -- vertical gate (visible number of lines in frame)
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Tvlen : in unsigned(15 downto 0); -- vertical length (number of lines in frame)
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CSyncL : in std_logic; -- composite sync pulse polarization level (pos/neg)
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BlankL : in std_logic; -- blank signal polarization level
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eol, -- end of line
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eof, -- end of frame
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gate, -- vertical AND horizontal gate (logical and function)
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Hsync, -- horizontal sync pulse
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Vsync, -- vertical sync pulse
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Csync, -- composite sync pulse
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Blank : out std_logic -- blank signal
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);
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end component tgen;
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--
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-- signals
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--
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signal eol, eof : std_logic;
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begin
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--
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-- timing block
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--
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tblk: block
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signal nVen : std_logic; -- video enable signal (active low)
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signal sHSyncL : std_logic; -- horizontal sync pulse polarization level (pos/neg)
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signal sThsync : unsigned(7 downto 0); -- horizontal sync pulse width (in pixels)
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signal sThgdel : unsigned(7 downto 0); -- horizontal gate delay (in pixels)
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signal sThgate : unsigned(15 downto 0); -- horizontal gate (number of visible pixels per line)
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signal sThlen : unsigned(15 downto 0); -- horizontal length (number of pixels per line)
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-- vertical timing settings
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signal sVSyncL : std_logic; -- vertical sync pulse polarization level (pos/neg)
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signal sTvsync : unsigned(7 downto 0); -- vertical sync width (in lines)
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signal sTvgdel : unsigned(7 downto 0); -- vertical gate delay (in lines)
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signal sTvgate : unsigned(15 downto 0); -- vertical gate (visible number of lines in frame)
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signal sTvlen : unsigned(15 downto 0); -- vertical length (number of lines in frame)
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signal sCSyncL : std_logic; -- composite sync pulse polarization level (pos/neg)
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signal sBlankL : std_logic; -- blank signal polarization level
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begin
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-- synchronize timing/control settings (from master-clock-domain to pixel-clock-domain)
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sync_settings: process(pclk)
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begin
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if (pclk'event and pclk = '1') then
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nVen <= not ctrl_Ven;
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sHSyncL <= ctrl_HSyncL;
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sThsync <= Thsync;
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sThgdel <= Thgdel;
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sThgate <= Thgate;
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sThlen <= Thlen;
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sVSyncL <= ctrl_VSyncL;
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sTvsync <= Tvsync;
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sTvgdel <= Tvgdel;
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sTvgate <= Tvgate;
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sTvlen <= Tvlen;
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sCSyncL <= ctrl_CSyncL;
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sBlankL <= ctrl_BlankL;
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end if;
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end process sync_settings;
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-- hookup video timing generator
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vtgen: tgen port map (clk => pclk, rst => nVen, HSyncL => sHSyncL, Thsync => sThsync, Thgdel => sThgdel, Thgate => sThgate, Thlen => sThlen,
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VsyncL => sVsyncL, Tvsync => sTvsync, Tvgdel => sTvgdel, Tvgate => sTvgate, Tvlen => sTvlen, CSyncL => sCSyncL,
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BlankL => sBlankL, eol => eol, eof => eof, gate => gate, Hsync => Hsync, Vsync => Vsync, Csync => Csync, Blank => Blank);
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end block tblk;
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--
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-- pixel clock
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--
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pblk: block
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signal seol, seof : std_logic; -- synchronized end-of-line, end-of-frame
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signal dseol, dseof : std_logic; -- delayed synchronized eol, eof
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begin
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-- synchronize eol, eof (from pixel-clock-domain to master-clock-domain)
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sync_eol_eof: process(mclk)
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begin
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if (mclk'event and mclk = '1') then
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seol <= eol;
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dseol <= seol;
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seof <= eof;
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dseof <= seof;
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eoh <= seol and not dseol;
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eov <= seof and not dseof;
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end if;
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end process sync_eol_eof;
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end block pblk;
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end architecture dataflow;
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