URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [test_bench_top.v] - Blame information for rev 26

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_bench_top.v,v 1.3 2002-01-28 03:40:30 rherveille Exp $
//
//  $Date: 2002-01-28 03:40:30 $
//  $Revision: 1.3 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//                        
 
`timescale 1ns / 10ps
 
module test;
 
reg             clk;
reg             rst;
wire            clk_v;
 
parameter       LINE_FIFO_AWIDTH = 7;
 
wire            int;
wire    [31:0]   wb_addr_o;
wire    [31:0]   wb_data_i;
wire    [31:0]   wb_data_o;
wire    [3:0]    wb_sel_o;
wire            wb_we_o;
wire            wb_stb_o;
wire            wb_cyc_o;
wire            wb_ack_i;
wire            wb_err_i;
wire    [31:0]   wb_addr_i;
wire    [31:0]   wbm_data_i;
wire    [3:0]    wb_sel_i;
wire            wb_we_i;
wire            wb_stb_i;
wire            wb_cyc_i;
wire            wb_ack_o;
wire            wb_err_o;
reg             pclk;
wire            hsync;
wire            vsync;
wire            csync;
wire            blanc;
wire    [7:0]    red;
wire    [7:0]    green;
wire    [7:0]    blue;
 
wire vga_stb_i;
wire clut_stb_i;
 
reg             scen;
 
// Test Bench Variables
integer         wd_cnt;
integer         error_cnt;
 
// Misc Variables
reg     [31:0]   data;
reg     [31:0]   pattern;
reg             int_warn;
 
integer         n;
integer         mode;
 
reg     [7:0]    thsync, thgdel;
reg     [15:0]   thgate, thlen;
reg     [7:0]    tvsync, tvgdel;
reg     [15:0]   tvgate, tvlen;
reg             hpol;
reg             vpol;
reg             cpol;
reg             bpol;
integer         p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   vbase;
reg     [31:0]   cbase;
reg     [31:0]   vbara;
reg     [31:0]   vbarb;
reg     [7:0]    bank;
 
/////////////////////////////////////////////////////////////////////
//
// Defines 
//
 
`define CTRL            32'h0000_0000
`define STAT            32'h0000_0004
`define HTIM            32'h0000_0008
`define VTIM            32'h0000_000c
`define HVLEN           32'h0000_0010
`define VBARA           32'h0000_0014
`define VBARB           32'h0000_0018
 
`define USE_VC          1
 
parameter       PCLK_C = 13;
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
initial
   begin
        $timeformat (-9, 1, " ns", 12);
        $display("\n\n");
        $display("******************************************************");
        $display("* WISHBONE VGA/LCD Controller Simulation started ... *");
        $display("******************************************************");
        $display("\n");
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        scen = 0;
        error_cnt = 0;
        clk = 0;
        pclk = 0;
        rst = 0;
        int_warn=1;
 
        repeat(20)      @(posedge clk);
        rst = 1;
        s0.delay = 1;
        repeat(20)      @(posedge clk);
 
        // HERE IS WHERE THE TEST CASES GO ...
 
if(0)    // Full Regression Run
   begin
 
   end
else
if(1)   // Quick Regression Run
   begin
        //reg_test;
        //tim_test;
        //pd1_test;
        pd2_test;
        //ur_test;
   end
else
   begin
 
        //
        // TEST DEVELOPMENT AREA
        //
$display("\n\n");
$display("*****************************************************");
$display("*** XXX Test                                 ***");
$display("*****************************************************\n");
 
        s0.fill_mem(1);
 
        repeat(10)      @(posedge clk);
 
        vbara = 32'h0000_0000;
        vbarb = 32'h0001_0000;
 
        m0.wb_wr1( `VBARA, 4'hf, vbara );
        m0.wb_wr1( `VBARB, 4'hf, vbarb );
 
        thsync = 0;
        thgdel = 0;
        thgate = 340;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
mode = 2;
 
//for(mode=0;mode<1;mode=mode+1)
for(bank=0;bank<3;bank=bank + 1)
   begin
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'h0,   // VBL
                                1'b0,   // Reserved
                                1'b1,   // CBSWE
                                1'b1,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        $display("Mode: %0d Screen: %0d", mode, bank);
        //repeat(2) @(posedge vsync);
        @(posedge vsync);
 
        // For Each Line
        for(l=0;l<tvgate+1;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                if(bank[0])      vbase = vbarb[31:2];
                else            vbase = vbara[31:2];
                if(bank[0])      cbase = 32'h0000_0c00;
                else            cbase = 32'h0000_0800;
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                   0:    // 24 bit/pixel mode
                   begin
                        pra = pn[31:2] * 3;     // Pixel relative Address
                        paa = pra + vbase;              // Pixel Absolute Address
 
                        // Pixel Data
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = tmp[31:8];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd[23:16] = tmp[7:0];
                                tmp = s0.mem[paa+1];
                                pd[15:0] = tmp[31:16];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa+1];
                                pd[23:8] = tmp[15:0];
                                tmp = s0.mem[paa+2];
                                pd[7:0] = tmp[31:24];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa+2];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   1:   // 8 bit/pixel grayscale mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                             end
                        endcase
                   end
 
                   2:   // 8 bit/pixel Pseudo Color mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[31:24]];
                                pd = tmp[23:0];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[23:16]];
                                pd = tmp[23:0];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[15:8]];
                                pd = tmp[23:0];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[7:0]];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   3:   // 16 bit/pixel mode
                   begin
                        pra = pn[31:1];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp[15:0] = tmp[31:16];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                        endcase
                   end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                   end
 
                @(posedge pclk);
 
           end
   end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
 
   end
 
        repeat(10)      @(posedge clk);
        $finish;
   end
 
/////////////////////////////////////////////////////////////////////
//
// Sync Monitor
//
 
sync_check #(PCLK_C) uceck(
                .pclk(          pclk            ),
                .rst(           rst             ),
                .enable(        scen            ),
                .hsync(         hsync           ),
                .vsync(         vsync           ),
                .csync(         csync           ),
                .blanc(         blanc           ),
                .hpol(          hpol            ),
                .vpol(          vpol            ),
                .cpol(          cpol            ),
                .bpol(          bpol            ),
                .thsync(        thsync          ),
                .thgdel(        thgdel          ),
                .thgate(        thgate          ),
                .thlen(         thlen           ),
                .tvsync(        tvsync          ),
                .tvgdel(        tvgdel          ),
                .tvgate(        tvgate          ),
                .tvlen(         tvlen           ) );
 
/////////////////////////////////////////////////////////////////////
//
// Video Data Monitor
//
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
always @(posedge clk)
        if(wb_cyc_i | wb_cyc_o | wb_ack_i | wb_ack_o | hsync)   wd_cnt <= #1 0;
        else                                            wd_cnt <= #1 wd_cnt + 1;
 
 
always @(wd_cnt)
        if(wd_cnt>9000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
 
always @(posedge int)
  if(int_warn)
   begin
        $display("\n\n*************************************\n");
        $display("WARNING: Recieved Interrupt (%0t)", $time);
        $display("*************************************\n\n\n");
   end
 
always #2.5             clk = ~clk;
always #(PCLK_C/2)      pclk = ~pclk;
 
assign clk_v = clk;
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE DMA IP Core
//
 
 
// Module Prototype
 
`ifdef USE_VC
vga_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
                .wb_clk_i(              clk             ),
                .wb_rst_i(              1'b0 ),
                .rst_i(         rst             ),
                .wb_inta_o(             int             ),
 
                //-- slave signals
                .wbs_adr_i(             wb_addr_i[11:0]  ),
                .wbs_dat_i(             wb_data_i       ),
                .wbs_dat_o(             wb_data_o       ),
                .wbs_sel_i(             wb_sel_i        ),
                .wbs_we_i(              wb_we_i         ),
                .wbs_stb_i(             wb_stb_i        ),
                .wbs_cyc_i(             wb_cyc_i        ),
                .wbs_ack_o(             wb_ack_o        ),
                .wbs_err_o(             wb_err_o        ),
 
                //-- master signals
                .wbm_adr_o(             wb_addr_o[31:0]  ),
                .wbm_dat_i(             wbm_data_i      ),
                .wbm_sel_o(             wb_sel_o        ),
                .wbm_we_o(              wb_we_o         ),
                .wbm_stb_o(             wb_stb_o        ),
                .wbm_cyc_o(             wb_cyc_o        ),
                .wbm_cab_o(                             ),
                .wbm_ack_i(             wb_ack_i        ),
                .wbm_err_i(             wb_err_i        ),
 
                //-- VGA signals
                .clk_p_i(               pclk            ),
                .hsync_pad_o(   hsync           ),
                .vsync_pad_o(   vsync           ),
                .csync_pad_o(   csync           ),
                .blank_pad_o(   blanc           ),
                .r_pad_o(               red             ),
                .g_pad_o(               green           ),
                .b_pad_o(               blue            )
        );
 
`else
 
VGA u0 (        .CLK_I( clk_v           ),
                .RST_I(         ~rst            ),
                .NRESET(        rst             ),
                .INTA_O(        int             ),
 
                //-- slave signals
                .ADR_I(         wb_addr_i[4:2]  ),
                .SDAT_I(        wb_data_i       ),
                .SDAT_O(        wb_data_o       ),
                .SEL_I(         wb_sel_i        ),
                .WE_I(          wb_we_i         ),
                .STB_I(         wb_stb_i        ),
                .CYC_I(         wb_cyc_i        ),
                .ACK_O(         wb_ack_o        ),
                .ERR_O(         wb_err_o        ),
 
                //-- master signals
                .ADR_O(         wb_addr_o[31:2] ),
                .MDAT_I(        wbm_data_i      ),
                .SEL_O(         wb_sel_o        ),
                .WE_O(          wb_we_o         ),
                .STB_O(         wb_stb_o        ),
                .CYC_O(         wb_cyc_o        ),
                .CAB_O(                         ),
                .ACK_I(         wb_ack_i        ),
                .ERR_I(         wb_err_i        ),
 
                //-- VGA signals
                .PCLK(          pclk            ),
                .HSYNC(         hsync           ),
                .VSYNC(         vsync           ),
                .CSYNC(         csync           ),
                .BLANK(         blanc           ),
                .R(             red             ),
                .G(             green           ),
                .B(             blue            )
        );
 
`endif
 
wb_mast m0(     .clk(           clk             ),
                .rst(           rst             ),
                .adr(           wb_addr_i       ),
                .din(           wb_data_o       ),
                .dout(          wb_data_i       ),
                .cyc(           wb_cyc_i        ),
                .stb(           wb_stb_i        ),
                .sel(           wb_sel_i        ),
                .we(            wb_we_i         ),
                .ack(           wb_ack_o        ),
                .err(           wb_err_o        ),
                .rty(           1'b0            )
                );
 
wb_slv #(24) s0(.clk(           clk             ),
                .rst(           rst             ),
                .adr(           {1'b0, wb_addr_o[30:0]}  ),
                .din(           32'h0           ),
                .dout(          wbm_data_i      ),
                .cyc(           wb_cyc_o        ),
                .stb(           wb_stb_o        ),
                .sel(           wb_sel_o        ),
                .we(            wb_we_o         ),
                .ack(           wb_ack_i        ),
                .err(           wb_err_i        ),
                .rty(                           )
                );
 
`include "tests.v"
 
endmodule
 
/*
module vdata_mon(clk, rst, hsync, vsync, blank, pixel, line);
input           clk, rst;
input           hsync, vsync, blank;
output  [31:0]  pixel, line;
 
reg     [31:0]  pixel, line;
 
always @(negedge blank)
        line = line + 1;
 
always @(posedge vsync or negedge rst)
        line = -1;
 
always @(posedge clk)
        if(!blank)      pixel = pixel + 1;
        else            pixel = 0;
 
endmodule
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Browse

Tools

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [test_bench_top.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	26	rherveille	`// $Id: test_bench_top.v,v 1.3 2002-01-28 03:40:30 rherveille Exp $`
41	16	rudi	`//`
42	26	rherveille	`// $Date: 2002-01-28 03:40:30 $`
43			`// $Revision: 1.3 $`
44	24	rherveille	`// $Author: rherveille $`
45	16	rudi	`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53			`//`
54
55			`timescale 1ns / 10ps
56
57			`module test;`
58
59			`reg clk;`
60			`reg rst;`
61			`wire clk_v;`
62
63			`parameter LINE_FIFO_AWIDTH = 7;`
64
65			`wire int;`
66			`wire [31:0] wb_addr_o;`
67			`wire [31:0] wb_data_i;`
68			`wire [31:0] wb_data_o;`
69			`wire [3:0] wb_sel_o;`
70			`wire wb_we_o;`
71			`wire wb_stb_o;`
72			`wire wb_cyc_o;`
73			`wire wb_ack_i;`
74			`wire wb_err_i;`
75			`wire [31:0] wb_addr_i;`
76			`wire [31:0] wbm_data_i;`
77			`wire [3:0] wb_sel_i;`
78			`wire wb_we_i;`
79			`wire wb_stb_i;`
80			`wire wb_cyc_i;`
81			`wire wb_ack_o;`
82			`wire wb_err_o;`
83			`reg pclk;`
84			`wire hsync;`
85			`wire vsync;`
86			`wire csync;`
87			`wire blanc;`
88			`wire [7:0] red;`
89			`wire [7:0] green;`
90			`wire [7:0] blue;`
91
92	24	rherveille	`wire vga_stb_i;`
93			`wire clut_stb_i;`
94	16	rudi
95			`reg scen;`
96
97			`// Test Bench Variables`
98			`integer wd_cnt;`
99			`integer error_cnt;`
100
101			`// Misc Variables`
102			`reg [31:0] data;`
103			`reg [31:0] pattern;`
104			`reg int_warn;`
105
106			`integer n;`
107			`integer mode;`
108
109			`reg [7:0] thsync, thgdel;`
110			`reg [15:0] thgate, thlen;`
111			`reg [7:0] tvsync, tvgdel;`
112			`reg [15:0] tvgate, tvlen;`
113			`reg hpol;`
114			`reg vpol;`
115			`reg cpol;`
116			`reg bpol;`
117			`integer p, l;`
118			`reg [31:0] pn;`
119			`reg [31:0] pra, paa, tmp;`
120			`reg [23:0] pd;`
121			`reg [1:0] cd;`
122			`reg pc;`
123			`reg [31:0] vbase;`
124			`reg [31:0] cbase;`
125			`reg [31:0] vbara;`
126			`reg [31:0] vbarb;`
127			`reg [7:0] bank;`
128
129			`/////////////////////////////////////////////////////////////////////`
130			`//`
131			`// Defines`
132			`//`
133
134			`define CTRL 32'h0000_0000
135			`define STAT 32'h0000_0004
136			`define HTIM 32'h0000_0008
137			`define VTIM 32'h0000_000c
138			`define HVLEN 32'h0000_0010
139			`define VBARA 32'h0000_0014
140			`define VBARB 32'h0000_0018
141
142			`define USE_VC 1
143
144	24	rherveille	`parameter PCLK_C = 13;`
145
146	16	rudi	`/////////////////////////////////////////////////////////////////////`
147			`//`
148			`// Simulation Initialization and Start up Section`
149			`//`
150
151			`initial`
152			`begin`
153			`$timeformat (-9, 1, " ns", 12);`
154			`$display("\n\n");`
155			`$display("******************************************************");`
156			`$display("* WISHBONE VGA/LCD Controller Simulation started ... *");`
157			`$display("******************************************************");`
158			`$display("\n");`
159			`ifdef WAVES
160			`$shm_open("waves");`
161			`$shm_probe("AS",test,"AS");`
162			`$display("INFO: Signal dump enabled ...\n\n");`
163			`endif
164			`scen = 0;`
165			`error_cnt = 0;`
166			`clk = 0;`
167			`pclk = 0;`
168			`rst = 0;`
169			`int_warn=1;`
170
171			`repeat(20) @(posedge clk);`
172			`rst = 1;`
173			`s0.delay = 1;`
174			`repeat(20) @(posedge clk);`
175
176			`// HERE IS WHERE THE TEST CASES GO ...`
177
178			`if(0) // Full Regression Run`
179			`begin`
180
181			`end`
182			`else`
183			`if(1) // Quick Regression Run`
184			`begin`
185			`//reg_test;`
186	24	rherveille	`//tim_test;`
187			`//pd1_test;`
188	16	rudi	`pd2_test;`
189	24	rherveille	`//ur_test;`
190	16	rudi	`end`
191			`else`
192			`begin`
193
194			`//`
195			`// TEST DEVELOPMENT AREA`
196			`//`
197			`$display("\n\n");`
198			`$display("*****************************************************");`
199			`$display("* XXX Test *");`
200			`$display("*****************************************************\n");`
201
202			`s0.fill_mem(1);`
203
204			`repeat(10) @(posedge clk);`
205
206			`vbara = 32'h0000_0000;`
207			`vbarb = 32'h0001_0000;`
208
209			m0.wb_wr1( `VBARA, 4'hf, vbara );
210			m0.wb_wr1( `VBARB, 4'hf, vbarb );
211
212			`thsync = 0;`
213			`thgdel = 0;`
214			`thgate = 340;`
215			`thlen = 345;`
216
217			`tvsync = 0;`
218			`tvgdel = 0;`
219			`tvgate = 240;`
220			`tvlen = 245;`
221
222			`/*`
223			`thsync = 0;`
224			`thgdel = 0;`
225			`thgate = 63;`
226			`thlen = 70;`
227
228			`tvsync = 0;`
229			`tvgdel = 0;`
230			`tvgate = 32;`
231			`tvlen = 36;`
232			`*/`
233
234			`hpol = 0;`
235			`vpol = 0;`
236			`cpol = 0;`
237			`bpol = 0;`
238
239			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
240			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
241			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
242
243			`mode = 2;`
244
245			`//for(mode=0;mode<1;mode=mode+1)`
246			`for(bank=0;bank<3;bank=bank + 1)`
247			`begin`
248			`case(mode)`
249			`0:`
250			`begin`
251			`cd = 2'h2;`
252			`pc = 1'b0;`
253			`end`
254			`1:`
255			`begin`
256			`cd = 2'h0;`
257			`pc = 1'b0;`
258			`end`
259			`2:`
260			`begin`
261			`cd = 2'h0;`
262			`pc = 1'b1;`
263			`end`
264			`3:`
265			`begin`
266			`cd = 2'h1;`
267			`pc = 1'b0;`
268			`end`
269			`endcase`
270
271			m0.wb_wr1( `CTRL, 4'hf, {
272			`16'h0, // Reserved`
273			`bpol, cpol,`
274			`vpol, hpol,`
275			`pc, // 1'b0, // PC`
276			`cd, // 2'h2, // CD`
277			`2'h0, // VBL`
278			`1'b0, // Reserved`
279			`1'b1, // CBSWE`
280			`1'b1, // VBSWE`
281			`1'b0, // BSIE`
282			`1'b0, // HIE`
283			`1'b0, // VIE`
284			`1'b1 // Video Enable`
285			`});`
286
287			`$display("Mode: %0d Screen: %0d", mode, bank);`
288			`//repeat(2) @(posedge vsync);`
289			`@(posedge vsync);`
290
291			`// For Each Line`
292			`for(l=0;l<tvgate+1;l=l+1)`
293			`// For each Pixel`
294			`for(p=0;p<thgate+1;p=p+1)`
295			`begin`
296			`while(blanc) @(posedge pclk); // wait for viewable data`
297
298			`//$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);`
299
300			`if(bank[0]) vbase = vbarb[31:2];`
301			`else vbase = vbara[31:2];`
302	24	rherveille	`if(bank[0]) cbase = 32'h0000_0c00;`
303			`else cbase = 32'h0000_0800;`
304	16	rudi
305			`// Depending on Mode, determine pixel data`
306			`// pixel number = line * (thgate + 1) + p`
307			`pn = l * (thgate + 1) + p;`
308
309			`case(mode)`
310			`0: // 24 bit/pixel mode`
311			`begin`
312			`pra = pn[31:2] * 3; // Pixel relative Address`
313			`paa = pra + vbase; // Pixel Absolute Address`
314
315			`// Pixel Data`
316			`case(pn[1:0])`
317			`0:`
318			`begin`
319			`tmp = s0.mem[paa];`
320			`pd = tmp[31:8];`
321			`end`
322			`1:`
323			`begin`
324			`tmp = s0.mem[paa];`
325			`pd[23:16] = tmp[7:0];`
326			`tmp = s0.mem[paa+1];`
327			`pd[15:0] = tmp[31:16];`
328			`end`
329			`2:`
330			`begin`
331			`tmp = s0.mem[paa+1];`
332			`pd[23:8] = tmp[15:0];`
333			`tmp = s0.mem[paa+2];`
334			`pd[7:0] = tmp[31:24];`
335			`end`
336			`3:`
337			`begin`
338			`tmp = s0.mem[paa+2];`
339			`pd = tmp[23:0];`
340			`end`
341			`endcase`
342			`end`
343
344			`1: // 8 bit/pixel grayscale mode`
345			`begin`
346			`pra = pn[31:2]; // Pixel relative Address`
347			`paa = pra + vbase; // Pixel Absolute Address`
348			`case(pn[1:0])`
349			`0:`
350			`begin`
351			`tmp = s0.mem[paa];`
352			`pd = { tmp[31:24], tmp[31:24], tmp[31:24] };`
353			`end`
354			`1:`
355			`begin`
356			`tmp = s0.mem[paa];`
357			`pd = { tmp[23:16], tmp[23:16], tmp[23:16] };`
358			`end`
359			`2:`
360			`begin`
361			`tmp = s0.mem[paa];`
362			`pd = { tmp[15:8], tmp[15:8], tmp[15:8] };`
363			`end`
364			`3:`
365			`begin`
366			`tmp = s0.mem[paa];`
367			`pd = { tmp[7:0], tmp[7:0], tmp[7:0] };`
368			`end`
369			`endcase`
370			`end`
371
372			`2: // 8 bit/pixel Pseudo Color mode`
373			`begin`
374			`pra = pn[31:2]; // Pixel relative Address`
375			`paa = pra + vbase; // Pixel Absolute Address`
376			`case(pn[1:0])`
377			`0:`
378			`begin`
379			`tmp = s0.mem[paa];`
380			`tmp = s0.mem[cbase[31:2] + tmp[31:24]];`
381			`pd = tmp[23:0];`
382			`end`
383			`1:`
384			`begin`
385			`tmp = s0.mem[paa];`
386			`tmp = s0.mem[cbase[31:2] + tmp[23:16]];`
387			`pd = tmp[23:0];`
388			`end`
389			`2:`
390			`begin`
391			`tmp = s0.mem[paa];`
392			`tmp = s0.mem[cbase[31:2] + tmp[15:8]];`
393			`pd = tmp[23:0];`
394			`end`
395			`3:`
396			`begin`
397			`tmp = s0.mem[paa];`
398			`tmp = s0.mem[cbase[31:2] + tmp[7:0]];`
399			`pd = tmp[23:0];`
400			`end`
401			`endcase`
402			`end`
403
404			`3: // 16 bit/pixel mode`
405			`begin`
406			`pra = pn[31:1]; // Pixel relative Address`
407			`paa = pra + vbase; // Pixel Absolute Address`
408			`case(pn[0])`
409			`0:`
410			`begin`
411			`tmp = s0.mem[paa];`
412			`tmp[15:0] = tmp[31:16];`
413			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
414			`end`
415			`1:`
416			`begin`
417			`tmp = s0.mem[paa];`
418			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
419			`end`
420			`endcase`
421			`end`
422
423			`endcase`
424
425			`if(pd !== {red, green, blue} )`
426			`begin`
427			`$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",`
428			`pd, red, green, blue);`
429			`$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);`
430			`error_cnt = error_cnt + 1;`
431			`end`
432
433			`@(posedge pclk);`
434
435			`end`
436			`end`
437
438			`show_errors;`
439			`$display("*****************************************************");`
440			`$display("* Test DONE ... *");`
441			`$display("*****************************************************\n\n");`
442
443
444			`end`
445
446			`repeat(10) @(posedge clk);`
447			`$finish;`
448			`end`
449
450			`/////////////////////////////////////////////////////////////////////`
451			`//`
452			`// Sync Monitor`
453			`//`
454
455			`sync_check #(PCLK_C) uceck(`
456			`.pclk( pclk ),`
457			`.rst( rst ),`
458			`.enable( scen ),`
459			`.hsync( hsync ),`
460			`.vsync( vsync ),`
461			`.csync( csync ),`
462			`.blanc( blanc ),`
463			`.hpol( hpol ),`
464			`.vpol( vpol ),`
465			`.cpol( cpol ),`
466			`.bpol( bpol ),`
467			`.thsync( thsync ),`
468			`.thgdel( thgdel ),`
469			`.thgate( thgate ),`
470			`.thlen( thlen ),`
471			`.tvsync( tvsync ),`
472			`.tvgdel( tvgdel ),`
473			`.tvgate( tvgate ),`
474			`.tvlen( tvlen ) );`
475
476			`/////////////////////////////////////////////////////////////////////`
477			`//`
478			`// Video Data Monitor`
479			`//`
480
481			`/////////////////////////////////////////////////////////////////////`
482			`//`
483			`// Watchdog Counter`
484			`//`
485
486			`always @(posedge clk)`
487			`if(wb_cyc_i \| wb_cyc_o \| wb_ack_i \| wb_ack_o \| hsync) wd_cnt <= #1 0;`
488			`else wd_cnt <= #1 wd_cnt + 1;`
489
490
491			`always @(wd_cnt)`
492			`if(wd_cnt>9000)`
493			`begin`
494			`$display("\n\n*************************************\n");`
495			`$display("ERROR: Watch Dog Counter Expired\n");`
496			`$display("*************************************\n\n\n");`
497			`$finish;`
498			`end`
499
500
501			`always @(posedge int)`
502			`if(int_warn)`
503			`begin`
504			`$display("\n\n*************************************\n");`
505			`$display("WARNING: Recieved Interrupt (%0t)", $time);`
506			`$display("*************************************\n\n\n");`
507			`end`
508
509			`always #2.5 clk = ~clk;`
510			`always #(PCLK_C/2) pclk = ~pclk;`
511
512			`assign clk_v = clk;`
513
514			`/////////////////////////////////////////////////////////////////////`
515			`//`
516			`// WISHBONE DMA IP Core`
517			`//`
518
519
520			`// Module Prototype`
521
522			`ifdef USE_VC
523	26	rherveille	`vga_top #(1'b0, LINE_FIFO_AWIDTH) u0 (`
524	16	rudi	`.wb_clk_i( clk ),`
525	24	rherveille	`.wb_rst_i( 1'b0 ),`
526			`.rst_i( rst ),`
527	16	rudi	`.wb_inta_o( int ),`
528
529			`//-- slave signals`
530	24	rherveille	`.wbs_adr_i( wb_addr_i[11:0] ),`
531			`.wbs_dat_i( wb_data_i ),`
532			`.wbs_dat_o( wb_data_o ),`
533			`.wbs_sel_i( wb_sel_i ),`
534			`.wbs_we_i( wb_we_i ),`
535			`.wbs_stb_i( wb_stb_i ),`
536			`.wbs_cyc_i( wb_cyc_i ),`
537			`.wbs_ack_o( wb_ack_o ),`
538			`.wbs_err_o( wb_err_o ),`
539	16	rudi
540			`//-- master signals`
541	24	rherveille	`.wbm_adr_o( wb_addr_o[31:0] ),`
542			`.wbm_dat_i( wbm_data_i ),`
543			`.wbm_sel_o( wb_sel_o ),`
544			`.wbm_we_o( wb_we_o ),`
545			`.wbm_stb_o( wb_stb_o ),`
546			`.wbm_cyc_o( wb_cyc_o ),`
547			`.wbm_cab_o( ),`
548			`.wbm_ack_i( wb_ack_i ),`
549			`.wbm_err_i( wb_err_i ),`
550	16	rudi
551			`//-- VGA signals`
552	24	rherveille	`.clk_p_i( pclk ),`
553			`.hsync_pad_o( hsync ),`
554			`.vsync_pad_o( vsync ),`
555			`.csync_pad_o( csync ),`
556			`.blank_pad_o( blanc ),`
557			`.r_pad_o( red ),`
558			`.g_pad_o( green ),`
559			`.b_pad_o( blue )`
560	16	rudi	`);`
561
562			`else
563
564			`VGA u0 ( .CLK_I( clk_v ),`
565			`.RST_I( ~rst ),`
566			`.NRESET( rst ),`
567			`.INTA_O( int ),`
568
569			`//-- slave signals`
570			`.ADR_I( wb_addr_i[4:2] ),`
571			`.SDAT_I( wb_data_i ),`
572			`.SDAT_O( wb_data_o ),`
573			`.SEL_I( wb_sel_i ),`
574			`.WE_I( wb_we_i ),`
575			`.STB_I( wb_stb_i ),`
576			`.CYC_I( wb_cyc_i ),`
577			`.ACK_O( wb_ack_o ),`
578			`.ERR_O( wb_err_o ),`
579
580			`//-- master signals`
581			`.ADR_O( wb_addr_o[31:2] ),`
582			`.MDAT_I( wbm_data_i ),`
583			`.SEL_O( wb_sel_o ),`
584			`.WE_O( wb_we_o ),`
585			`.STB_O( wb_stb_o ),`
586			`.CYC_O( wb_cyc_o ),`
587			`.CAB_O( ),`
588			`.ACK_I( wb_ack_i ),`
589			`.ERR_I( wb_err_i ),`
590
591			`//-- VGA signals`
592			`.PCLK( pclk ),`
593			`.HSYNC( hsync ),`
594			`.VSYNC( vsync ),`
595			`.CSYNC( csync ),`
596			`.BLANK( blanc ),`
597			`.R( red ),`
598			`.G( green ),`
599			`.B( blue )`
600			`);`
601
602			`endif
603
604			`wb_mast m0( .clk( clk ),`
605			`.rst( rst ),`
606			`.adr( wb_addr_i ),`
607			`.din( wb_data_o ),`
608			`.dout( wb_data_i ),`
609			`.cyc( wb_cyc_i ),`
610			`.stb( wb_stb_i ),`
611			`.sel( wb_sel_i ),`
612			`.we( wb_we_i ),`
613			`.ack( wb_ack_o ),`
614			`.err( wb_err_o ),`
615			`.rty( 1'b0 )`
616			`);`
617
618			`wb_slv #(24) s0(.clk( clk ),`
619			`.rst( rst ),`
620			`.adr( {1'b0, wb_addr_o[30:0]} ),`
621			`.din( 32'h0 ),`
622			`.dout( wbm_data_i ),`
623			`.cyc( wb_cyc_o ),`
624			`.stb( wb_stb_o ),`
625			`.sel( wb_sel_o ),`
626			`.we( wb_we_o ),`
627			`.ack( wb_ack_i ),`
628			`.err( wb_err_i ),`
629			`.rty( )`
630			`);`
631
632			`include "tests.v"
633
634			`endmodule`
635
636			`/*`
637			`module vdata_mon(clk, rst, hsync, vsync, blank, pixel, line);`
638			`input clk, rst;`
639			`input hsync, vsync, blank;`
640			`output [31:0] pixel, line;`
641
642			`reg [31:0] pixel, line;`
643
644			`always @(negedge blank)`
645			`line = line + 1;`
646
647			`always @(posedge vsync or negedge rst)`
648			`line = -1;`
649
650			`always @(posedge clk)`
651			`if(!blank) pixel = pixel + 1;`
652			`else pixel = 0;`
653
654			`endmodule`
655			`*/`
656	24	rherveille
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710