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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Tests Library                                              ////
////                                                             ////
////                                                             ////
////  Authors: Rudolf Usselmann, Richard Herveille               ////
////           rudi@asics.ws,    richard@asics.ws                ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tests.v,v 1.5 2002-04-20 09:57:55 rherveille Exp $
//
//  $Date: 2002-04-20 09:57:55 $
//  $Revision: 1.5 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//                        
 
 
task show_errors;
 
begin
 
$display("\n");
$display("     +--------------------+");
$display("     |  Total ERRORS: %0d   |", error_cnt);
$display("     +--------------------+");
 
end
endtask
 
 
task reg_test;
 
reg     [31:0]   data;
reg     [31:0]   pattern;
integer         n;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Register Test                                 ***");
$display("*****************************************************\n");
 
        // Check reset Values
        $display("Testing Reset Values ...");
        check( `CTRL,  0, 32'h0000_ffff, "CTRL ");
        check( `STAT,  0, 32'h0000_0073, "STAT ");
        check( `HTIM,  0, 32'hffff_ffff, "HTIM ");
        check( `VTIM,  0, 32'hffff_ffff, "VTIM ");
        check( `HVLEN, 0, 32'hffff_ffff, "HVLEN");
        check( `VBARA, 0, 32'hffff_ffff, "VBARA");
        check( `VBARB, 0, 32'hffff_ffff, "VBARB");
 
        $display("Testing Pattern R/W ...");
for(n=0;n<6;n=n+1)
        begin
                case(n)
                  0: pattern = 32'h0000_0000;
                  1: pattern = 32'hffff_ffff;
                  2: pattern = 32'haaaa_aaaa;
                  3: pattern = 32'h5555_5555;
                  4: pattern = 32'hcccc_cccc;
                  5: pattern = 32'h3333_3333;
                endcase
 
                m0.wb_wr1( `CTRL, 4'hf, pattern );
                check( `CTRL,  pattern, 32'h0000_ffff, "CTRL ");
 
                m0.wb_wr1( `HTIM, 4'hf, pattern );
                check( `HTIM,  pattern, 32'hffff_ffff, "HTIM ");
 
                m0.wb_wr1( `VTIM, 4'hf, pattern );
                check( `VTIM,  pattern, 32'hffff_ffff, "VTIM ");
 
                m0.wb_wr1( `HVLEN, 4'hf, pattern );
                check( `HVLEN, pattern, 32'hffff_ffff, "HVLEN");
 
                m0.wb_wr1( `VBARA, 4'hf, pattern );
                check( `VBARA, pattern, 32'hffff_fffc, "VBARA");
 
                m0.wb_wr1( `VBARB, 4'hf, pattern );
                check( `VBARB, pattern, 32'hffff_fffc, "VBARB");
 
        end
 
repeat(10)      @(posedge clk);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task check;
input   [31:0]   addr;
input   [31:0]   edata;
input   [31:0]   mask;
input   [39:0]   name;
 
reg     [31:0]   data;
begin
 
m0.wb_rd1( addr, 4'hf, data );
if(( (data & mask) != (edata & mask)) | ((^data) === 1'bx) )
   begin
        $display("ERROR: %s Reg: Value Mismatch. Expected %h, Got %h (%0t)",
                name, edata & mask, data, $time);
        error_cnt = error_cnt + 1;
   end
 
end
endtask
 
 
 
 
task tim_test;
 
integer         mode;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Timing Test                                   ***");
$display("*****************************************************\n");
 
        s0.fill_mem(0);
 
        repeat(10)      @(posedge clk);
 
        m0.wb_wr1( `VBARA, 4'hf, 0 );
        m0.wb_wr1( `VBARB, 4'hf, 0 );
        m0.wb_wr1( `CTRL,  4'hf, 32'h0000_0000);
        repeat(10)      @(posedge clk);
mode = 4;
 
for(mode=0;mode<6;mode=mode+1)
   begin
        scen = 0;
        $display("Mode: %0d", mode);
 
        case(mode)
                0:
                begin
                        thsync = 0;
                        thgdel = 0;
                        thgate = 340;
                        thlen = 345;
 
                        tvsync = 0;
                        tvgdel = 0;
                        tvgate = 240;
                        tvlen = 245;
 
                        hpol = 0;
                        vpol = 0;
                        cpol = 0;
                        bpol = 0;
                end
 
                1:
                begin
                        thsync = 18;
                        thgdel = 18;
                        thgate = 340;
                        thlen = 390;
 
                        tvsync = 18;
                        tvgdel = 18;
                        tvgate = 240;
                        tvlen = 290;
 
                        hpol = 1;
                        vpol = 0;
                        cpol = 0;
                        bpol = 0;
                end
 
                2:
                begin
                        thsync = 1;
                        thgdel = 1;
                        thgate = 640;
                        thlen = 643;
 
                        tvsync = 1;
                        tvgdel = 1;
                        tvgate = 480;
                        tvlen = 483;
 
                        hpol = 0;
                        vpol = 1;
                        cpol = 0;
                        bpol = 0;
                end
 
                3:
                begin
                        thsync = 0;
                        thgdel = 2;
                        thgate = 800;
                        thlen = 804;
 
                        tvsync = 0;
                        tvgdel = 2;
                        tvgate = 600;
                        tvlen = 604;
 
                        hpol = 0;
                        vpol = 0;
                        cpol = 1;
                        bpol = 0;
                end
 
                4:
                begin
                        thsync = 3;
                        thgdel = 2;
                        thgate = 800;
                        thlen = 806;
 
                        tvsync = 2;
                        tvgdel = 2;
                        tvgate = 600;
                        tvlen = 606;
 
                        hpol = 0;
                        vpol = 0;
                        cpol = 0;
                        bpol = 1;
                end
 
                5:
                begin
                        thsync = 6;
                        thgdel = 2;
                        thgate = 800;
                        thlen = 810;
 
                        tvsync = 4;
                        tvgdel = 2;
                        tvgate = 600;
                        tvlen = 607;
 
                        hpol = 1;
                        vpol = 1;
                        cpol = 1;
                        bpol = 1;
                end
        endcase
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 64;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 64;
        tvlen = 70;
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
*/
 
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,
                                bpol, cpol,
                                vpol, hpol,
                                1'b0,   // PC
                                2'h0,   // CD
                                2'h0,   // VBL
                                2'h0,   // Reserved
                                5'h01   // Bank Switch, INT, VideoEn
                                });
 
        repeat(2) @(posedge vsync);
        scen = 1;
        repeat(4) @(posedge vsync);
   end
 
scen = 0;
repeat(10)      @(posedge clk);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
 
task pd1_test;
 
integer         mode;
integer         n, p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   data;
reg [31:0] cbar;
reg     [7:0]    vbl;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Pixel Data Test 1                             ***");
$display("*****************************************************\n");
 
        m0.wb_wr1( `VBARA, 4'hf, 0 );
        m0.wb_wr1( `VBARB, 4'hf, 123456 );
 
        cbar = 32'h0000_0800;
 
        thsync = 0;
        thgdel = 0;
        thgate = 320;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
        thsync = 39;
        thgdel = 124;
        thgate = 646;
        thlen = 832;
 
        tvsync = 2;
        tvgdel = 25;
        tvgate = 484;
        tvlen = 520;
 
        thsync = 6;
        thgdel = 20;
        thgate = 319;
        thlen = 390;
 
        tvsync = 1;
        tvgdel = 8;
        tvgate = 239;
        tvlen = 280;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
 
        thsync = 119;
        thgdel = 61;
        thgate = 805;
        thlen  = 1038;
 
        tvsync = 5;
        tvgdel = 20;
        tvgate = 600;
        tvlen  = 665;
 
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
mode = 2;
vbl = 0;
 
for(vbl=0;vbl<4;vbl=vbl+1)
for(mode=0;mode<4;mode=mode+1)
   begin
 
        // -------------------------------
        // Turn Off VGA before Mode Change
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'h0,   // VBL
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0, // CBSIE
                                1'b0,   // VBSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b0    // Video Enable
                                });
 
        s0.fill_mem(1);
 
`ifdef USE_VC
// Fill internal Color Lookup Table
repeat(10)      @(posedge clk);
for(n=0;n<512;n=n+1)
   begin
        //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
        data = s0.mem[ cbar[31:2] + n];
        m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
   end
repeat(10)      @(posedge clk);
`endif
 
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        //repeat(50) @(posedge clk);
 
        // -------------------------------
        // Turn VGA back On ...
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                vbl[1:0],        // VBL
                                1'b0,   // Reserved
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        $display("VBL: %0d, Mode: %0d", vbl, mode);
        repeat(2) @(posedge vsync);
 
        // For Each Line
        for(l=0;l<tvgate;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                   0:    // 24 bit/pixel mode
                   begin
                        pra = pn[31:2] * 3;     // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
 
                        // Pixel Data
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = tmp[31:8];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd[23:16] = tmp[7:0];
                                tmp = s0.mem[paa+1];
                                pd[15:0] = tmp[31:16];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa+1];
                                pd[23:8] = tmp[15:0];
                                tmp = s0.mem[paa+2];
                                pd[7:0] = tmp[31:24];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa+2];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   1:   // 8 bit/pixel grayscale mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                             end
                        endcase
                   end
 
                   2:   // 8 bit/pixel Pseudo Color mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[31:24]];
                                pd = tmp[23:0];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[23:16]];
                                pd = tmp[23:0];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[15:8]];
                                pd = tmp[23:0];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[7:0]];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   3:   // 16 bit/pixel mode
                   begin
                        pra = pn[31:1];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp[15:0] = tmp[31:16];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                        endcase
                   end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                   end
 
                @(posedge pclk);
 
           end
   end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task pd2_test;
 
integer         mode;
integer         p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   cbar;
reg     [31:0]   vbase;
reg     [31:0]   cbase;
reg     [31:0]   vbara;
reg     [31:0]   vbarb;
reg     [7:0]    bank, vbl;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Pixel Data Test 2                             ***");
$display("*****************************************************\n");
 
        s0.fill_mem(1);
 
        repeat(10)      @(posedge clk);
 
        vbara = 32'h0000_0000;
        vbarb = 32'h0040_0000;
        cbar  = 32'h0000_0800;
 
        m0.wb_wr1( `VBARA, 4'hf, vbara );
        m0.wb_wr1( `VBARB, 4'hf, vbarb );
 
        thsync = 6;
        thgdel = 20;
        thgate = 319;
        thlen = 390;
 
        tvsync = 1;
        tvgdel = 8;
//      tvgate = 239;
        tvgate = 240;
        tvlen = 280;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
 
*/
 
/*
        thsync = 39;
        thgdel = 124;
        thgate = 645;
        thlen = 832;
 
        tvsync = 2;
        tvgdel = 25;
        tvgate = 483;
        tvlen = 520;
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
 
`ifdef USE_VC
// Fill internal Color Lookup Table
repeat(10)      @(posedge clk);
for(n=0;n<512;n=n+1)
   begin
        //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
        data = s0.mem[ cbar[31:2] + n];
        m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
   end
repeat(10)      @(posedge clk);
`endif
 
 
vbl = 0;
mode = 1;
 
for(vbl=0;vbl<4;vbl=vbl+1)
for(mode=0;mode<=4;mode=mode+1)
   begin
 
        m0.wb_wr1( `CTRL,  4'hf, 32'h0);
        repeat(100) @(posedge clk);
 
                case(mode)
                0:
                begin
                        cd = 2'h2;
                        pc = 1'b0;
                end
 
                1:
                begin
                        cd = 2'h0;
                        pc = 1'b0;
                end
 
                2:
                begin
                        cd = 2'h0;
                        pc = 1'b1;
                end
 
                3:
                begin
                        cd = 2'h1;
                        pc = 1'b0;
                end
 
                4:
                begin
                        cd = 2'h3;
                        pc = 1'b0;
                end
        endcase
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                vbl[1:0],// VBL
                                1'b1,   // CBSWE
                                1'b1,   // VBSWE
                                1'b0, // CBSIE
                                1'b0,   // VBSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                }
        );
 
bank = 0;
 
//for(bank=0;bank<3;bank=bank+1)
for(bank=0;bank<2;bank=bank+1)
   begin
 
        $display("VBL: %0d, Mode: %0d Screen: %0d", vbl, mode, bank);
        @(posedge vsync);
 
        error_cnt=0;
        // For Each Line
//      for(l=0;l<tvgate+1;l=l+1)
        for(l=0; l<tvgate;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                if(bank[0])      vbase = vbarb[31:2];
                else            vbase = vbara[31:2];
                if(bank[0])      cbase = cbar | 32'h0000_0400;
                else            cbase = cbar;
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                        0:       // 24 bit/pixel mode
                        begin
                                pra = pn[31:2] * 3;     // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                // Pixel Data
                                case(pn[1:0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = tmp[31:8];
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd[23:16] = tmp[7:0];
                                                tmp = s0.mem[paa+1];
                                                pd[15:0] = tmp[31:16];
                                        end
 
                                        2:
                                        begin
                                                tmp = s0.mem[paa+1];
                                                pd[23:8] = tmp[15:0];
                                                tmp = s0.mem[paa+2];
                                                pd[7:0] = tmp[31:24];
                                        end
 
                                        3:
                                        begin
                                                tmp = s0.mem[paa+2];
                                                pd = tmp[23:0];
                                        end
                                endcase
                        end
 
                        1:      // 8 bit/pixel grayscale mode
                        begin
                                pra = pn[31:2];         // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                case(pn[1:0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                                        end
 
                                        2:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                                        end
 
                                        3:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                                        end
                                endcase
                        end
 
                        2:      // 8 bit/pixel Pseudo Color mode
                        begin
                                pra = pn[31:2];         // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                case(pn[1:0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[31:24]];
                                                pd = tmp[23:0];
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[23:16]];
                                                pd = tmp[23:0];
                                        end
 
                                        2:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[15:8]];
                                                pd = tmp[23:0];
                                        end
 
                                        3:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[7:0]];
                                                pd = tmp[23:0];
                                        end
                                endcase
                        end
 
                        3:      // 16 bit/pixel mode
                        begin
                                pra = pn[31:1];         // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                case(pn[0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp[15:0] = tmp[31:16];
                                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                                        end
                                endcase
                        end
 
                        4:      // 32 bit/pixel mode
                        begin
                                pra = pn[31:0];          // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                tmp = s0.mem[paa];
                                pd = tmp[23:0];
                        end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                        if(error_cnt > 10)      $stop;
                   end
 
                @(posedge pclk);
 
           end
   end
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task ur_test;
 
integer         mode;
integer         n, p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   cbar;
reg     [31:0]   data;
reg     [7:0]    vbl;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** FIFO Underrun Test 1                          ***");
$display("*****************************************************\n");
 
        s0.delay=5;
        int_warn = 0;
 
        m0.wb_wr1( `VBARA, 4'hf, 0 );
        m0.wb_wr1( `VBARB, 4'hf, 123456 );
 
        cbar = 32'h0000_0800;
 
        thsync = 0;
        thgdel = 0;
        thgate = 340;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
        thsync = 39;
        thgdel = 124;
        thgate = 646;
        thlen = 832;
 
        tvsync = 2;
        tvgdel = 25;
        tvgate = 484;
        tvlen = 520;
 
        thsync = 6;
        thgdel = 20;
        thgate = 319;
        thlen = 390;
 
        tvsync = 1;
        tvgdel = 8;
        tvgate = 239;
        tvlen = 280;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
 
        thsync = 119;
        thgdel = 61;
        thgate = 805;
        thlen  = 1038;
 
        tvsync = 5;
        tvgdel = 20;
        tvgate = 600;
        tvlen  = 665;
 
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
        mode = 2;
 
        // -------------------------------
        // Turn Off VGA before Mode Change
 
        m0.wb_wr1( `CTRL,  4'hf, 32'h0000_0000);
 
        s0.fill_mem(1);
 
`ifdef USE_VC
// Fill internal Color Lookup Table
repeat(10)      @(posedge clk);
for(n=0;n<512;n=n+1)
   begin
        //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
        data = s0.mem[ cbar[31:2] + n];
        m0.wb_wr1( 32'h8000_0000 + (n*4), 4'hf, data );
   end
repeat(10)      @(posedge clk);
`endif
 
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        // -------------------------------
        // Turn VGA back On ...
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'b00,  // VBL
                                1'b0,   // Reserved
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        while(!int)     @(posedge clk);
        m0.wb_rd1( `STAT,  4'hf, data);
        if(data[1] !== 1'b1)
           begin
                $display("ERROR: Did not get Line FIFO Interrupt. (%0t)",
                        $time);
           end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
m0.wb_wr1( `CTRL,  4'hf, 32'h0000_0000);
int_warn = 1;
s0.delay=1;
repeat(10) @(posedge clk);
 
end
endtask
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tests Library ////`
4			`//// ////`
5			`//// ////`
6	29	rherveille	`//// Authors: Rudolf Usselmann, Richard Herveille ////`
7			`//// rudi@asics.ws, richard@asics.ws ////`
8	16	rudi	`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	38	rherveille	`// $Id: tests.v,v 1.5 2002-04-20 09:57:55 rherveille Exp $`
41	16	rudi	`//`
42	38	rherveille	`// $Date: 2002-04-20 09:57:55 $`
43			`// $Revision: 1.5 $`
44	24	rherveille	`// $Author: rherveille $`
45	16	rudi	`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53			`//`
54
55
56			`task show_errors;`
57
58			`begin`
59
60			`$display("\n");`
61			`$display(" +--------------------+");`
62			`$display(" \| Total ERRORS: %0d \|", error_cnt);`
63			`$display(" +--------------------+");`
64
65			`end`
66			`endtask`
67
68
69			`task reg_test;`
70
71			`reg [31:0] data;`
72			`reg [31:0] pattern;`
73			`integer n;`
74
75			`begin`
76			`$display("\n\n");`
77			`$display("*****************************************************");`
78			`$display("* Register Test *");`
79			`$display("*****************************************************\n");`
80
81			`// Check reset Values`
82			`$display("Testing Reset Values ...");`
83			check( `CTRL, 0, 32'h0000_ffff, "CTRL ");
84			check( `STAT, 0, 32'h0000_0073, "STAT ");
85			check( `HTIM, 0, 32'hffff_ffff, "HTIM ");
86			check( `VTIM, 0, 32'hffff_ffff, "VTIM ");
87			check( `HVLEN, 0, 32'hffff_ffff, "HVLEN");
88			check( `VBARA, 0, 32'hffff_ffff, "VBARA");
89			check( `VBARB, 0, 32'hffff_ffff, "VBARB");
90
91			`$display("Testing Pattern R/W ...");`
92			`for(n=0;n<6;n=n+1)`
93	24	rherveille	`begin`
94			`case(n)`
95			`0: pattern = 32'h0000_0000;`
96			`1: pattern = 32'hffff_ffff;`
97			`2: pattern = 32'haaaa_aaaa;`
98			`3: pattern = 32'h5555_5555;`
99			`4: pattern = 32'hcccc_cccc;`
100			`5: pattern = 32'h3333_3333;`
101			`endcase`
102	16	rudi
103	24	rherveille	m0.wb_wr1( `CTRL, 4'hf, pattern );
104			check( `CTRL, pattern, 32'h0000_ffff, "CTRL ");
105	16	rudi
106	24	rherveille	m0.wb_wr1( `HTIM, 4'hf, pattern );
107			check( `HTIM, pattern, 32'hffff_ffff, "HTIM ");
108	16	rudi
109	24	rherveille	m0.wb_wr1( `VTIM, 4'hf, pattern );
110			check( `VTIM, pattern, 32'hffff_ffff, "VTIM ");
111	16	rudi
112	24	rherveille	m0.wb_wr1( `HVLEN, 4'hf, pattern );
113			check( `HVLEN, pattern, 32'hffff_ffff, "HVLEN");
114	16	rudi
115	24	rherveille	m0.wb_wr1( `VBARA, 4'hf, pattern );
116			check( `VBARA, pattern, 32'hffff_fffc, "VBARA");
117	16	rudi
118	24	rherveille	m0.wb_wr1( `VBARB, 4'hf, pattern );
119			check( `VBARB, pattern, 32'hffff_fffc, "VBARB");
120	16	rudi
121	24	rherveille	`end`
122	16	rudi
123			`repeat(10) @(posedge clk);`
124
125			`show_errors;`
126			`$display("*****************************************************");`
127			`$display("* Test DONE ... *");`
128			`$display("*****************************************************\n\n");`
129
130			`end`
131			`endtask`
132
133
134
135			`task check;`
136			`input [31:0] addr;`
137			`input [31:0] edata;`
138			`input [31:0] mask;`
139			`input [39:0] name;`
140
141			`reg [31:0] data;`
142			`begin`
143
144			`m0.wb_rd1( addr, 4'hf, data );`
145			`if(( (data & mask) != (edata & mask)) \| ((^data) === 1'bx) )`
146			`begin`
147			`$display("ERROR: %s Reg: Value Mismatch. Expected %h, Got %h (%0t)",`
148			`name, edata & mask, data, $time);`
149			`error_cnt = error_cnt + 1;`
150			`end`
151
152			`end`
153			`endtask`
154
155
156
157
158			`task tim_test;`
159
160			`integer mode;`
161
162			`begin`
163			`$display("\n\n");`
164			`$display("*****************************************************");`
165			`$display("* Timing Test *");`
166			`$display("*****************************************************\n");`
167
168			`s0.fill_mem(0);`
169
170			`repeat(10) @(posedge clk);`
171
172			m0.wb_wr1( `VBARA, 4'hf, 0 );
173			m0.wb_wr1( `VBARB, 4'hf, 0 );
174			m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000);
175			`repeat(10) @(posedge clk);`
176			`mode = 4;`
177
178			`for(mode=0;mode<6;mode=mode+1)`
179			`begin`
180			`scen = 0;`
181			`$display("Mode: %0d", mode);`
182
183			`case(mode)`
184	38	rherveille	`0:`
185			`begin`
186			`thsync = 0;`
187			`thgdel = 0;`
188			`thgate = 340;`
189			`thlen = 345;`
190	16	rudi
191	38	rherveille	`tvsync = 0;`
192			`tvgdel = 0;`
193			`tvgate = 240;`
194			`tvlen = 245;`
195	16	rudi
196	38	rherveille	`hpol = 0;`
197			`vpol = 0;`
198			`cpol = 0;`
199			`bpol = 0;`
200			`end`
201	16	rudi
202	38	rherveille	`1:`
203			`begin`
204			`thsync = 18;`
205			`thgdel = 18;`
206			`thgate = 340;`
207			`thlen = 390;`
208	16	rudi
209	38	rherveille	`tvsync = 18;`
210			`tvgdel = 18;`
211			`tvgate = 240;`
212			`tvlen = 290;`
213	16	rudi
214	38	rherveille	`hpol = 1;`
215			`vpol = 0;`
216			`cpol = 0;`
217			`bpol = 0;`
218			`end`
219	16	rudi
220	38	rherveille	`2:`
221			`begin`
222			`thsync = 1;`
223			`thgdel = 1;`
224			`thgate = 640;`
225			`thlen = 643;`
226	16	rudi
227	38	rherveille	`tvsync = 1;`
228			`tvgdel = 1;`
229			`tvgate = 480;`
230			`tvlen = 483;`
231	16	rudi
232	38	rherveille	`hpol = 0;`
233			`vpol = 1;`
234			`cpol = 0;`
235			`bpol = 0;`
236			`end`
237	16	rudi
238	38	rherveille	`3:`
239			`begin`
240			`thsync = 0;`
241			`thgdel = 2;`
242			`thgate = 800;`
243			`thlen = 804;`
244	16	rudi
245	38	rherveille	`tvsync = 0;`
246			`tvgdel = 2;`
247			`tvgate = 600;`
248			`tvlen = 604;`
249	16	rudi
250	38	rherveille	`hpol = 0;`
251			`vpol = 0;`
252			`cpol = 1;`
253			`bpol = 0;`
254			`end`
255	16	rudi
256	38	rherveille	`4:`
257			`begin`
258			`thsync = 3;`
259			`thgdel = 2;`
260			`thgate = 800;`
261			`thlen = 806;`
262	16	rudi
263	38	rherveille	`tvsync = 2;`
264			`tvgdel = 2;`
265			`tvgate = 600;`
266			`tvlen = 606;`
267	16	rudi
268	38	rherveille	`hpol = 0;`
269			`vpol = 0;`
270			`cpol = 0;`
271			`bpol = 1;`
272			`end`
273	16	rudi
274	38	rherveille	`5:`
275			`begin`
276			`thsync = 6;`
277			`thgdel = 2;`
278			`thgate = 800;`
279			`thlen = 810;`
280	16	rudi
281	38	rherveille	`tvsync = 4;`
282			`tvgdel = 2;`
283			`tvgate = 600;`
284			`tvlen = 607;`
285	16	rudi
286	38	rherveille	`hpol = 1;`
287			`vpol = 1;`
288			`cpol = 1;`
289			`bpol = 1;`
290			`end`
291	16	rudi	`endcase`
292
293			`/*`
294			`thsync = 0;`
295			`thgdel = 0;`
296			`thgate = 64;`
297			`thlen = 70;`
298
299			`tvsync = 0;`
300			`tvgdel = 0;`
301			`tvgate = 64;`
302			`tvlen = 70;`
303
304			`hpol = 0;`
305			`vpol = 0;`
306			`cpol = 0;`
307			`bpol = 0;`
308			`*/`
309
310
311			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
312			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
313			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
314			m0.wb_wr1( `CTRL, 4'hf, {
315			`16'h0,`
316			`bpol, cpol,`
317			`vpol, hpol,`
318			`1'b0, // PC`
319			`2'h0, // CD`
320			`2'h0, // VBL`
321			`2'h0, // Reserved`
322			`5'h01 // Bank Switch, INT, VideoEn`
323			`});`
324
325			`repeat(2) @(posedge vsync);`
326			`scen = 1;`
327			`repeat(4) @(posedge vsync);`
328			`end`
329
330			`scen = 0;`
331			`repeat(10) @(posedge clk);`
332
333			`show_errors;`
334			`$display("*****************************************************");`
335			`$display("* Test DONE ... *");`
336			`$display("*****************************************************\n\n");`
337
338			`end`
339			`endtask`
340
341
342
343
344			`task pd1_test;`
345
346			`integer mode;`
347			`integer n, p, l;`
348			`reg [31:0] pn;`
349			`reg [31:0] pra, paa, tmp;`
350			`reg [23:0] pd;`
351			`reg [1:0] cd;`
352			`reg pc;`
353			`reg [31:0] data;`
354	24	rherveille	`reg [31:0] cbar;`
355	16	rudi	`reg [7:0] vbl;`
356
357			`begin`
358
359			`$display("\n\n");`
360			`$display("*****************************************************");`
361			`$display("* Pixel Data Test 1 *");`
362			`$display("*****************************************************\n");`
363
364			m0.wb_wr1( `VBARA, 4'hf, 0 );
365			m0.wb_wr1( `VBARB, 4'hf, 123456 );
366
367	24	rherveille	`cbar = 32'h0000_0800;`
368	16	rudi
369			`thsync = 0;`
370			`thgdel = 0;`
371	24	rherveille	`thgate = 320;`
372	16	rudi	`thlen = 345;`
373
374			`tvsync = 0;`
375			`tvgdel = 0;`
376			`tvgate = 240;`
377			`tvlen = 245;`
378
379			`thsync = 39;`
380			`thgdel = 124;`
381			`thgate = 646;`
382			`thlen = 832;`
383
384			`tvsync = 2;`
385			`tvgdel = 25;`
386			`tvgate = 484;`
387			`tvlen = 520;`
388
389			`thsync = 6;`
390			`thgdel = 20;`
391			`thgate = 319;`
392			`thlen = 390;`
393
394			`tvsync = 1;`
395			`tvgdel = 8;`
396			`tvgate = 239;`
397			`tvlen = 280;`
398
399			`/*`
400			`thsync = 0;`
401			`thgdel = 0;`
402			`thgate = 63;`
403			`thlen = 70;`
404
405			`tvsync = 0;`
406			`tvgdel = 0;`
407			`tvgate = 32;`
408			`tvlen = 36;`
409
410			`thsync = 119;`
411			`thgdel = 61;`
412			`thgate = 805;`
413			`thlen = 1038;`
414
415			`tvsync = 5;`
416			`tvgdel = 20;`
417			`tvgate = 600;`
418			`tvlen = 665;`
419
420			`*/`
421
422			`hpol = 0;`
423			`vpol = 0;`
424			`cpol = 0;`
425			`bpol = 0;`
426
427			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
428			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
429			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
430
431	24	rherveille	`mode = 2;`
432			`vbl = 0;`
433	16	rudi
434			`for(vbl=0;vbl<4;vbl=vbl+1)`
435			`for(mode=0;mode<4;mode=mode+1)`
436			`begin`
437
438			`// -------------------------------`
439			`// Turn Off VGA before Mode Change`
440
441			m0.wb_wr1( `CTRL, 4'hf, {
442			`16'h0, // Reserved`
443			`bpol, cpol,`
444			`vpol, hpol,`
445			`pc, // 1'b0, // PC`
446			`cd, // 2'h2, // CD`
447			`2'h0, // VBL`
448			`1'b0, // CBSWE`
449			`1'b0, // VBSWE`
450	24	rherveille	`1'b0, // CBSIE`
451			`1'b0, // VBSIE`
452	16	rudi	`1'b0, // HIE`
453			`1'b0, // VIE`
454			`1'b0 // Video Enable`
455			`});`
456
457			`s0.fill_mem(1);`
458
459			`ifdef USE_VC
460			`// Fill internal Color Lookup Table`
461			`repeat(10) @(posedge clk);`
462			`for(n=0;n<512;n=n+1)`
463			`begin`
464			`//m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );`
465			`data = s0.mem[ cbar[31:2] + n];`
466	24	rherveille	`m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );`
467	16	rudi	`end`
468			`repeat(10) @(posedge clk);`
469			`endif
470
471			`case(mode)`
472			`0:`
473			`begin`
474			`cd = 2'h2;`
475			`pc = 1'b0;`
476			`end`
477			`1:`
478			`begin`
479			`cd = 2'h0;`
480			`pc = 1'b0;`
481			`end`
482			`2:`
483			`begin`
484			`cd = 2'h0;`
485			`pc = 1'b1;`
486			`end`
487			`3:`
488			`begin`
489			`cd = 2'h1;`
490			`pc = 1'b0;`
491			`end`
492			`endcase`
493
494			`//repeat(50) @(posedge clk);`
495
496			`// -------------------------------`
497			`// Turn VGA back On ...`
498			m0.wb_wr1( `CTRL, 4'hf, {
499			`16'h0, // Reserved`
500			`bpol, cpol,`

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