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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Tests Library                                              ////
////                                                             ////
////                                                             ////
////  Authors: Rudolf Usselmann, Richard Herveille               ////
////           rudi@asics.ws,    richard@asics.ws                ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tests.v,v 1.10 2003-09-23 13:09:25 markom Exp $
//
//  $Date: 2003-09-23 13:09:25 $
//  $Revision: 1.10 $
//  $Author: markom $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.9  2003/08/22 07:17:21  rherveille
//               Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.
//
//               Revision 1.8  2003/05/07 14:39:19  rherveille
//               Added DVI tests
//
//               Revision 1.7  2003/05/07 09:45:28  rherveille
//               Numerous updates and added checks
//
//               Revision 1.6  2003/03/19 12:20:53  rherveille
//               Changed timing section in VGA core, changed testbench accordingly.
//               Fixed bug in 'timing check' test.
//
//               Revision 1.5  2002/04/20 09:57:55  rherveille
//               Changed testbench to reflect modified VGA timing generator.
//
//
//
//
//
 
 
task show_errors;
 
begin
 
$display("\n");
$display("     +--------------------+");
$display("     |  Total ERRORS: %0d   |", error_cnt);
$display("     +--------------------+");
 
end
endtask
 
 
task reg_test;
 
reg     [31:0]   data;
reg     [31:0]   pattern;
integer         n;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Register Test                                 ***");
$display("*****************************************************\n");
 
        // Check reset Values
        $display("Testing Reset Values ...");
        check( `CTRL,  0, 32'h0000_ffff, "CTRL ");
        check( `STAT,  0, 32'h0000_0073, "STAT ");
        check( `HTIM,  0, 32'hffff_ffff, "HTIM ");
        check( `VTIM,  0, 32'hffff_ffff, "VTIM ");
        check( `HVLEN, 0, 32'hffff_ffff, "HVLEN");
        check( `VBARA, 0, 32'hffff_ffff, "VBARA");
        check( `VBARB, 0, 32'hffff_ffff, "VBARB");
 
        $display("Testing Pattern R/W ...");
for(n=0;n<6;n=n+1)
        begin
                case(n)
                  0: pattern = 32'h0000_0000;
                  1: pattern = 32'hffff_ffff;
                  2: pattern = 32'haaaa_aaaa;
                  3: pattern = 32'h5555_5555;
                  4: pattern = 32'hcccc_cccc;
                  5: pattern = 32'h3333_3333;
                endcase
 
                m0.wb_wr1( `CTRL, 4'hf, pattern );
                check( `CTRL,  pattern, 32'hffff_ff9f, "CTRL ");
 
                m0.wb_wr1( `HTIM, 4'hf, pattern );
                check( `HTIM,  pattern, 32'hffff_ffff, "HTIM ");
 
                m0.wb_wr1( `VTIM, 4'hf, pattern );
                check( `VTIM,  pattern, 32'hffff_ffff, "VTIM ");
 
                m0.wb_wr1( `HVLEN, 4'hf, pattern );
                check( `HVLEN, pattern, 32'hffff_ffff, "HVLEN");
 
                m0.wb_wr1( `VBARA, 4'hf, pattern );
                check( `VBARA, pattern, 32'hffff_fffc, "VBARA");
 
                m0.wb_wr1( `VBARB, 4'hf, pattern );
                check( `VBARB, pattern, 32'hffff_fffc, "VBARB");
 
        end
 
repeat(10)      @(posedge clk);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task check;
input   [31:0]   addr;
input   [31:0]   edata;
input   [31:0]   mask;
input   [39:0]   name;
 
reg     [31:0]   data;
begin
 
m0.wb_rd1( addr, 4'hf, data );
if(( (data & mask) != (edata & mask)) | ((^data) === 1'bx) )
   begin
        $display("ERROR: %s Reg: Value Mismatch. Expected %h, Got %h (%0t)",
                name, edata & mask, data, $time);
        error_cnt = error_cnt + 1;
   end
 
end
endtask
 
 
 
 
task tim_test;
 
integer         mode;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Timing Test                                   ***");
$display("*****************************************************\n");
 
        s0.fill_mem(0);
 
        repeat(10)      @(posedge clk);
 
        m0.wb_wr1( `VBARA, 4'hf, 0 );
        m0.wb_wr1( `VBARB, 4'hf, 0 );
 
mode = 2;
for(mode=0;mode<6;mode=mode+1)
   begin
 
        // reset core
        scen = 0;
        m0.wb_wr1( `CTRL,  4'hf, 32'h0000_0000);
        repeat(10)      @(posedge clk);
 
        $display("Mode: %0d", mode);
 
        case(mode)
                0:
                begin
                        thsync = 0;
                        thgdel = 0;
                        thgate = 319; // gate = 320
                        thlen = 345;
 
                        tvsync = 0;
                        tvgdel = 0;
                        tvgate = 239; // vgate = 240
                        tvlen = 245;
 
                        hpol = 0;
                        vpol = 0;
                        cpol = 0;
                        bpol = 0;
                end
 
                1:
                begin
                        thsync = 18;
                        thgdel = 18;
                        thgate = 319; // gate = 320
                        thlen = 390;
 
                        tvsync = 18;
                        tvgdel = 18;
                        tvgate = 239; // vgate = 240
                        tvlen = 290;
 
                        hpol = 1;
                        vpol = 0;
                        cpol = 0;
                        bpol = 0;
                end
 
                2:
                begin
                        thsync = 1;
                        thgdel = 1;
                        thgate = 639; // hgate = 640
                        thlen = 644;
 
                        tvsync = 1;
                        tvgdel = 1;
                        tvgate = 479; // vgate = 480
                        tvlen = 484;
 
                        hpol = 0;
                        vpol = 1;
                        cpol = 0;
                        bpol = 0;
                end
 
                3:
                begin
                        thsync = 0;
                        thgdel = 2;
                        thgate = 799; // hgate = 800
                        thlen = 804;
 
                        tvsync = 0;
                        tvgdel = 2;
                        tvgate = 599; // vgate = 600
                        tvlen = 604;
 
                        hpol = 0;
                        vpol = 0;
                        cpol = 1;
                        bpol = 0;
                end
 
                4:
                begin
                        thsync = 3;
                        thgdel = 2;
                        thgate = 799; // hgate = 800
                        thlen = 807;
 
                        tvsync = 2;
                        tvgdel = 2;
                        tvgate = 599; // vgate = 600
                        tvlen = 606;
 
                        hpol = 0;
                        vpol = 0;
                        cpol = 0;
                        bpol = 1;
                end
 
                5:
                begin
                        thsync = 6;
                        thgdel = 2;
                        thgate = 799; // hgate = 800
                        thlen = 810;
 
                        tvsync = 4;
                        tvgdel = 2;
                        tvgate = 599; // vgate = 600
                        tvlen = 608;
 
                        hpol = 1;
                        vpol = 1;
                        cpol = 1;
                        bpol = 1;
                end
        endcase
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 64;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 64;
        tvlen = 70;
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
*/
 
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,
                                bpol, cpol,
                                vpol, hpol,
                                1'b0,   // PC
                                2'h0,   // CD
                                2'h0,   // VBL
                                2'h0,   // Reserved
                                5'h01   // Bank Switch, INT, VideoEn
                                });
 
        repeat(2) @(posedge vsync);
        scen = 1;
        repeat(4) @(posedge vsync);
   end
 
scen = 0;
repeat(10)      @(posedge clk);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
 
task pd1_test;
 
integer         mode;
integer         n, p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [ 1:0]   cd;
reg             pc;
reg     [31:0]   data;
reg     [31:0]   cbar;
reg     [ 7:0]   vbl;
reg     [ 5:0]   delay;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Pixel Data Test 1                             ***");
$display("*****************************************************\n");
 
        m0.wb_wr1( `VBARA, 4'hf, 0 );
        m0.wb_wr1( `VBARB, 4'hf, 123456 );
 
        cbar = 32'h0000_0800;
 
        thsync = 0;
        thgdel = 0;
        thgate = 320;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
        thsync = 39;
        thgdel = 124;
        thgate = 646;
        thlen = 832;
 
        tvsync = 2;
        tvgdel = 25;
        tvgate = 484;
        tvlen = 520;
 
        thsync = 6;
        thgdel = 20;
        thgate = 319;
        thlen = 390;
 
        tvsync = 1;
        tvgdel = 8;
        tvgate = 239;
        tvlen = 280;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
 
        thsync = 119;
        thgdel = 61;
        thgate = 805;
        thlen  = 1038;
 
        tvsync = 5;
        tvgdel = 20;
        tvgate = 600;
        tvlen  = 665;
 
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
mode  = 3;
vbl   = 1;
delay = 1;
 
for(delay=0;delay<6;delay=delay+1)
   begin
        s0.set_delay(delay);
for(vbl=0;vbl<4;vbl=vbl+1)
for(mode=0;mode<4;mode=mode+1)
   begin
        // -------------------------------
        // Turn Off VGA before Mode Change
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'h0,   // VBL
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0, // CBSIE
                                1'b0,   // VBSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b0    // Video Enable
                                });
 
        s0.fill_mem(1);
 
        `ifdef USE_VC
        // Fill internal Color Lookup Table
        repeat(10)      @(posedge clk);
        for(n=0;n<512;n=n+1)
           begin
               //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
               data = s0.mem[ cbar[31:2] + n];
               m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
           end
        repeat(10)      @(posedge clk);
        `endif
 
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        //repeat(50) @(posedge clk);
 
        // -------------------------------
        // Turn VGA back On ...
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                vbl[1:0],        // VBL
                                1'b0,   // Reserved
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        $display("VBL: %0d, Mode: %0d", vbl, mode);
        repeat(2) @(posedge vsync);
 
        // For Each Line
        for(l=0;l<tvgate;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                   0:    // 24 bit/pixel mode
                   begin
                        pra = pn[31:2] * 3;     // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
 
                        // Pixel Data
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = tmp[31:8];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd[23:16] = tmp[7:0];
                                tmp = s0.mem[paa+1];
                                pd[15:0] = tmp[31:16];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa+1];
                                pd[23:8] = tmp[15:0];
                                tmp = s0.mem[paa+2];
                                pd[7:0] = tmp[31:24];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa+2];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   1:   // 8 bit/pixel grayscale mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                             end
                        endcase
                   end
 
                   2:   // 8 bit/pixel Pseudo Color mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[31:24]];
                                pd = tmp[23:0];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[23:16]];
                                pd = tmp[23:0];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[15:8]];
                                pd = tmp[23:0];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[7:0]];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   3:   // 16 bit/pixel mode
                   begin
                        pra = pn[31:1];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp[15:0] = tmp[31:16];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                        endcase
                   end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                        if(error_cnt > 10)      $stop;
                   end
 
                @(posedge pclk);
 
           end
   end end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task pd2_test;
 
integer         mode;
integer         p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [ 1:0]   cd;
reg             pc;
reg     [31:0]   cbar;
reg     [31:0]   vbase;
reg     [31:0]   cbase;
reg     [31:0]   vbara;
reg     [31:0]   vbarb;
reg     [ 7:0]   bank, vbl;
reg     [ 5:0]   delay;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** Pixel Data Test 2                             ***");
$display("*****************************************************\n");
 
        s0.fill_mem(1);
 
        repeat(10)      @(posedge clk);
 
        vbara = 32'h0000_0000;
        vbarb = 32'h0040_0000;
        cbar  = 32'h0000_0800;
 
        m0.wb_wr1( `VBARA, 4'hf, vbara );
        m0.wb_wr1( `VBARB, 4'hf, vbarb );
 
        thsync = 6;
        thgdel = 20;
        thgate = 319;
        thlen = 390;
 
        tvsync = 1;
        tvgdel = 8;
        tvgate = 239;
//      tvgate = 240;
        tvlen = 280;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
 
*/
 
/*
        thsync = 39;
        thgdel = 124;
        thgate = 645;
        thlen = 832;
 
        tvsync = 2;
        tvgdel = 25;
        tvgate = 483;
        tvlen = 520;
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
 
`ifdef USE_VC
// Fill internal Color Lookup Table
repeat(10)      @(posedge clk);
for(n=0;n<512;n=n+1)
   begin
        //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
        data = s0.mem[ cbar[31:2] + n];
        m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
   end
repeat(10)      @(posedge clk);
`endif
 
 
vbl   = 3;
mode  = 3;
delay = 2;
 
for(delay=0;delay<6;delay=delay+1)
   begin
        s0.set_delay(delay);
for(vbl=0;vbl<4;vbl=vbl+1)
for(mode=0;mode<=4;mode=mode+1)
   begin
 
        m0.wb_wr1( `CTRL,  4'hf, 32'h0);
        repeat(100) @(posedge clk);
 
                case(mode)
                0:
                begin
                        cd = 2'h2;
                        pc = 1'b0;
                end
 
                1:
                begin
                        cd = 2'h0;
                        pc = 1'b0;
                end
 
                2:
                begin
                        cd = 2'h0;
                        pc = 1'b1;
                end
 
                3:
                begin
                        cd = 2'h1;
                        pc = 1'b0;
                end
 
                4:
                begin
                        cd = 2'h3;
                        pc = 1'b0;
                end
        endcase
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                vbl[1:0],// VBL
                                1'b1,   // CBSWE
                                1'b1,   // VBSWE
                                1'b0, // CBSIE
                                1'b0,   // VBSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                }
        );
 
bank = 0;
 
//for(bank=0;bank<3;bank=bank+1)
for(bank=0;bank<2;bank=bank+1)
   begin
 
        $display("VBL: %0d, Mode: %0d Screen: %0d", vbl, mode, bank);
        @(posedge vsync);
 
        error_cnt=0;
        // For Each Line
        for(l=0; l<tvgate;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                if(bank[0])      vbase = vbarb[31:2];
                else            vbase = vbara[31:2];
                if(bank[0])      cbase = cbar | 32'h0000_0400;
                else            cbase = cbar;
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                        0:       // 24 bit/pixel mode
                        begin
                                pra = pn[31:2] * 3;     // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                // Pixel Data
                                case(pn[1:0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = tmp[31:8];
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd[23:16] = tmp[7:0];
                                                tmp = s0.mem[paa+1];
                                                pd[15:0] = tmp[31:16];
                                        end
 
                                        2:
                                        begin
                                                tmp = s0.mem[paa+1];
                                                pd[23:8] = tmp[15:0];
                                                tmp = s0.mem[paa+2];
                                                pd[7:0] = tmp[31:24];
                                        end
 
                                        3:
                                        begin
                                                tmp = s0.mem[paa+2];
                                                pd = tmp[23:0];
                                        end
                                endcase
                        end
 
                        1:      // 8 bit/pixel grayscale mode
                        begin
                                pra = pn[31:2];         // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                case(pn[1:0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                                        end
 
                                        2:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                                        end
 
                                        3:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                                        end
                                endcase
                        end
 
                        2:      // 8 bit/pixel Pseudo Color mode
                        begin
                                pra = pn[31:2];         // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                case(pn[1:0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[31:24]];
                                                pd = tmp[23:0];
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[23:16]];
                                                pd = tmp[23:0];
                                        end
 
                                        2:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[15:8]];
                                                pd = tmp[23:0];
                                        end
 
                                        3:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp = s0.mem[cbase[31:2] + tmp[7:0]];
                                                pd = tmp[23:0];
                                        end
                                endcase
                        end
 
                        3:      // 16 bit/pixel mode
                        begin
                                pra = pn[31:1];         // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                case(pn[0])
                                        0:
                                        begin
                                                tmp = s0.mem[paa];
                                                tmp[15:0] = tmp[31:16];
                                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                                        end
 
                                        1:
                                        begin
                                                tmp = s0.mem[paa];
                                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                                        end
                                endcase
                        end
 
                        4:      // 32 bit/pixel mode
                        begin
                                pra = pn[31:0];          // Pixel relative Address
                                paa = pra + vbase;      // Pixel Absolute Address
 
                                tmp = s0.mem[paa];
                                pd = tmp[23:0];
                        end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                        if(error_cnt > 10)      $stop;
                   end
 
                @(posedge pclk);
 
           end
   end
end end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task ur_test;
 
integer         mode;
integer         n, p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   cbar;
reg     [31:0]   data;
reg     [7:0]    vbl;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** FIFO Underrun Test 1                          ***");
$display("*****************************************************\n");
 
        s0.delay=15;
        int_warn = 0;
 
        m0.wb_wr1( `VBARA, 4'hf, 0 );
        m0.wb_wr1( `VBARB, 4'hf, 123456 );
 
        cbar = 32'h0000_0800;
 
        thsync = 6;
        thgdel = 20;
        thgate = 319;
        thlen = 390;
 
        tvsync = 1;
        tvgdel = 8;
        tvgate = 239;
        tvlen = 280;
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
        mode = 0;
 
        // -------------------------------
        // Turn Off VGA before Mode Change
 
        m0.wb_wr1( `CTRL,  4'hf, 32'h0000_0000);
 
        s0.fill_mem(1);
 
`ifdef USE_VC
// Fill internal Color Lookup Table
repeat(10)      @(posedge clk);
for(n=0;n<512;n=n+1)
   begin
        //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
        data = s0.mem[ cbar[31:2] + n];
        m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
   end
repeat(10)      @(posedge clk);
`endif
 
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        // -------------------------------
        // Turn VGA back On ...
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'b00,  // VBL
                                1'b0,   // Reserved
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        while(!int)     @(posedge clk);
        m0.wb_rd1( `STAT,  4'hf, data);
        if(data[1] !== 1'b1)
           begin
                $display("ERROR: Did not get Line FIFO Interrupt. (%0t)",
                        $time);
           end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
m0.wb_wr1( `CTRL,  4'hf, 32'h0000_0000);
int_warn = 1;
s0.delay=1;
repeat(10) @(posedge clk);
 
end
endtask
 
 
//////////////////////////////////////
//
// DVI test section
//
 
 
task dvi_pd_test;
 
integer         mode;
integer         n, p, l;
reg     [ 2:0]   dvi_odf;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [11:0]   pda, pdb;
reg     [ 1:0]   cd;
reg             pc;
reg     [31:0]   data;
reg     [31:0]   cbar;
reg     [ 7:0]   vbl;
reg     [ 5:0]   delay;
 
begin
 
$display("\n\n");
$display("*****************************************************");
$display("*** DVI Pixel Data Test                           ***");
$display("*****************************************************\n");
 
        m0.wb_wr1( `VBARA, 4'hf, 0 );
        m0.wb_wr1( `VBARB, 4'hf, 123456 );
 
        cbar = 32'h0000_0800;
 
        thsync = 0;
        thgdel = 0;
        thgate = 320;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
        thsync = 39;
        thgdel = 124;
        thgate = 646;
        thlen = 832;
 
        tvsync = 2;
        tvgdel = 25;
        tvgate = 484;
        tvlen = 520;
 
        thsync = 6;
        thgdel = 20;
        thgate = 319;
        thlen = 390;
 
        tvsync = 1;
        tvgdel = 8;
        tvgate = 239;
        tvlen = 280;
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
// Choose mode, vbl, and delay
// These should have been tested & verified by previous tests
mode  = 3;
vbl   = 4;
delay = 0;
s0.set_delay(delay);
 
for(dvi_odf=0; dvi_odf<4;dvi_odf=dvi_odf +1)
   begin
        // -------------------------------
        // Turn Off VGA before Mode Change
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                2'h0,   // Reserved
                                dvi_odf[1:0],
                                12'h0,  // Reserved
                                bpol,
                                cpol,
                                vpol,
                                hpol,
                                pc,     // PC
                                cd,     // CD
                                2'h0,   // VBL
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0,   // CBSIE
                                1'b0,   // VBSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b0    // Video Enable
                                });
 
        s0.fill_mem(1);
 
        `ifdef USE_VC
        // Fill internal Color Lookup Table
        repeat(10)      @(posedge clk);
        for(n=0;n<512;n=n+1)
           begin
               //m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );
               data = s0.mem[ cbar[31:2] + n];
               m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );
           end
        repeat(10)      @(posedge clk);
        `endif
 
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        //repeat(50) @(posedge clk);
 
        // -------------------------------
        // Turn VGA back On ...
        m0.wb_wr1( `CTRL,  4'hf, {
                                2'h0,   // Reserved
                                dvi_odf[1:0],
                                12'h0,  // Reserved
                                bpol,
                                cpol,
                                vpol,
                                hpol,
                                pc,     // PC
                                cd,     // CD
                                2'h0,   // VBL
                                1'b0,   // CBSWE
                                1'b0,   // VBSWE
                                1'b0,   // CBSIE
                                1'b0,   // VBSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        $display("DVI output data format: %0h", dvi_odf);
        repeat(2) @(posedge vsync);
 
        // For Each Line
        for(l=0;l<tvgate;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(dvi_de_o == 1'b0) @(pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                //
                // Get the correct pixel data
                case(mode)
                   0:    // 24 bit/pixel mode
                   begin
                        pra = pn[31:2] * 3;     // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
 
                        // Pixel Data
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = tmp[31:8];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd[23:16] = tmp[7:0];
                                tmp = s0.mem[paa+1];
                                pd[15:0] = tmp[31:16];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa+1];
                                pd[23:8] = tmp[15:0];
                                tmp = s0.mem[paa+2];
                                pd[7:0] = tmp[31:24];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa+2];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   1:   // 8 bit/pixel grayscale mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                             end
                        endcase
                   end
 
                   2:   // 8 bit/pixel Pseudo Color mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[31:24]];
                                pd = tmp[23:0];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[23:16]];
                                pd = tmp[23:0];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[15:8]];
                                pd = tmp[23:0];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbar[31:2] + tmp[7:0]];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   3:   // 16 bit/pixel mode
                   begin
                        pra = pn[31:1];         // Pixel relative Address
                        paa = pra + 0;           // Pixel Absolute Address
                        case(pn[0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp[15:0] = tmp[31:16];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                        endcase
                   end
 
                endcase
 
                //
                // convert pixel data in DVI output format
                case (dvi_odf)
                   2'b00:
                      begin
                          pda = pd[11:0];
                          pdb = pd[23:12];
                      end
 
                   2'b01:
                      begin
                          pda = {pd[12:10],pd[7:3],pd[8],pd[2:0]};
                          pdb = {pd[23:19],pd[15:13],pd[18:16],pd[9]};
                      end
 
                   2'b10:
                      begin
                          pda = {pd[12:10],pd[7:3],4'h0};
                          pdb = {pd[23:19],pd[15:13],4'h0};
                      end
 
                   2'b11:
                      begin
                          pda = {pd[13:11],pd[7:3],4'h0};
                          pdb = {1'b0,pd[23:19],pd[15:14],4'h0};
                      end
                endcase
 
                //
                // verify pixel data
 
`ifdef VGA_12BIT_DVI
 
                // rising edge data
                if (pda !== dvi_d_o)
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h",
                                pda, dvi_d_o);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                        if(error_cnt > 10) $stop;
                   end
 
                @(negedge pclk_i);
 
                // falling edge data
                if (pdb !== dvi_d_o)
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h",
                                pdb, dvi_d_o);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                        if(error_cnt > 10) $stop;
                   end
                @(posedge pclk_i);
`else
 
                // compare data
                if ({pdb, pda} !== dvi_d_o)
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h",
                                {pdb, pda}, dvi_d_o);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                        if(error_cnt > 10) $stop;
                   end
 
                @(negedge pclk_i);
                @(posedge pclk_i);
`endif
           end
   end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tests Library ////`
4			`//// ////`
5			`//// ////`
6	29	rherveille	`//// Authors: Rudolf Usselmann, Richard Herveille ////`
7			`//// rudi@asics.ws, richard@asics.ws ////`
8	16	rudi	`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	60	markom	`// $Id: tests.v,v 1.10 2003-09-23 13:09:25 markom Exp $`
41	16	rudi	`//`
42	60	markom	`// $Date: 2003-09-23 13:09:25 $`
43			`// $Revision: 1.10 $`
44			`// $Author: markom $`
45	16	rudi	`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	60	markom	`// Revision 1.9 2003/08/22 07:17:21 rherveille`
51			`// Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.`
52			`//`
53	59	rherveille	`// Revision 1.8 2003/05/07 14:39:19 rherveille`
54			`// Added DVI tests`
55			`//`
56	54	rherveille	`// Revision 1.7 2003/05/07 09:45:28 rherveille`
57			`// Numerous updates and added checks`
58			`//`
59	52	rherveille	`// Revision 1.6 2003/03/19 12:20:53 rherveille`
60			`// Changed timing section in VGA core, changed testbench accordingly.`
61			`// Fixed bug in 'timing check' test.`
62			`//`
63	44	rherveille	`// Revision 1.5 2002/04/20 09:57:55 rherveille`
64			`// Changed testbench to reflect modified VGA timing generator.`
65	16	rudi	`//`
66			`//`
67			`//`
68	44	rherveille	`//`
69	59	rherveille	`//`
70	16	rudi
71
72			`task show_errors;`
73
74			`begin`
75
76			`$display("\n");`
77			`$display(" +--------------------+");`
78			`$display(" \| Total ERRORS: %0d \|", error_cnt);`
79			`$display(" +--------------------+");`
80
81			`end`
82			`endtask`
83
84
85			`task reg_test;`
86
87			`reg [31:0] data;`
88			`reg [31:0] pattern;`
89			`integer n;`
90
91			`begin`
92			`$display("\n\n");`
93			`$display("*****************************************************");`
94			`$display("* Register Test *");`
95			`$display("*****************************************************\n");`
96
97			`// Check reset Values`
98			`$display("Testing Reset Values ...");`
99			check( `CTRL, 0, 32'h0000_ffff, "CTRL ");
100			check( `STAT, 0, 32'h0000_0073, "STAT ");
101			check( `HTIM, 0, 32'hffff_ffff, "HTIM ");
102			check( `VTIM, 0, 32'hffff_ffff, "VTIM ");
103			check( `HVLEN, 0, 32'hffff_ffff, "HVLEN");
104			check( `VBARA, 0, 32'hffff_ffff, "VBARA");
105			check( `VBARB, 0, 32'hffff_ffff, "VBARB");
106
107			`$display("Testing Pattern R/W ...");`
108			`for(n=0;n<6;n=n+1)`
109	24	rherveille	`begin`
110			`case(n)`
111			`0: pattern = 32'h0000_0000;`
112			`1: pattern = 32'hffff_ffff;`
113			`2: pattern = 32'haaaa_aaaa;`
114			`3: pattern = 32'h5555_5555;`
115			`4: pattern = 32'hcccc_cccc;`
116			`5: pattern = 32'h3333_3333;`
117			`endcase`
118	16	rudi
119	24	rherveille	m0.wb_wr1( `CTRL, 4'hf, pattern );
120	59	rherveille	check( `CTRL, pattern, 32'hffff_ff9f, "CTRL ");
121	16	rudi
122	24	rherveille	m0.wb_wr1( `HTIM, 4'hf, pattern );
123			check( `HTIM, pattern, 32'hffff_ffff, "HTIM ");
124	16	rudi
125	24	rherveille	m0.wb_wr1( `VTIM, 4'hf, pattern );
126			check( `VTIM, pattern, 32'hffff_ffff, "VTIM ");
127	16	rudi
128	24	rherveille	m0.wb_wr1( `HVLEN, 4'hf, pattern );
129			check( `HVLEN, pattern, 32'hffff_ffff, "HVLEN");
130	16	rudi
131	24	rherveille	m0.wb_wr1( `VBARA, 4'hf, pattern );
132			check( `VBARA, pattern, 32'hffff_fffc, "VBARA");
133	16	rudi
134	24	rherveille	m0.wb_wr1( `VBARB, 4'hf, pattern );
135			check( `VBARB, pattern, 32'hffff_fffc, "VBARB");
136	16	rudi
137	24	rherveille	`end`
138	16	rudi
139			`repeat(10) @(posedge clk);`
140
141			`show_errors;`
142			`$display("*****************************************************");`
143			`$display("* Test DONE ... *");`
144			`$display("*****************************************************\n\n");`
145
146			`end`
147			`endtask`
148
149
150
151			`task check;`
152			`input [31:0] addr;`
153			`input [31:0] edata;`
154			`input [31:0] mask;`
155			`input [39:0] name;`
156
157			`reg [31:0] data;`
158			`begin`
159
160			`m0.wb_rd1( addr, 4'hf, data );`
161			`if(( (data & mask) != (edata & mask)) \| ((^data) === 1'bx) )`
162			`begin`
163			`$display("ERROR: %s Reg: Value Mismatch. Expected %h, Got %h (%0t)",`
164			`name, edata & mask, data, $time);`
165			`error_cnt = error_cnt + 1;`
166			`end`
167
168			`end`
169			`endtask`
170
171
172
173
174			`task tim_test;`
175
176			`integer mode;`
177
178			`begin`
179			`$display("\n\n");`
180			`$display("*****************************************************");`
181			`$display("* Timing Test *");`
182			`$display("*****************************************************\n");`
183
184			`s0.fill_mem(0);`
185
186			`repeat(10) @(posedge clk);`
187
188			m0.wb_wr1( `VBARA, 4'hf, 0 );
189			m0.wb_wr1( `VBARB, 4'hf, 0 );
190
191	44	rherveille	`mode = 2;`
192	16	rudi	`for(mode=0;mode<6;mode=mode+1)`
193			`begin`
194	44	rherveille
195			`// reset core`
196	16	rudi	`scen = 0;`
197	44	rherveille	m0.wb_wr1( `CTRL, 4'hf, 32'h0000_0000);
198			`repeat(10) @(posedge clk);`
199
200	16	rudi	`$display("Mode: %0d", mode);`
201
202			`case(mode)`
203	38	rherveille	`0:`
204			`begin`
205			`thsync = 0;`
206			`thgdel = 0;`
207	44	rherveille	`thgate = 319; // gate = 320`
208	38	rherveille	`thlen = 345;`
209	16	rudi
210	38	rherveille	`tvsync = 0;`
211			`tvgdel = 0;`
212	44	rherveille	`tvgate = 239; // vgate = 240`
213	38	rherveille	`tvlen = 245;`
214	16	rudi
215	38	rherveille	`hpol = 0;`
216			`vpol = 0;`
217			`cpol = 0;`
218			`bpol = 0;`
219			`end`
220	16	rudi
221	38	rherveille	`1:`
222			`begin`
223			`thsync = 18;`
224			`thgdel = 18;`
225	44	rherveille	`thgate = 319; // gate = 320`
226	38	rherveille	`thlen = 390;`
227	16	rudi
228	38	rherveille	`tvsync = 18;`
229			`tvgdel = 18;`
230	44	rherveille	`tvgate = 239; // vgate = 240`
231	38	rherveille	`tvlen = 290;`
232	16	rudi
233	38	rherveille	`hpol = 1;`
234			`vpol = 0;`
235			`cpol = 0;`
236			`bpol = 0;`
237			`end`
238	16	rudi
239	38	rherveille	`2:`
240			`begin`
241			`thsync = 1;`
242			`thgdel = 1;`
243	44	rherveille	`thgate = 639; // hgate = 640`
244			`thlen = 644;`
245	16	rudi
246	38	rherveille	`tvsync = 1;`
247			`tvgdel = 1;`
248	44	rherveille	`tvgate = 479; // vgate = 480`
249			`tvlen = 484;`
250	16	rudi
251	38	rherveille	`hpol = 0;`
252			`vpol = 1;`
253			`cpol = 0;`
254			`bpol = 0;`
255			`end`
256	16	rudi
257	38	rherveille	`3:`
258			`begin`
259			`thsync = 0;`
260			`thgdel = 2;`
261	44	rherveille	`thgate = 799; // hgate = 800`
262	38	rherveille	`thlen = 804;`
263	16	rudi
264	38	rherveille	`tvsync = 0;`
265			`tvgdel = 2;`
266	44	rherveille	`tvgate = 599; // vgate = 600`
267	38	rherveille	`tvlen = 604;`
268	16	rudi
269	38	rherveille	`hpol = 0;`
270			`vpol = 0;`
271			`cpol = 1;`
272			`bpol = 0;`
273			`end`
274	16	rudi
275	38	rherveille	`4:`
276			`begin`
277			`thsync = 3;`
278			`thgdel = 2;`
279	44	rherveille	`thgate = 799; // hgate = 800`
280			`thlen = 807;`
281	16	rudi
282	38	rherveille	`tvsync = 2;`
283			`tvgdel = 2;`
284	44	rherveille	`tvgate = 599; // vgate = 600`
285	38	rherveille	`tvlen = 606;`
286	16	rudi
287	38	rherveille	`hpol = 0;`
288			`vpol = 0;`
289			`cpol = 0;`
290			`bpol = 1;`
291			`end`
292	16	rudi
293	38	rherveille	`5:`
294			`begin`
295			`thsync = 6;`
296			`thgdel = 2;`
297	44	rherveille	`thgate = 799; // hgate = 800`
298	38	rherveille	`thlen = 810;`
299	16	rudi
300	38	rherveille	`tvsync = 4;`
301			`tvgdel = 2;`
302	44	rherveille	`tvgate = 599; // vgate = 600`
303			`tvlen = 608;`
304	16	rudi
305	38	rherveille	`hpol = 1;`
306			`vpol = 1;`
307			`cpol = 1;`
308			`bpol = 1;`
309			`end`
310	16	rudi	`endcase`
311
312			`/*`
313			`thsync = 0;`
314			`thgdel = 0;`
315			`thgate = 64;`
316			`thlen = 70;`
317
318			`tvsync = 0;`
319			`tvgdel = 0;`
320			`tvgate = 64;`
321			`tvlen = 70;`
322
323			`hpol = 0;`
324			`vpol = 0;`
325			`cpol = 0;`
326			`bpol = 0;`
327			`*/`
328
329
330			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
331			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
332			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
333			m0.wb_wr1( `CTRL, 4'hf, {
334			`16'h0,`
335			`bpol, cpol,`
336			`vpol, hpol,`
337			`1'b0, // PC`
338			`2'h0, // CD`
339			`2'h0, // VBL`
340			`2'h0, // Reserved`
341			`5'h01 // Bank Switch, INT, VideoEn`
342			`});`
343
344			`repeat(2) @(posedge vsync);`
345			`scen = 1;`
346			`repeat(4) @(posedge vsync);`
347			`end`
348
349			`scen = 0;`
350			`repeat(10) @(posedge clk);`
351
352			`show_errors;`
353			`$display("*****************************************************");`
354			`$display("* Test DONE ... *");`
355			`$display("*****************************************************\n\n");`
356
357			`end`
358			`endtask`
359
360
361
362
363			`task pd1_test;`
364
365			`integer mode;`
366			`integer n, p, l;`
367			`reg [31:0] pn;`
368			`reg [31:0] pra, paa, tmp;`
369			`reg [23:0] pd;`
370	52	rherveille	`reg [ 1:0] cd;`
371	16	rudi	`reg pc;`
372			`reg [31:0] data;`
373	52	rherveille	`reg [31:0] cbar;`
374			`reg [ 7:0] vbl;`
375			`reg [ 5:0] delay;`
376	16	rudi
377			`begin`
378
379			`$display("\n\n");`
380			`$display("*****************************************************");`
381			`$display("* Pixel Data Test 1 *");`
382			`$display("*****************************************************\n");`
383
384			m0.wb_wr1( `VBARA, 4'hf, 0 );
385			m0.wb_wr1( `VBARB, 4'hf, 123456 );
386
387	24	rherveille	`cbar = 32'h0000_0800;`
388	16	rudi
389			`thsync = 0;`
390			`thgdel = 0;`
391	24	rherveille	`thgate = 320;`
392	16	rudi	`thlen = 345;`
393
394			`tvsync = 0;`
395			`tvgdel = 0;`
396			`tvgate = 240;`
397			`tvlen = 245;`
398
399			`thsync = 39;`
400			`thgdel = 124;`
401			`thgate = 646;`
402			`thlen = 832;`
403
404			`tvsync = 2;`
405			`tvgdel = 25;`
406			`tvgate = 484;`
407			`tvlen = 520;`
408
409			`thsync = 6;`
410			`thgdel = 20;`
411			`thgate = 319;`
412			`thlen = 390;`
413
414			`tvsync = 1;`
415			`tvgdel = 8;`
416			`tvgate = 239;`
417			`tvlen = 280;`
418
419			`/*`
420			`thsync = 0;`
421			`thgdel = 0;`
422			`thgate = 63;`
423			`thlen = 70;`
424
425			`tvsync = 0;`
426			`tvgdel = 0;`
427			`tvgate = 32;`
428			`tvlen = 36;`
429
430			`thsync = 119;`
431			`thgdel = 61;`
432			`thgate = 805;`
433			`thlen = 1038;`
434
435			`tvsync = 5;`
436			`tvgdel = 20;`
437			`tvgate = 600;`
438			`tvlen = 665;`
439
440			`*/`
441
442			`hpol = 0;`
443			`vpol = 0;`
444			`cpol = 0;`
445			`bpol = 0;`
446
447			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
448			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
449			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
450
451	52	rherveille	`mode = 3;`
452			`vbl = 1;`
453			`delay = 1;`
454	16	rudi
455	52	rherveille	`for(delay=0;delay<6;delay=delay+1)`
456			`begin`
457			`s0.set_delay(delay);`
458	16	rudi	`for(vbl=0;vbl<4;vbl=vbl+1)`
459			`for(mode=0;mode<4;mode=mode+1)`
460			`begin`
461			`// -------------------------------`
462			`// Turn Off VGA before Mode Change`
463
464			m0.wb_wr1( `CTRL, 4'hf, {
465			`16'h0, // Reserved`
466			`bpol, cpol,`
467			`vpol, hpol,`
468			`pc, // 1'b0, // PC`
469			`cd, // 2'h2, // CD`
470			`2'h0, // VBL`
471			`1'b0, // CBSWE`
472			`1'b0, // VBSWE`
473	24	rherveille	`1'b0, // CBSIE`
474			`1'b0, // VBSIE`
475	16	rudi	`1'b0, // HIE`
476			`1'b0, // VIE`
477			`1'b0 // Video Enable`
478			`});`
479
480			`s0.fill_mem(1);`
481
482	52	rherveille	`ifdef USE_VC
483			`// Fill internal Color Lookup Table`
484			`repeat(10) @(posedge clk);`
485			`for(n=0;n<512;n=n+1)`
486			`begin`
487			`//m0.wb_rd1( 32'h0002_0000 + (n*4), 4'hf, data );`
488			`data = s0.mem[ cbar[31:2] + n];`
489			`m0.wb_wr1( 32'h0000_0800 + (n*4), 4'hf, data );`
490			`end`
491			`repeat(10) @(posedge clk);`
492			`endif
493	16	rudi
494			`case(mode)`
495			`0:`
496			`begin`
497			`cd = 2'h2;`
498			`pc = 1'b0;`
499			`end`
500			`1:`

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