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[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [wb_b3_check.v] - Blame information for rev 52

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE revB.3 Registered Feedback Cycle checker          ////
////                                                             ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@ascis.ws                                   ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2003 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
module wb_b3_check (clk_i, cyc_i, stb_i, we_i, cti_i, bte_i, ack_i, err_i, rty_i);
 
input       clk_i;
input       cyc_i;
input       stb_i;
input [2:0] cti_i;
input [1:0] bte_i;
input       we_i;
input       ack_i;
input       err_i;
input       rty_i;
 
 
parameter [2:0] cti_classic   = 3'b000;
parameter [2:0] cti_streaming = 3'b001;
parameter [2:0] cti_inc_burst = 3'b010;
parameter [2:0] cti_eob       = 3'b111;
 
// check CTI, BTE
reg [2:0] pcti; // previous cti
reg [1:0] pbte; // previous bte
reg       pwe;  // previous we
reg       chk;
 
integer wb_b3_err;
 
initial
begin
  chk = 0;
  wb_b3_err = 0;
 
  $display ("**********************************************");
  $display ("**                                          **");
  $display ("** WISBONE RevB.3 sanity check instantiated **");
  $display ("** (C) 2003 Richard Herveille               **");
  $display ("**                                          **");
  $display ("**********************************************");
end
 
 
always @(posedge clk_i)
  begin
      pcti <= #1 cti_i;
      pbte <= #1 bte_i;
      pwe  <= #1 we_i;
  end
 
 
always @(posedge clk_i)
  if (cyc_i) begin
    chk <= #1 1'b1;
  end else
    chk <= #1 1'b0;
 
 
 
//
// Check CTI_I
always @(cti_i)
 if (chk)
   if (cyc_i) begin
     if (ack_i)
       case (cti_i)
          cti_eob: ; // ok
 
          default:
            if ( (cti_i !== pcti) && (pcti !== cti_eob) ) begin
              $display("\nWISHBONE revB.3 Burst error. CTI change from %b to %b not allowed. (%t)\n",
                        pcti, cti_i, $time);
 
              wb_b3_err = wb_b3_err +1;
            end
       endcase
     else
       if ( (cti_i !== pcti) && (pcti !== cti_eob) ) begin
         $display("\nWISHBONE revB.3 Burst error. Illegal CTI change during burst transfer. (%t)\n",
                   $time);
 
         wb_b3_err = wb_b3_err +1;
       end
   end else
     case (pcti)
        cti_classic: ; //ok
        cti_eob: ;     // ok
 
        default: begin
          $display("\nWISHBONE revB.3 Burst error. Cycle negated without EOB (CTI=%b). (%t)\n",
                    pcti, $time);
 
          wb_b3_err = wb_b3_err +1;
        end
     endcase
 
 
//
// Check BTE_I
always @(bte_i)
 if (chk & cyc_i)
   if (ack_i) begin
     if ( (pcti !== cti_eob) && (bte_i !== pbte) ) begin
        $display("\nWISHBONE revB.3 Burst ERROR. BTE change from %b to %b not allowed. (%t)\n",
                  pbte, bte_i, $time);
 
        wb_b3_err = wb_b3_err +1;
     end
   end else begin
     $display("\nWISHBONE revB.3 Burst error. Illegal BTE change in burst cycle. (%t)\n",
               $time);
 
     wb_b3_err = wb_b3_err +1;
   end
 
//
// Check WE_I
always @(we_i)
 if (chk & cyc_i & stb_i)
   if (ack_i) begin
     if ( (pcti !== cti_eob) && (we_i !== pwe)) begin
       $display("\nWISHBONE revB.3 Burst ERROR. WE change from %b to %b not allowed. (%t)\n",
                 pwe, we_i, $time);
 
       wb_b3_err = wb_b3_err +1;
     end
   end else begin
     $display("\nWISHBONE revB.3 Burst error. Illegal WE change in burst cycle. (%t)\n",
               $time);
 
     wb_b3_err = wb_b3_err +1;
   end
 
 
 
//
// Check ACK_I, ERR_I, RTY_I
always @(posedge clk_i)
if (cyc_i & stb_i)
  case ({ack_i, err_i, rty_i})
     3'b000: ;
     3'b001: ;
     3'b010: ;
     3'b100: ;
 
     default: begin
        $display("\n WISHBONE revB.3 ERROR. Either ack(%0b), rty(%0b), or err(%0b) may be asserted. (%t)",
               ack_i, rty_i, err_i, $time);
 
        wb_b3_err = wb_b3_err +1;
     end
  endcase
 
//
// check errors
always @(wb_b3_err)
  if (chk && (wb_b3_err > 10) ) begin
    $display ("**********************************************");
    $display ("**                                          **");
    $display ("** More than 10 WISBONE RevB.3 errors found **");
    $display ("** Simulation stopped                       **");
    $display ("**                                          **");
    $display ("**********************************************");
    $stop;
  end
endmodule

Line No.	Rev	Author	Line
1	46	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE revB.3 Registered Feedback Cycle checker ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@ascis.ws ////`
8			`//// ////`
9			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
10			`//// ////`
11			`/////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2003 Richard Herveille ////`
14			`//// richard@asics.ws ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer.////`
20			`//// ////`
21			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
22			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
23			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
24			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
25			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
26			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
27			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
28			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
29			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
30			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
31			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
32			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
33			`//// POSSIBILITY OF SUCH DAMAGE. ////`
34			`//// ////`
35			`/////////////////////////////////////////////////////////////////////`
36
37			`module wb_b3_check (clk_i, cyc_i, stb_i, we_i, cti_i, bte_i, ack_i, err_i, rty_i);`
38
39			`input clk_i;`
40			`input cyc_i;`
41			`input stb_i;`
42			`input [2:0] cti_i;`
43			`input [1:0] bte_i;`
44			`input we_i;`
45			`input ack_i;`
46			`input err_i;`
47			`input rty_i;`
48
49
50			`parameter [2:0] cti_classic = 3'b000;`
51			`parameter [2:0] cti_streaming = 3'b001;`
52			`parameter [2:0] cti_inc_burst = 3'b010;`
53			`parameter [2:0] cti_eob = 3'b111;`
54
55			`// check CTI, BTE`
56			`reg [2:0] pcti; // previous cti`
57			`reg [1:0] pbte; // previous bte`
58			`reg pwe; // previous we`
59			`reg chk;`
60
61	52	rherveille	`integer wb_b3_err;`
62
63			`initial`
64			`begin`
65			`chk = 0;`
66			`wb_b3_err = 0;`
67
68			`$display ("**********************************************");`
69			`$display (" ");`
70			`$display (" WISBONE RevB.3 sanity check instantiated ");`
71			`$display (" (C) 2003 Richard Herveille ");`
72			`$display (" ");`
73			`$display ("**********************************************");`
74			`end`
75
76
77	46	rherveille	`always @(posedge clk_i)`
78	52	rherveille	`begin`
79			`pcti <= #1 cti_i;`
80			`pbte <= #1 bte_i;`
81			`pwe <= #1 we_i;`
82			`end`
83	46	rherveille
84
85			`always @(posedge clk_i)`
86	52	rherveille	`if (cyc_i) begin`
87			`chk <= #1 1'b1;`
88			`end else`
89	46	rherveille	`chk <= #1 1'b0;`
90
91
92	52	rherveille
93	46	rherveille	`//`
94			`// Check CTI_I`
95	52	rherveille	`always @(cti_i)`
96			`if (chk)`
97			`if (cyc_i) begin`
98			`if (ack_i)`
99			`case (cti_i)`
100			`cti_eob: ; // ok`
101	46	rherveille
102	52	rherveille	`default:`
103			`if ( (cti_i !== pcti) && (pcti !== cti_eob) ) begin`
104			`$display("\nWISHBONE revB.3 Burst error. CTI change from %b to %b not allowed. (%t)\n",`
105			`pcti, cti_i, $time);`
106	46	rherveille
107	52	rherveille	`wb_b3_err = wb_b3_err +1;`
108			`end`
109			`endcase`
110			`else`
111			`if ( (cti_i !== pcti) && (pcti !== cti_eob) ) begin`
112			`$display("\nWISHBONE revB.3 Burst error. Illegal CTI change during burst transfer. (%t)\n",`
113			`$time);`
114	46	rherveille
115	52	rherveille	`wb_b3_err = wb_b3_err +1;`
116			`end`
117			`end else`
118			`case (pcti)`
119			`cti_classic: ; //ok`
120			`cti_eob: ; // ok`
121
122			`default: begin`
123			`$display("\nWISHBONE revB.3 Burst error. Cycle negated without EOB (CTI=%b). (%t)\n",`
124			`pcti, $time);`
125
126			`wb_b3_err = wb_b3_err +1;`
127			`end`
128			`endcase`
129
130
131	46	rherveille	`//`
132			`// Check BTE_I`
133	52	rherveille	`always @(bte_i)`
134			`if (chk & cyc_i)`
135			`if (ack_i) begin`
136			`if ( (pcti !== cti_eob) && (bte_i !== pbte) ) begin`
137			`$display("\nWISHBONE revB.3 Burst ERROR. BTE change from %b to %b not allowed. (%t)\n",`
138			`pbte, bte_i, $time);`
139	46	rherveille
140	52	rherveille	`wb_b3_err = wb_b3_err +1;`
141			`end`
142			`end else begin`
143			`$display("\nWISHBONE revB.3 Burst error. Illegal BTE change in burst cycle. (%t)\n",`
144			`$time);`
145	46	rherveille
146	52	rherveille	`wb_b3_err = wb_b3_err +1;`
147			`end`
148
149	46	rherveille	`//`
150			`// Check WE_I`
151	52	rherveille	`always @(we_i)`
152			`if (chk & cyc_i & stb_i)`
153			`if (ack_i) begin`
154			`if ( (pcti !== cti_eob) && (we_i !== pwe)) begin`
155			`$display("\nWISHBONE revB.3 Burst ERROR. WE change from %b to %b not allowed. (%t)\n",`
156			`pwe, we_i, $time);`
157	46	rherveille
158	52	rherveille	`wb_b3_err = wb_b3_err +1;`
159			`end`
160			`end else begin`
161			`$display("\nWISHBONE revB.3 Burst error. Illegal WE change in burst cycle. (%t)\n",`
162			`$time);`
163	46	rherveille
164	52	rherveille	`wb_b3_err = wb_b3_err +1;`
165			`end`
166
167
168
169	46	rherveille	`//`
170			`// Check ACK_I, ERR_I, RTY_I`
171			`always @(posedge clk_i)`
172	52	rherveille	`if (cyc_i & stb_i)`
173	46	rherveille	`case ({ack_i, err_i, rty_i})`
174	52	rherveille	`3'b000: ;`
175			`3'b001: ;`
176			`3'b010: ;`
177			`3'b100: ;`
178	46	rherveille
179	52	rherveille	`default: begin`
180			`$display("\n WISHBONE revB.3 ERROR. Either ack(%0b), rty(%0b), or err(%0b) may be asserted. (%t)",`
181	46	rherveille	`ack_i, rty_i, err_i, $time);`
182	52	rherveille
183			`wb_b3_err = wb_b3_err +1;`
184			`end`
185	46	rherveille	`endcase`
186
187	52	rherveille	`//`
188			`// check errors`
189			`always @(wb_b3_err)`
190			`if (chk && (wb_b3_err > 10) ) begin`
191			`$display ("**********************************************");`
192			`$display (" ");`
193			`$display (" More than 10 WISBONE RevB.3 errors found ");`
194			`$display (" Simulation stopped ");`
195			`$display (" ");`
196			`$display ("**********************************************");`
197			`$stop;`
198			`end`
199	46	rherveille	`endmodule`

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[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [wb_b3_check.v] - Blame information for rev 52