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[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 16

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.1 2001-08-21 05:42:32 rudi Exp $
//
//  $Date: 2001-08-21 05:42:32 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack)     @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
//@(posedge clk);
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack)     @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack)     @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask
 
 
endmodule

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[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 16

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: wb_mast_model.v,v 1.1 2001-08-21 05:42:32 rudi Exp $`
41			`//`
42			`// $Date: 2001-08-21 05:42:32 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53
54			`include "wb_model_defines.v"
55
56			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
57
58			`input clk, rst;`
59			`output [31:0] adr;`
60			`input [31:0] din;`
61			`output [31:0] dout;`
62			`output cyc, stb;`
63			`output [3:0] sel;`
64			`output we;`
65			`input ack, err, rty;`
66
67			`////////////////////////////////////////////////////////////////////`
68			`//`
69			`// Local Wires`
70			`//`
71
72			`reg [31:0] adr;`
73			`reg [31:0] dout;`
74			`reg cyc, stb;`
75			`reg [3:0] sel;`
76			`reg we;`
77
78			`////////////////////////////////////////////////////////////////////`
79			`//`
80			`// Memory Logic`
81			`//`
82
83			`initial`
84			`begin`
85			`//adr = 32'hxxxx_xxxx;`
86			`//adr = 0;`
87			`adr = 32'hffff_ffff;`
88			`dout = 32'hxxxx_xxxx;`
89			`cyc = 0;`
90			`stb = 0;`
91			`sel = 4'hx;`
92			`we = 1'hx;`
93			`#1;`
94			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
95			`end`
96
97			`////////////////////////////////////////////////////////////////////`
98			`//`
99			`// Write 1 Word Task`
100			`//`
101
102			`task wb_wr1;`
103			`input [31:0] a;`
104			`input [3:0] s;`
105			`input [31:0] d;`
106
107			`begin`
108
109			`@(posedge clk);`
110			`#1;`
111			`adr = a;`
112			`dout = d;`
113			`cyc = 1;`
114			`stb = 1;`
115			`we=1;`
116			`sel = s;`
117
118			`@(posedge clk);`
119			`while(~ack) @(posedge clk);`
120			`#1;`
121			`cyc=0;`
122			`stb=0;`
123			`adr = 32'hxxxx_xxxx;`
124			`dout = 32'hxxxx_xxxx;`
125			`we = 1'hx;`
126			`sel = 4'hx;`
127
128			`//@(posedge clk);`
129			`end`
130			`endtask`
131
132
133			`////////////////////////////////////////////////////////////////////`
134			`//`
135			`// Write 4 Words Task`
136			`//`
137
138			`task wb_wr4;`
139			`input [31:0] a;`
140			`input [3:0] s;`
141			`input delay;`
142			`input [31:0] d1;`
143			`input [31:0] d2;`
144			`input [31:0] d3;`
145			`input [31:0] d4;`
146
147			`integer delay;`
148
149			`begin`
150
151			`@(posedge clk);`
152			`#1;`
153			`cyc = 1;`
154			`sel = s;`
155
156			`repeat(delay)`
157			`begin`
158			`@(posedge clk);`
159			`#1;`
160			`end`
161			`adr = a;`
162			`dout = d1;`
163			`stb = 1;`
164			`we=1;`
165			`while(~ack) @(posedge clk);`
166			`#2;`
167			`stb=0;`
168			`we=1'bx;`
169			`dout = 32'hxxxx_xxxx;`
170
171
172			`repeat(delay)`
173			`begin`
174			`@(posedge clk);`
175			`#1;`
176			`end`
177			`stb=1;`
178			`adr = a+4;`
179			`dout = d2;`
180			`we=1;`
181			`@(posedge clk);`
182			`while(~ack) @(posedge clk);`
183			`#2;`
184			`stb=0;`
185			`we=1'bx;`
186			`dout = 32'hxxxx_xxxx;`
187
188			`repeat(delay)`
189			`begin`
190			`@(posedge clk);`
191			`#1;`
192			`end`
193			`stb=1;`
194			`adr = a+8;`
195			`dout = d3;`
196			`we=1;`
197			`@(posedge clk);`
198			`while(~ack) @(posedge clk);`
199			`#2;`
200			`stb=0;`
201			`we=1'bx;`
202			`dout = 32'hxxxx_xxxx;`
203
204			`repeat(delay)`
205			`begin`
206			`@(posedge clk);`
207			`#1;`
208			`end`
209			`stb=1;`
210			`adr = a+12;`
211			`dout = d4;`
212			`we=1;`
213			`@(posedge clk);`
214			`while(~ack) @(posedge clk);`
215			`#1;`
216			`stb=0;`
217			`cyc=0;`
218
219			`adr = 32'hxxxx_xxxx;`
220			`dout = 32'hxxxx_xxxx;`
221			`we = 1'hx;`
222			`sel = 4'hx;`
223
224			`end`
225			`endtask`
226
227
228			`////////////////////////////////////////////////////////////////////`
229			`//`
230			`// Read 1 Word Task`
231			`//`
232
233			`task wb_rd1;`
234			`input [31:0] a;`
235			`input [3:0] s;`
236			`output [31:0] d;`
237
238			`begin`
239
240			`@(posedge clk);`
241			`#1;`
242			`adr = a;`
243			`cyc = 1;`
244			`stb = 1;`
245			`we = 0;`
246			`sel = s;`
247
248			`//@(posedge clk);`
249			`while(~ack) @(posedge clk);`
250			`d = din;`
251			`#1;`
252			`cyc=0;`
253			`stb=0;`
254			`//adr = 32'hxxxx_xxxx;`
255			`//adr = 0;`
256			`adr = 32'hffff_ffff;`
257			`dout = 32'hxxxx_xxxx;`
258			`we = 1'hx;`
259			`sel = 4'hx;`
260
261			`end`
262			`endtask`
263
264
265			`////////////////////////////////////////////////////////////////////`
266			`//`
267			`// Read 4 Words Task`
268			`//`
269
270
271			`task wb_rd4;`
272			`input [31:0] a;`
273			`input [3:0] s;`
274			`input delay;`
275			`output [31:0] d1;`
276			`output [31:0] d2;`
277			`output [31:0] d3;`
278			`output [31:0] d4;`
279
280			`integer delay;`
281			`begin`
282
283			`@(posedge clk);`
284			`#1;`
285			`cyc = 1;`
286			`we = 0;`
287			`sel = s;`
288			`repeat(delay) @(posedge clk);`
289
290			`adr = a;`
291			`stb = 1;`
292			`while(~ack) @(posedge clk);`
293			`d1 = din;`
294			`#2;`
295			`stb=0;`
296			`we = 1'hx;`
297			`sel = 4'hx;`
298			`repeat(delay)`
299			`begin`
300			`@(posedge clk);`
301			`#1;`
302			`end`
303			`we = 0;`
304			`sel = s;`
305
306			`adr = a+4;`
307			`stb = 1;`
308			`@(posedge clk);`
309			`while(~ack) @(posedge clk);`
310			`d2 = din;`
311			`#2;`
312			`stb=0;`
313			`we = 1'hx;`
314			`sel = 4'hx;`
315			`repeat(delay)`
316			`begin`
317			`@(posedge clk);`
318			`#1;`
319			`end`
320			`we = 0;`
321			`sel = s;`
322
323
324			`adr = a+8;`
325			`stb = 1;`
326			`@(posedge clk);`
327			`while(~ack) @(posedge clk);`
328			`d3 = din;`
329			`#2;`
330			`stb=0;`
331			`we = 1'hx;`
332			`sel = 4'hx;`
333			`repeat(delay)`
334			`begin`
335			`@(posedge clk);`
336			`#1;`
337			`end`
338			`we = 0;`
339			`sel = s;`
340
341			`adr = a+12;`
342			`stb = 1;`
343			`@(posedge clk);`
344			`while(~ack) @(posedge clk);`
345			`d4 = din;`
346			`#1;`
347			`stb=0;`
348			`cyc=0;`
349			`we = 1'hx;`
350			`sel = 4'hx;`
351			`adr = 32'hffff_ffff;`
352			`end`
353			`endtask`
354
355
356			`endmodule`