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[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 62

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.2 2003-09-23 13:09:25 markom Exp $
//
//  $Date: 2003-09-23 13:09:25 $
//  $Revision: 1.2 $
//  $Author: markom $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/08/21 05:42:32  rudi
//
//               - Changed Directory Structure
//               - Added verilog Source Code
//               - Changed IO pin names and defines statements
//
//
//
//                        
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        //adr = 32'hxxxx_xxxx;
        //adr = 0;
        adr = 32'hffff_ffff;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack)     @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
//@(posedge clk);
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack)     @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
//@(posedge clk);
while(~ack)     @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack)     @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack)     @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask
 
 
endmodule

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[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 62

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	60	markom	`// $Id: wb_mast_model.v,v 1.2 2003-09-23 13:09:25 markom Exp $`
41	16	rudi	`//`
42	60	markom	`// $Date: 2003-09-23 13:09:25 $`
43			`// $Revision: 1.2 $`
44			`// $Author: markom $`
45	16	rudi	`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	60	markom	`// Revision 1.1 2001/08/21 05:42:32 rudi`
51	16	rudi	`//`
52	60	markom	`// - Changed Directory Structure`
53			`// - Added verilog Source Code`
54			`// - Changed IO pin names and defines statements`
55	16	rudi	`//`
56	60	markom	`//`
57			`//`
58	16	rudi	`//`
59
60			`include "wb_model_defines.v"
61
62			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
63
64			`input clk, rst;`
65			`output [31:0] adr;`
66			`input [31:0] din;`
67			`output [31:0] dout;`
68			`output cyc, stb;`
69			`output [3:0] sel;`
70			`output we;`
71			`input ack, err, rty;`
72
73			`////////////////////////////////////////////////////////////////////`
74			`//`
75			`// Local Wires`
76			`//`
77
78			`reg [31:0] adr;`
79			`reg [31:0] dout;`
80			`reg cyc, stb;`
81			`reg [3:0] sel;`
82			`reg we;`
83
84			`////////////////////////////////////////////////////////////////////`
85			`//`
86			`// Memory Logic`
87			`//`
88
89			`initial`
90			`begin`
91			`//adr = 32'hxxxx_xxxx;`
92			`//adr = 0;`
93			`adr = 32'hffff_ffff;`
94			`dout = 32'hxxxx_xxxx;`
95			`cyc = 0;`
96			`stb = 0;`
97			`sel = 4'hx;`
98			`we = 1'hx;`
99			`#1;`
100			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
101			`end`
102
103			`////////////////////////////////////////////////////////////////////`
104			`//`
105			`// Write 1 Word Task`
106			`//`
107
108			`task wb_wr1;`
109			`input [31:0] a;`
110			`input [3:0] s;`
111			`input [31:0] d;`
112
113			`begin`
114			`@(posedge clk);`
115			`#1;`
116			`adr = a;`
117			`dout = d;`
118			`cyc = 1;`
119			`stb = 1;`
120			`we=1;`
121			`sel = s;`
122
123			`@(posedge clk);`
124			`while(~ack) @(posedge clk);`
125			`#1;`
126			`cyc=0;`
127			`stb=0;`
128			`adr = 32'hxxxx_xxxx;`
129			`dout = 32'hxxxx_xxxx;`
130			`we = 1'hx;`
131			`sel = 4'hx;`
132
133			`//@(posedge clk);`
134			`end`
135			`endtask`
136
137
138			`////////////////////////////////////////////////////////////////////`
139			`//`
140			`// Write 4 Words Task`
141			`//`
142
143			`task wb_wr4;`
144			`input [31:0] a;`
145			`input [3:0] s;`
146			`input delay;`
147			`input [31:0] d1;`
148			`input [31:0] d2;`
149			`input [31:0] d3;`
150			`input [31:0] d4;`
151
152			`integer delay;`
153
154			`begin`
155
156			`@(posedge clk);`
157			`#1;`
158			`cyc = 1;`
159			`sel = s;`
160
161			`repeat(delay)`
162			`begin`
163			`@(posedge clk);`
164			`#1;`
165			`end`
166			`adr = a;`
167			`dout = d1;`
168			`stb = 1;`
169			`we=1;`
170			`while(~ack) @(posedge clk);`
171			`#2;`
172			`stb=0;`
173			`we=1'bx;`
174			`dout = 32'hxxxx_xxxx;`
175
176
177			`repeat(delay)`
178			`begin`
179			`@(posedge clk);`
180			`#1;`
181			`end`
182			`stb=1;`
183			`adr = a+4;`
184			`dout = d2;`
185			`we=1;`
186			`@(posedge clk);`
187			`while(~ack) @(posedge clk);`
188			`#2;`
189			`stb=0;`
190			`we=1'bx;`
191			`dout = 32'hxxxx_xxxx;`
192
193			`repeat(delay)`
194			`begin`
195			`@(posedge clk);`
196			`#1;`
197			`end`
198			`stb=1;`
199			`adr = a+8;`
200			`dout = d3;`
201			`we=1;`
202			`@(posedge clk);`
203			`while(~ack) @(posedge clk);`
204			`#2;`
205			`stb=0;`
206			`we=1'bx;`
207			`dout = 32'hxxxx_xxxx;`
208
209			`repeat(delay)`
210			`begin`
211			`@(posedge clk);`
212			`#1;`
213			`end`
214			`stb=1;`
215			`adr = a+12;`
216			`dout = d4;`
217			`we=1;`
218			`@(posedge clk);`
219			`while(~ack) @(posedge clk);`
220			`#1;`
221			`stb=0;`
222			`cyc=0;`
223
224			`adr = 32'hxxxx_xxxx;`
225			`dout = 32'hxxxx_xxxx;`
226			`we = 1'hx;`
227			`sel = 4'hx;`
228
229			`end`
230			`endtask`
231
232
233			`////////////////////////////////////////////////////////////////////`
234			`//`
235			`// Read 1 Word Task`
236			`//`
237
238			`task wb_rd1;`
239			`input [31:0] a;`
240			`input [3:0] s;`
241			`output [31:0] d;`
242
243			`begin`
244
245			`@(posedge clk);`
246			`#1;`
247			`adr = a;`
248			`cyc = 1;`
249			`stb = 1;`
250			`we = 0;`
251			`sel = s;`
252
253			`//@(posedge clk);`
254			`while(~ack) @(posedge clk);`
255			`d = din;`
256			`#1;`
257			`cyc=0;`
258			`stb=0;`
259			`//adr = 32'hxxxx_xxxx;`
260			`//adr = 0;`
261			`adr = 32'hffff_ffff;`
262			`dout = 32'hxxxx_xxxx;`
263			`we = 1'hx;`
264			`sel = 4'hx;`
265
266			`end`
267			`endtask`
268
269
270			`////////////////////////////////////////////////////////////////////`
271			`//`
272			`// Read 4 Words Task`
273			`//`
274
275
276			`task wb_rd4;`
277			`input [31:0] a;`
278			`input [3:0] s;`
279			`input delay;`
280			`output [31:0] d1;`
281			`output [31:0] d2;`
282			`output [31:0] d3;`
283			`output [31:0] d4;`
284
285			`integer delay;`
286			`begin`
287
288			`@(posedge clk);`
289			`#1;`
290			`cyc = 1;`
291			`we = 0;`
292			`sel = s;`
293			`repeat(delay) @(posedge clk);`
294
295			`adr = a;`
296			`stb = 1;`
297			`while(~ack) @(posedge clk);`
298			`d1 = din;`
299			`#2;`
300			`stb=0;`
301			`we = 1'hx;`
302			`sel = 4'hx;`
303			`repeat(delay)`
304			`begin`
305			`@(posedge clk);`
306			`#1;`
307			`end`
308			`we = 0;`
309			`sel = s;`
310
311			`adr = a+4;`
312			`stb = 1;`
313			`@(posedge clk);`
314			`while(~ack) @(posedge clk);`
315			`d2 = din;`
316			`#2;`
317			`stb=0;`
318			`we = 1'hx;`
319			`sel = 4'hx;`
320			`repeat(delay)`
321			`begin`
322			`@(posedge clk);`
323			`#1;`
324			`end`
325			`we = 0;`
326			`sel = s;`
327
328
329			`adr = a+8;`
330			`stb = 1;`
331			`@(posedge clk);`
332			`while(~ack) @(posedge clk);`
333			`d3 = din;`
334			`#2;`
335			`stb=0;`
336			`we = 1'hx;`
337			`sel = 4'hx;`
338			`repeat(delay)`
339			`begin`
340			`@(posedge clk);`
341			`#1;`
342			`end`
343			`we = 0;`
344			`sel = s;`
345
346			`adr = a+12;`
347			`stb = 1;`
348			`@(posedge clk);`
349			`while(~ack) @(posedge clk);`
350			`d4 = din;`
351			`#1;`
352			`stb=0;`
353			`cyc=0;`
354			`we = 1'hx;`
355			`sel = 4'hx;`
356			`adr = 32'hffff_ffff;`
357			`end`
358			`endtask`
359
360
361			`endmodule`