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[/] [vga_lcd/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Blame information for rev 44

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_bench_top.v,v 1.5 2003-03-19 12:20:53 rherveille Exp $
//
//  $Date: 2003-03-19 12:20:53 $
//  $Revision: 1.5 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.4  2002/02/07 05:38:32  rherveille
//               Added wb_ack delay section to testbench
//
//
//
//
//                        
 
`timescale 1ns/10ps
 
module test;
 
reg             clk;
reg             rst;
wire            clk_v;
 
parameter       LINE_FIFO_AWIDTH = 7;
 
wire            int;
wire    [31:0]   wb_addr_o;
wire    [31:0]   wb_data_i;
wire    [31:0]   wb_data_o;
wire    [3:0]    wb_sel_o;
wire            wb_we_o;
wire            wb_stb_o;
wire            wb_cyc_o;
wire            wb_ack_i;
wire            wb_err_i;
wire    [31:0]   wb_addr_i;
wire    [31:0]   wbm_data_i;
wire    [3:0]    wb_sel_i;
wire            wb_we_i;
wire            wb_stb_i;
wire            wb_cyc_i;
wire            wb_ack_o;
wire            wb_err_o;
reg             pclk;
wire            hsync;
wire            vsync;
wire            csync;
wire            blanc;
wire    [7:0]    red;
wire    [7:0]    green;
wire    [7:0]    blue;
 
wire vga_stb_i;
wire clut_stb_i;
 
reg             scen;
 
// Test Bench Variables
integer         wd_cnt;
integer         error_cnt;
 
// Misc Variables
reg     [31:0]   data;
reg     [31:0]   pattern;
reg             int_warn;
 
integer         n;
integer         mode;
integer delay;
 
reg     [7:0]    thsync, thgdel;
reg     [15:0]   thgate, thlen;
reg     [7:0]    tvsync, tvgdel;
reg     [15:0]   tvgate, tvlen;
reg             hpol;
reg             vpol;
reg             cpol;
reg             bpol;
integer         p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   vbase;
reg     [31:0]   cbase;
reg     [31:0]   vbara;
reg     [31:0]   vbarb;
reg     [7:0]    bank;
 
/////////////////////////////////////////////////////////////////////
//
// Defines 
//
 
`define CTRL            32'h0000_0000
`define STAT            32'h0000_0004
`define HTIM            32'h0000_0008
`define VTIM            32'h0000_000c
`define HVLEN           32'h0000_0010
`define VBARA           32'h0000_0014
`define VBARB           32'h0000_0018
 
`define USE_VC          1
 
parameter       PCLK_C = 20;
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
initial
   begin
        $timeformat (-9, 1, " ns", 12);
        $display("\n\n");
        $display("******************************************************");
        $display("* WISHBONE VGA/LCD Controller Simulation started ... *");
        $display("******************************************************");
        $display("\n");
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        scen = 0;
        error_cnt = 0;
        clk = 0;
        pclk = 0;
        rst = 0;
        int_warn=1;
 
        repeat(20)      @(posedge clk);
        rst = 1;
        repeat(20)      @(posedge clk);
 
        // HERE IS WHERE THE TEST CASES GO ...
 
if(0)    // Full Regression Run
   begin
 
   end
else
if(1)   // Quick Regression Run
   begin
        reg_test;
        tim_test;
 
        delay = 2;
        for(delay = 0; delay < 3; delay = delay +1)
        begin
                $display("Setting wishbone slave delay to %d", delay);
                s0.delay = delay;
                pd1_test;
                pd2_test;
        end
 
        //ur_test;
   end
else
   begin
 
        //
        // TEST DEVELOPMENT AREA
        //
$display("\n\n");
$display("*****************************************************");
$display("*** XXX Test                                 ***");
$display("*****************************************************\n");
 
        s0.fill_mem(1);
 
        repeat(10)      @(posedge clk);
 
        vbara = 32'h0000_0000;
        vbarb = 32'h0001_0000;
 
        m0.wb_wr1( `VBARA, 4'hf, vbara );
        m0.wb_wr1( `VBARB, 4'hf, vbarb );
 
        thsync = 0;
        thgdel = 0;
        thgate = 340;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
mode = 2;
 
//for(mode=0;mode<1;mode=mode+1)
for(bank=0;bank<3;bank=bank + 1)
   begin
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'h0,   // VBL
                                1'b0,   // Reserved
                                1'b1,   // CBSWE
                                1'b1,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        $display("Mode: %0d Screen: %0d", mode, bank);
        //repeat(2) @(posedge vsync);
        @(posedge vsync);
 
        // For Each Line
        for(l=0;l<tvgate+1;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                if(bank[0])      vbase = vbarb[31:2];
                else            vbase = vbara[31:2];
                if(bank[0])      cbase = 32'h0000_0c00;
                else            cbase = 32'h0000_0800;
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                   0:    // 24 bit/pixel mode
                   begin
                        pra = pn[31:2] * 3;     // Pixel relative Address
                        paa = pra + vbase;              // Pixel Absolute Address
 
                        // Pixel Data
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = tmp[31:8];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd[23:16] = tmp[7:0];
                                tmp = s0.mem[paa+1];
                                pd[15:0] = tmp[31:16];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa+1];
                                pd[23:8] = tmp[15:0];
                                tmp = s0.mem[paa+2];
                                pd[7:0] = tmp[31:24];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa+2];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   1:   // 8 bit/pixel grayscale mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                             end
                        endcase
                   end
 
                   2:   // 8 bit/pixel Pseudo Color mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[31:24]];
                                pd = tmp[23:0];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[23:16]];
                                pd = tmp[23:0];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[15:8]];
                                pd = tmp[23:0];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[7:0]];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   3:   // 16 bit/pixel mode
                   begin
                        pra = pn[31:1];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp[15:0] = tmp[31:16];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                        endcase
                   end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                   end
 
                @(posedge pclk);
 
           end
   end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
 
   end
 
        repeat(10)      @(posedge clk);
        $finish;
   end
 
/////////////////////////////////////////////////////////////////////
//
// Sync Monitor
//
 
sync_check #(PCLK_C) uceck(
                .pclk(          pclk            ),
                .rst(           rst             ),
                .enable(        scen            ),
                .hsync(         hsync           ),
                .vsync(         vsync           ),
                .csync(         csync           ),
                .blanc(         blanc           ),
                .hpol(          hpol            ),
                .vpol(          vpol            ),
                .cpol(          cpol            ),
                .bpol(          bpol            ),
                .thsync(        thsync          ),
                .thgdel(        thgdel          ),
                .thgate(        thgate          ),
                .thlen(         thlen           ),
                .tvsync(        tvsync          ),
                .tvgdel(        tvgdel          ),
                .tvgate(        tvgate          ),
                .tvlen(         tvlen           ) );
 
/////////////////////////////////////////////////////////////////////
//
// Video Data Monitor
//
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
always @(posedge clk)
        if(wb_cyc_i | wb_cyc_o | wb_ack_i | wb_ack_o | hsync)
          wd_cnt <= #1 0;
        else
          wd_cnt <= #1 wd_cnt + 1;
 
 
always @(wd_cnt)
        if(wd_cnt>9000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
 
always @(posedge int)
  if(int_warn)
   begin
        $display("\n\n*************************************\n");
        $display("WARNING: Recieved Interrupt (%0t)", $time);
        $display("*************************************\n\n\n");
   end
 
always #2.5             clk = ~clk;
always #(PCLK_C/2)      pclk = ~pclk;
 
assign clk_v = clk;
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE DMA IP Core
//
 
 
// Module Prototype
 
`ifdef USE_VC
vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
                .wb_clk_i    ( clk             ),
                .wb_rst_i    ( 1'b0            ),
                .rst_i       ( rst             ),
                .wb_inta_o   ( int             ),
 
                //-- slave signals
                .wbs_adr_i   ( wb_addr_i[11:0] ),
                .wbs_dat_i   ( wb_data_i       ),
                .wbs_dat_o   ( wb_data_o       ),
                .wbs_sel_i   ( wb_sel_i        ),
                .wbs_we_i    ( wb_we_i         ),
                .wbs_stb_i   ( wb_stb_i        ),
                .wbs_cyc_i   ( wb_cyc_i        ),
                .wbs_ack_o   ( wb_ack_o        ),
                .wbs_err_o   ( wb_err_o        ),
 
                //-- master signals
                .wbm_adr_o   ( wb_addr_o[31:0] ),
                .wbm_dat_i   ( wbm_data_i      ),
                .wbm_sel_o   ( wb_sel_o        ),
                .wbm_we_o    ( wb_we_o         ),
                .wbm_stb_o   ( wb_stb_o        ),
                .wbm_cyc_o   ( wb_cyc_o        ),
                .wbm_cti_o   ( ),
                .wbm_bte_o   ( ),
                .wbm_ack_i   ( wb_ack_i        ),
                .wbm_err_i   ( wb_err_i        ),
 
                //-- VGA signals
                .clk_p_i     ( pclk            ),
                .hsync_pad_o ( hsync           ),
                .vsync_pad_o ( vsync           ),
                .csync_pad_o ( csync           ),
                .blank_pad_o ( blanc           ),
                .r_pad_o     ( red             ),
                .g_pad_o     ( green           ),
                .b_pad_o     ( blue            )
        );
 
`else
 
VGA u0 (        .CLK_I( clk_v           ),
                .RST_I(         ~rst            ),
                .NRESET(        rst             ),
                .INTA_O(        int             ),
 
                //-- slave signals
                .ADR_I(         wb_addr_i[4:2]  ),
                .SDAT_I(        wb_data_i       ),
                .SDAT_O(        wb_data_o       ),
                .SEL_I(         wb_sel_i        ),
                .WE_I(          wb_we_i         ),
                .STB_I(         wb_stb_i        ),
                .CYC_I(         wb_cyc_i        ),
                .ACK_O(         wb_ack_o        ),
                .ERR_O(         wb_err_o        ),
 
                //-- master signals
                .ADR_O(         wb_addr_o[31:2] ),
                .MDAT_I(        wbm_data_i      ),
                .SEL_O(         wb_sel_o        ),
                .WE_O(          wb_we_o         ),
                .STB_O(         wb_stb_o        ),
                .CYC_O(         wb_cyc_o        ),
                .CAB_O(                         ),
                .ACK_I(         wb_ack_i        ),
                .ERR_I(         wb_err_i        ),
 
                //-- VGA signals
                .PCLK(          pclk            ),
                .HSYNC(         hsync           ),
                .VSYNC(         vsync           ),
                .CSYNC(         csync           ),
                .BLANK(         blanc           ),
                .R(             red             ),
                .G(             green           ),
                .B(             blue            )
        );
 
`endif
 
wb_mast m0(     .clk(           clk             ),
                .rst(           rst             ),
                .adr(           wb_addr_i       ),
                .din(           wb_data_o       ),
                .dout(          wb_data_i       ),
                .cyc(           wb_cyc_i        ),
                .stb(           wb_stb_i        ),
                .sel(           wb_sel_i        ),
                .we(            wb_we_i         ),
                .ack(           wb_ack_o        ),
                .err(           wb_err_o        ),
                .rty(           1'b0            )
                );
 
wb_slv #(24) s0(.clk(           clk             ),
                .rst(           rst             ),
                .adr(           {1'b0, wb_addr_o[30:0]}  ),
                .din(           32'h0           ),
                .dout(          wbm_data_i      ),
                .cyc(           wb_cyc_o        ),
                .stb(           wb_stb_o        ),
                .sel(           wb_sel_o        ),
                .we(            wb_we_o         ),
                .ack(           wb_ack_i        ),
                .err(           wb_err_i        ),
                .rty(                           )
                );
 
`include "tests.v"
 
endmodule

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Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Blame information for rev 44

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	44	rherveille	`// $Id: test_bench_top.v,v 1.5 2003-03-19 12:20:53 rherveille Exp $`
41	16	rudi	`//`
42	44	rherveille	`// $Date: 2003-03-19 12:20:53 $`
43			`// $Revision: 1.5 $`
44	24	rherveille	`// $Author: rherveille $`
45	16	rudi	`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	44	rherveille	`// Revision 1.4 2002/02/07 05:38:32 rherveille`
51			`// Added wb_ack delay section to testbench`
52	16	rudi	`//`
53			`//`
54			`//`
55	44	rherveille	`//`
56	16	rudi	`//`
57
58	44	rherveille	`timescale 1ns/10ps
59	16	rudi
60			`module test;`
61
62			`reg clk;`
63			`reg rst;`
64			`wire clk_v;`
65
66			`parameter LINE_FIFO_AWIDTH = 7;`
67
68			`wire int;`
69			`wire [31:0] wb_addr_o;`
70			`wire [31:0] wb_data_i;`
71			`wire [31:0] wb_data_o;`
72			`wire [3:0] wb_sel_o;`
73			`wire wb_we_o;`
74			`wire wb_stb_o;`
75			`wire wb_cyc_o;`
76			`wire wb_ack_i;`
77			`wire wb_err_i;`
78			`wire [31:0] wb_addr_i;`
79			`wire [31:0] wbm_data_i;`
80			`wire [3:0] wb_sel_i;`
81			`wire wb_we_i;`
82			`wire wb_stb_i;`
83			`wire wb_cyc_i;`
84			`wire wb_ack_o;`
85			`wire wb_err_o;`
86			`reg pclk;`
87			`wire hsync;`
88			`wire vsync;`
89			`wire csync;`
90			`wire blanc;`
91			`wire [7:0] red;`
92			`wire [7:0] green;`
93			`wire [7:0] blue;`
94
95	24	rherveille	`wire vga_stb_i;`
96			`wire clut_stb_i;`
97	16	rudi
98			`reg scen;`
99
100			`// Test Bench Variables`
101			`integer wd_cnt;`
102			`integer error_cnt;`
103
104			`// Misc Variables`
105			`reg [31:0] data;`
106			`reg [31:0] pattern;`
107			`reg int_warn;`
108
109			`integer n;`
110			`integer mode;`
111	29	rherveille	`integer delay;`
112	16	rudi
113			`reg [7:0] thsync, thgdel;`
114			`reg [15:0] thgate, thlen;`
115			`reg [7:0] tvsync, tvgdel;`
116			`reg [15:0] tvgate, tvlen;`
117			`reg hpol;`
118			`reg vpol;`
119			`reg cpol;`
120			`reg bpol;`
121			`integer p, l;`
122			`reg [31:0] pn;`
123			`reg [31:0] pra, paa, tmp;`
124			`reg [23:0] pd;`
125			`reg [1:0] cd;`
126			`reg pc;`
127			`reg [31:0] vbase;`
128			`reg [31:0] cbase;`
129			`reg [31:0] vbara;`
130			`reg [31:0] vbarb;`
131			`reg [7:0] bank;`
132
133			`/////////////////////////////////////////////////////////////////////`
134			`//`
135			`// Defines`
136			`//`
137
138			`define CTRL 32'h0000_0000
139			`define STAT 32'h0000_0004
140			`define HTIM 32'h0000_0008
141			`define VTIM 32'h0000_000c
142			`define HVLEN 32'h0000_0010
143			`define VBARA 32'h0000_0014
144			`define VBARB 32'h0000_0018
145
146			`define USE_VC 1
147
148	44	rherveille	`parameter PCLK_C = 20;`
149	24	rherveille
150	16	rudi	`/////////////////////////////////////////////////////////////////////`
151			`//`
152			`// Simulation Initialization and Start up Section`
153			`//`
154
155			`initial`
156			`begin`
157			`$timeformat (-9, 1, " ns", 12);`
158			`$display("\n\n");`
159			`$display("******************************************************");`
160			`$display("* WISHBONE VGA/LCD Controller Simulation started ... *");`
161			`$display("******************************************************");`
162			`$display("\n");`
163			`ifdef WAVES
164			`$shm_open("waves");`
165			`$shm_probe("AS",test,"AS");`
166			`$display("INFO: Signal dump enabled ...\n\n");`
167			`endif
168			`scen = 0;`
169			`error_cnt = 0;`
170			`clk = 0;`
171			`pclk = 0;`
172			`rst = 0;`
173			`int_warn=1;`
174
175			`repeat(20) @(posedge clk);`
176			`rst = 1;`
177			`repeat(20) @(posedge clk);`
178
179			`// HERE IS WHERE THE TEST CASES GO ...`
180
181			`if(0) // Full Regression Run`
182			`begin`
183
184			`end`
185			`else`
186			`if(1) // Quick Regression Run`
187			`begin`
188	44	rherveille	`reg_test;`
189			`tim_test;`
190	29	rherveille
191			`delay = 2;`
192			`for(delay = 0; delay < 3; delay = delay +1)`
193			`begin`
194			`$display("Setting wishbone slave delay to %d", delay);`
195			`s0.delay = delay;`
196	44	rherveille	`pd1_test;`
197	29	rherveille	`pd2_test;`
198			`end`
199
200	24	rherveille	`//ur_test;`
201	16	rudi	`end`
202			`else`
203			`begin`
204
205			`//`
206			`// TEST DEVELOPMENT AREA`
207			`//`
208			`$display("\n\n");`
209			`$display("*****************************************************");`
210			`$display("* XXX Test *");`
211			`$display("*****************************************************\n");`
212
213			`s0.fill_mem(1);`
214
215			`repeat(10) @(posedge clk);`
216
217			`vbara = 32'h0000_0000;`
218			`vbarb = 32'h0001_0000;`
219
220			m0.wb_wr1( `VBARA, 4'hf, vbara );
221			m0.wb_wr1( `VBARB, 4'hf, vbarb );
222
223			`thsync = 0;`
224			`thgdel = 0;`
225			`thgate = 340;`
226			`thlen = 345;`
227
228			`tvsync = 0;`
229			`tvgdel = 0;`
230			`tvgate = 240;`
231			`tvlen = 245;`
232
233			`/*`
234			`thsync = 0;`
235			`thgdel = 0;`
236			`thgate = 63;`
237			`thlen = 70;`
238
239			`tvsync = 0;`
240			`tvgdel = 0;`
241			`tvgate = 32;`
242			`tvlen = 36;`
243			`*/`
244
245			`hpol = 0;`
246			`vpol = 0;`
247			`cpol = 0;`
248			`bpol = 0;`
249
250			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
251			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
252			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
253
254			`mode = 2;`
255
256			`//for(mode=0;mode<1;mode=mode+1)`
257			`for(bank=0;bank<3;bank=bank + 1)`
258			`begin`
259			`case(mode)`
260			`0:`
261			`begin`
262			`cd = 2'h2;`
263			`pc = 1'b0;`
264			`end`
265			`1:`
266			`begin`
267			`cd = 2'h0;`
268			`pc = 1'b0;`
269			`end`
270			`2:`
271			`begin`
272			`cd = 2'h0;`
273			`pc = 1'b1;`
274			`end`
275			`3:`
276			`begin`
277			`cd = 2'h1;`
278			`pc = 1'b0;`
279			`end`
280			`endcase`
281
282			m0.wb_wr1( `CTRL, 4'hf, {
283			`16'h0, // Reserved`
284			`bpol, cpol,`
285			`vpol, hpol,`
286			`pc, // 1'b0, // PC`
287			`cd, // 2'h2, // CD`
288			`2'h0, // VBL`
289			`1'b0, // Reserved`
290			`1'b1, // CBSWE`
291			`1'b1, // VBSWE`
292			`1'b0, // BSIE`
293			`1'b0, // HIE`
294			`1'b0, // VIE`
295			`1'b1 // Video Enable`
296			`});`
297
298			`$display("Mode: %0d Screen: %0d", mode, bank);`
299			`//repeat(2) @(posedge vsync);`
300			`@(posedge vsync);`
301
302			`// For Each Line`
303			`for(l=0;l<tvgate+1;l=l+1)`
304			`// For each Pixel`
305			`for(p=0;p<thgate+1;p=p+1)`
306			`begin`
307			`while(blanc) @(posedge pclk); // wait for viewable data`
308
309			`//$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);`
310
311			`if(bank[0]) vbase = vbarb[31:2];`
312			`else vbase = vbara[31:2];`
313	24	rherveille	`if(bank[0]) cbase = 32'h0000_0c00;`
314			`else cbase = 32'h0000_0800;`
315	16	rudi
316			`// Depending on Mode, determine pixel data`
317			`// pixel number = line * (thgate + 1) + p`
318			`pn = l * (thgate + 1) + p;`
319
320			`case(mode)`
321			`0: // 24 bit/pixel mode`
322			`begin`
323			`pra = pn[31:2] * 3; // Pixel relative Address`
324			`paa = pra + vbase; // Pixel Absolute Address`
325
326			`// Pixel Data`
327			`case(pn[1:0])`
328			`0:`
329			`begin`
330			`tmp = s0.mem[paa];`
331			`pd = tmp[31:8];`
332			`end`
333			`1:`
334			`begin`
335			`tmp = s0.mem[paa];`
336			`pd[23:16] = tmp[7:0];`
337			`tmp = s0.mem[paa+1];`
338			`pd[15:0] = tmp[31:16];`
339			`end`
340			`2:`
341			`begin`
342			`tmp = s0.mem[paa+1];`
343			`pd[23:8] = tmp[15:0];`
344			`tmp = s0.mem[paa+2];`
345			`pd[7:0] = tmp[31:24];`
346			`end`
347			`3:`
348			`begin`
349			`tmp = s0.mem[paa+2];`
350			`pd = tmp[23:0];`
351			`end`
352			`endcase`
353			`end`
354
355			`1: // 8 bit/pixel grayscale mode`
356			`begin`
357			`pra = pn[31:2]; // Pixel relative Address`
358			`paa = pra + vbase; // Pixel Absolute Address`
359			`case(pn[1:0])`
360			`0:`
361			`begin`
362			`tmp = s0.mem[paa];`
363			`pd = { tmp[31:24], tmp[31:24], tmp[31:24] };`
364			`end`
365			`1:`
366			`begin`
367			`tmp = s0.mem[paa];`
368			`pd = { tmp[23:16], tmp[23:16], tmp[23:16] };`
369			`end`
370			`2:`
371			`begin`
372			`tmp = s0.mem[paa];`
373			`pd = { tmp[15:8], tmp[15:8], tmp[15:8] };`
374			`end`
375			`3:`
376			`begin`
377			`tmp = s0.mem[paa];`
378			`pd = { tmp[7:0], tmp[7:0], tmp[7:0] };`
379			`end`
380			`endcase`
381			`end`
382
383			`2: // 8 bit/pixel Pseudo Color mode`
384			`begin`
385			`pra = pn[31:2]; // Pixel relative Address`
386			`paa = pra + vbase; // Pixel Absolute Address`
387			`case(pn[1:0])`
388			`0:`
389			`begin`
390			`tmp = s0.mem[paa];`
391			`tmp = s0.mem[cbase[31:2] + tmp[31:24]];`
392			`pd = tmp[23:0];`
393			`end`
394			`1:`
395			`begin`
396			`tmp = s0.mem[paa];`
397			`tmp = s0.mem[cbase[31:2] + tmp[23:16]];`
398			`pd = tmp[23:0];`
399			`end`
400			`2:`
401			`begin`
402			`tmp = s0.mem[paa];`
403			`tmp = s0.mem[cbase[31:2] + tmp[15:8]];`
404			`pd = tmp[23:0];`
405			`end`
406			`3:`
407			`begin`
408			`tmp = s0.mem[paa];`
409			`tmp = s0.mem[cbase[31:2] + tmp[7:0]];`
410			`pd = tmp[23:0];`
411			`end`
412			`endcase`
413			`end`
414
415			`3: // 16 bit/pixel mode`
416			`begin`
417			`pra = pn[31:1]; // Pixel relative Address`
418			`paa = pra + vbase; // Pixel Absolute Address`
419			`case(pn[0])`
420			`0:`
421			`begin`
422			`tmp = s0.mem[paa];`
423			`tmp[15:0] = tmp[31:16];`
424			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
425			`end`
426			`1:`
427			`begin`
428			`tmp = s0.mem[paa];`
429			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
430			`end`
431			`endcase`
432			`end`
433
434			`endcase`
435
436			`if(pd !== {red, green, blue} )`
437			`begin`
438			`$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",`
439			`pd, red, green, blue);`
440			`$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);`
441			`error_cnt = error_cnt + 1;`
442			`end`
443
444			`@(posedge pclk);`
445
446			`end`
447			`end`
448
449			`show_errors;`
450			`$display("*****************************************************");`
451			`$display("* Test DONE ... *");`
452			`$display("*****************************************************\n\n");`
453
454
455			`end`
456
457			`repeat(10) @(posedge clk);`
458			`$finish;`
459			`end`
460
461			`/////////////////////////////////////////////////////////////////////`
462			`//`
463			`// Sync Monitor`
464			`//`
465
466			`sync_check #(PCLK_C) uceck(`
467			`.pclk( pclk ),`
468			`.rst( rst ),`
469			`.enable( scen ),`
470			`.hsync( hsync ),`
471			`.vsync( vsync ),`
472			`.csync( csync ),`
473			`.blanc( blanc ),`
474			`.hpol( hpol ),`
475			`.vpol( vpol ),`
476			`.cpol( cpol ),`
477			`.bpol( bpol ),`
478			`.thsync( thsync ),`
479			`.thgdel( thgdel ),`
480			`.thgate( thgate ),`
481			`.thlen( thlen ),`
482			`.tvsync( tvsync ),`
483			`.tvgdel( tvgdel ),`
484			`.tvgate( tvgate ),`
485			`.tvlen( tvlen ) );`
486
487			`/////////////////////////////////////////////////////////////////////`
488			`//`
489			`// Video Data Monitor`
490			`//`
491
492			`/////////////////////////////////////////////////////////////////////`
493			`//`
494			`// Watchdog Counter`
495			`//`
496
497			`always @(posedge clk)`
498	44	rherveille	`if(wb_cyc_i \| wb_cyc_o \| wb_ack_i \| wb_ack_o \| hsync)`
499			`wd_cnt <= #1 0;`
500			`else`
501			`wd_cnt <= #1 wd_cnt + 1;`
502	16	rudi
503
504			`always @(wd_cnt)`
505			`if(wd_cnt>9000)`
506			`begin`
507			`$display("\n\n*************************************\n");`
508			`$display("ERROR: Watch Dog Counter Expired\n");`
509			`$display("*************************************\n\n\n");`
510			`$finish;`
511			`end`
512
513
514			`always @(posedge int)`
515			`if(int_warn)`
516			`begin`
517			`$display("\n\n*************************************\n");`
518			`$display("WARNING: Recieved Interrupt (%0t)", $time);`
519			`$display("*************************************\n\n\n");`
520			`end`
521
522			`always #2.5 clk = ~clk;`
523			`always #(PCLK_C/2) pclk = ~pclk;`
524
525			`assign clk_v = clk;`
526
527			`/////////////////////////////////////////////////////////////////////`
528			`//`
529			`// WISHBONE DMA IP Core`
530			`//`
531
532
533			`// Module Prototype`
534
535			`ifdef USE_VC
536	29	rherveille	`vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 (`
537	44	rherveille	`.wb_clk_i ( clk ),`
538			`.wb_rst_i ( 1'b0 ),`
539			`.rst_i ( rst ),`
540			`.wb_inta_o ( int ),`
541	16	rudi
542			`//-- slave signals`
543	44	rherveille	`.wbs_adr_i ( wb_addr_i[11:0] ),`
544			`.wbs_dat_i ( wb_data_i ),`
545			`.wbs_dat_o ( wb_data_o ),`
546			`.wbs_sel_i ( wb_sel_i ),`
547			`.wbs_we_i ( wb_we_i ),`
548			`.wbs_stb_i ( wb_stb_i ),`
549			`.wbs_cyc_i ( wb_cyc_i ),`
550			`.wbs_ack_o ( wb_ack_o ),`
551			`.wbs_err_o ( wb_err_o ),`
552	16	rudi
553			`//-- master signals`
554	44	rherveille	`.wbm_adr_o ( wb_addr_o[31:0] ),`
555			`.wbm_dat_i ( wbm_data_i ),`
556			`.wbm_sel_o ( wb_sel_o ),`
557			`.wbm_we_o ( wb_we_o ),`
558			`.wbm_stb_o ( wb_stb_o ),`
559			`.wbm_cyc_o ( wb_cyc_o ),`
560			`.wbm_cti_o ( ),`
561			`.wbm_bte_o ( ),`
562			`.wbm_ack_i ( wb_ack_i ),`
563			`.wbm_err_i ( wb_err_i ),`
564	16	rudi
565			`//-- VGA signals`
566	44	rherveille	`.clk_p_i ( pclk ),`
567			`.hsync_pad_o ( hsync ),`
568			`.vsync_pad_o ( vsync ),`
569			`.csync_pad_o ( csync ),`
570			`.blank_pad_o ( blanc ),`
571			`.r_pad_o ( red ),`
572			`.g_pad_o ( green ),`
573			`.b_pad_o ( blue )`
574	16	rudi	`);`
575
576			`else
577
578			`VGA u0 ( .CLK_I( clk_v ),`
579			`.RST_I( ~rst ),`
580			`.NRESET( rst ),`
581			`.INTA_O( int ),`
582
583			`//-- slave signals`
584			`.ADR_I( wb_addr_i[4:2] ),`
585			`.SDAT_I( wb_data_i ),`
586			`.SDAT_O( wb_data_o ),`
587			`.SEL_I( wb_sel_i ),`
588			`.WE_I( wb_we_i ),`
589			`.STB_I( wb_stb_i ),`
590			`.CYC_I( wb_cyc_i ),`
591			`.ACK_O( wb_ack_o ),`
592			`.ERR_O( wb_err_o ),`
593
594			`//-- master signals`
595			`.ADR_O( wb_addr_o[31:2] ),`
596			`.MDAT_I( wbm_data_i ),`
597			`.SEL_O( wb_sel_o ),`
598			`.WE_O( wb_we_o ),`
599			`.STB_O( wb_stb_o ),`
600			`.CYC_O( wb_cyc_o ),`
601			`.CAB_O( ),`
602			`.ACK_I( wb_ack_i ),`
603			`.ERR_I( wb_err_i ),`
604
605			`//-- VGA signals`
606			`.PCLK( pclk ),`
607			`.HSYNC( hsync ),`
608			`.VSYNC( vsync ),`
609			`.CSYNC( csync ),`
610			`.BLANK( blanc ),`
611			`.R( red ),`
612			`.G( green ),`
613			`.B( blue )`
614			`);`
615
616			`endif
617
618			`wb_mast m0( .clk( clk ),`
619			`.rst( rst ),`
620			`.adr( wb_addr_i ),`
621			`.din( wb_data_o ),`
622			`.dout( wb_data_i ),`
623			`.cyc( wb_cyc_i ),`
624			`.stb( wb_stb_i ),`
625			`.sel( wb_sel_i ),`
626			`.we( wb_we_i ),`
627			`.ack( wb_ack_o ),`
628			`.err( wb_err_o ),`
629			`.rty( 1'b0 )`
630			`);`
631
632			`wb_slv #(24) s0(.clk( clk ),`
633			`.rst( rst ),`
634			`.adr( {1'b0, wb_addr_o[30:0]} ),`
635			`.din( 32'h0 ),`
636			`.dout( wbm_data_i ),`
637			`.cyc( wb_cyc_o ),`
638			`.stb( wb_stb_o ),`
639			`.sel( wb_sel_o ),`
640			`.we( wb_we_o ),`
641			`.ack( wb_ack_i ),`
642			`.err( wb_err_i ),`
643			`.rty( )`
644			`);`
645
646			`include "tests.v"
647
648			`endmodule`