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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Top Level Test Bench                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: test_bench_top.v,v 1.8 2003-05-07 14:39:19 rherveille Exp $
//
//  $Date: 2003-05-07 14:39:19 $
//  $Revision: 1.8 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.7  2003/05/07 09:45:28  rherveille
//               Numerous updates and added checks
//
//               Revision 1.6  2003/03/19 17:22:19  rherveille
//               Added WISHBONE revB.3 sanity checks
//
//               Revision 1.5  2003/03/19 12:20:53  rherveille
//               Changed timing section in VGA core, changed testbench accordingly.
//               Fixed bug in 'timing check' test.
//
//               Revision 1.4  2002/02/07 05:38:32  rherveille
//               Added wb_ack delay section to testbench
//
//
//
//
//
 
`timescale 1ns/10ps
 
module test;
 
reg             clk;
reg             rst;
 
parameter       LINE_FIFO_AWIDTH = 7;
 
wire            int;
wire    [31:0]   wb_addr_o;
wire    [31:0]   wb_data_i;
wire    [31:0]   wb_data_o;
wire    [3:0]    wb_sel_o;
wire            wb_we_o;
wire            wb_stb_o;
wire            wb_cyc_o;
wire    [2:0]    wb_cti_o;
wire    [1:0]    wb_bte_o;
wire            wb_ack_i;
wire            wb_err_i;
wire    [31:0]   wb_addr_i;
wire    [31:0]   wbm_data_i;
wire    [3:0]    wb_sel_i;
wire            wb_we_i;
wire            wb_stb_i;
wire            wb_cyc_i;
wire            wb_ack_o;
wire            wb_rty_o;
wire            wb_err_o;
reg             pclk_i;
wire            pclk;
wire            hsync;
wire            vsync;
wire            csync;
wire            blanc;
wire    [7:0]    red;
wire    [7:0]    green;
wire    [7:0]    blue;
wire            dvi_pclk_p_o;
wire            dvi_pclk_m_o;
wire            dvi_hsync_o;
wire            dvi_vsync_o;
wire            dvi_de_o;
wire    [11:0]   dvi_d_o;
 
 
wire vga_stb_i;
wire clut_stb_i;
 
reg             scen;
 
// Test Bench Variables
integer         wd_cnt;
integer         error_cnt;
 
// Misc Variables
reg     [31:0]   data;
reg     [31:0]   pattern;
reg             int_warn;
 
integer         n;
integer         mode;
 
reg     [7:0]    thsync, thgdel;
reg     [15:0]   thgate, thlen;
reg     [7:0]    tvsync, tvgdel;
reg     [15:0]   tvgate, tvlen;
reg             hpol;
reg             vpol;
reg             cpol;
reg             bpol;
integer         p, l;
reg     [31:0]   pn;
reg     [31:0]   pra, paa, tmp;
reg     [23:0]   pd;
reg     [1:0]    cd;
reg             pc;
reg     [31:0]   vbase;
reg     [31:0]   cbase;
reg     [31:0]   vbara;
reg     [31:0]   vbarb;
reg     [7:0]    bank;
 
/////////////////////////////////////////////////////////////////////
//
// Defines
//
 
`define CTRL            32'h0000_0000
`define STAT            32'h0000_0004
`define HTIM            32'h0000_0008
`define VTIM            32'h0000_000c
`define HVLEN           32'h0000_0010
`define VBARA           32'h0000_0014
`define VBARB           32'h0000_0018
 
`define USE_VC          1
 
parameter       PCLK_C = 20;
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
initial
   begin
        $timeformat (-9, 1, " ns", 12);
        $display("\n\n");
        $display("******************************************************");
        $display("* WISHBONE VGA/LCD Controller Simulation started ... *");
        $display("******************************************************");
        $display("\n");
`ifdef WAVES
        $shm_open("waves");
        $shm_probe("AS",test,"AS");
        $display("INFO: Signal dump enabled ...\n\n");
`endif
        scen = 0;
        error_cnt = 0;
        clk = 0;
        pclk_i = 0;
        rst = 0;
        int_warn=1;
 
        repeat(20)      @(posedge clk);
        rst = 1;
        repeat(20)      @(posedge clk);
 
        // HERE IS WHERE THE TEST CASES GO ...
 
if(0)    // Full Regression Run
   begin
 
   end
else
if(1)   // Quick Regression Run
   begin
//      reg_test;
//      tim_test;
 
//      pd1_test;
//      pd2_test;
 
`ifdef VGA_12BIT_DVI
        dvi_pd_test;
`endif
 
//      ur_test;
   end
else
   begin
 
        //
        // TEST DEVELOPMENT AREA
        //
$display("\n\n");
$display("*****************************************************");
$display("*** XXX Test                                 ***");
$display("*****************************************************\n");
 
        s0.fill_mem(1);
 
        repeat(10) @(posedge clk);
 
        vbara = 32'h0000_0000;
        vbarb = 32'h0001_0000;
 
        m0.wb_wr1( `VBARA, 4'hf, vbara );
        m0.wb_wr1( `VBARB, 4'hf, vbarb );
 
        thsync = 0;
        thgdel = 0;
        thgate = 340;
        thlen = 345;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 240;
        tvlen = 245;
 
/*
        thsync = 0;
        thgdel = 0;
        thgate = 63;
        thlen = 70;
 
        tvsync = 0;
        tvgdel = 0;
        tvgate = 32;
        tvlen = 36;
*/
 
        hpol = 0;
        vpol = 0;
        cpol = 0;
        bpol = 0;
 
        m0.wb_wr1( `HTIM,  4'hf, {thsync, thgdel, thgate} );
        m0.wb_wr1( `VTIM,  4'hf, {tvsync, tvgdel, tvgate} );
        m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
 
mode = 2;
 
//for(mode=0;mode<1;mode=mode+1)
for(bank=0;bank<3;bank=bank + 1)
   begin
        case(mode)
           0:
             begin
                cd = 2'h2;
                pc = 1'b0;
             end
           1:
             begin
                cd = 2'h0;
                pc = 1'b0;
             end
           2:
             begin
                cd = 2'h0;
                pc = 1'b1;
             end
           3:
             begin
                cd = 2'h1;
                pc = 1'b0;
             end
        endcase
 
        m0.wb_wr1( `CTRL,  4'hf, {
                                16'h0,  // Reserved
                                bpol, cpol,
                                vpol, hpol,
                                pc,     // 1'b0,        // PC
                                cd,     // 2'h2,        // CD
                                2'h0,   // VBL
                                1'b0,   // Reserved
                                1'b1,   // CBSWE
                                1'b1,   // VBSWE
                                1'b0,   // BSIE
                                1'b0,   // HIE
                                1'b0,   // VIE
                                1'b1    // Video Enable
                                });
 
        $display("Mode: %0d Screen: %0d", mode, bank);
        //repeat(2) @(posedge vsync);
        @(posedge vsync);
 
        // For Each Line
        for(l=0;l<tvgate+1;l=l+1)
        // For each Pixel
        for(p=0;p<thgate+1;p=p+1)
           begin
                while(blanc)    @(posedge pclk);  // wait for viewable data
 
                //$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
 
                if(bank[0])      vbase = vbarb[31:2];
                else            vbase = vbara[31:2];
                if(bank[0])      cbase = 32'h0000_0c00;
                else            cbase = 32'h0000_0800;
 
                // Depending on Mode, determine pixel data
                // pixel number = line * (thgate + 1) + p
                pn = l * (thgate + 1) + p;
 
                case(mode)
                   0:    // 24 bit/pixel mode
                   begin
                        pra = pn[31:2] * 3;     // Pixel relative Address
                        paa = pra + vbase;              // Pixel Absolute Address
 
                        // Pixel Data
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = tmp[31:8];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd[23:16] = tmp[7:0];
                                tmp = s0.mem[paa+1];
                                pd[15:0] = tmp[31:16];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa+1];
                                pd[23:8] = tmp[15:0];
                                tmp = s0.mem[paa+2];
                                pd[7:0] = tmp[31:24];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa+2];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   1:   // 8 bit/pixel grayscale mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
                             end
                        endcase
                   end
 
                   2:   // 8 bit/pixel Pseudo Color mode
                   begin
                        pra = pn[31:2];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[1:0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[31:24]];
                                pd = tmp[23:0];
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[23:16]];
                                pd = tmp[23:0];
                             end
                           2:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[15:8]];
                                pd = tmp[23:0];
                             end
                           3:
                             begin
                                tmp = s0.mem[paa];
                                tmp = s0.mem[cbase[31:2] + tmp[7:0]];
                                pd = tmp[23:0];
                             end
                        endcase
                   end
 
                   3:   // 16 bit/pixel mode
                   begin
                        pra = pn[31:1];         // Pixel relative Address
                        paa = pra + vbase;      // Pixel Absolute Address
                        case(pn[0])
                           0:
                             begin
                                tmp = s0.mem[paa];
                                tmp[15:0] = tmp[31:16];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                           1:
                             begin
                                tmp = s0.mem[paa];
                                pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
                             end
                        endcase
                   end
 
                endcase
 
                if(pd !== {red, green, blue} )
                   begin
                        $display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
                                pd, red, green, blue);
                        $display("       pixel=%0d, line=%0d, (%0t)",p,l,$time);
                        error_cnt = error_cnt + 1;
                   end
 
                @(posedge pclk);
 
           end
   end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
 
   end
 
        repeat(10)      @(posedge clk);
        $finish;
   end
 
/////////////////////////////////////////////////////////////////////
//
// Sync Monitor
//
 
`ifdef VGA_12BIT_DVI
sync_check #(PCLK_C*2) ucheck(
`else
sync_check #(PCLK_C) ucheck(
`endif
                .pclk(          pclk            ),
                .rst(           rst             ),
                .enable(        scen            ),
                .hsync(         hsync           ),
                .vsync(         vsync           ),
                .csync(         csync           ),
                .blanc(         blanc           ),
                .hpol(          hpol            ),
                .vpol(          vpol            ),
                .cpol(          cpol            ),
                .bpol(          bpol            ),
                .thsync(        thsync          ),
                .thgdel(        thgdel          ),
                .thgate(        thgate          ),
                .thlen(         thlen           ),
                .tvsync(        tvsync          ),
                .tvgdel(        tvgdel          ),
                .tvgate(        tvgate          ),
                .tvlen(         tvlen           ) );
 
/////////////////////////////////////////////////////////////////////
//
// Video Data Monitor
//
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE revB.3 checker
//
 
wb_b3_check u_wb_check (
        .clk_i ( clk      ),
        .cyc_i ( wb_cyc_o ),
        .stb_i ( wb_stb_o ),
        .cti_i ( wb_cti_o ),
        .bte_i ( wb_bte_o ),
        .we_i  ( wb_we_o  ),
        .ack_i ( wb_ack_i ),
        .err_i ( wb_err_i ),
        .rty_i ( 1'b0     ) );
 
 
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
 
always @(posedge clk)
        if(wb_cyc_i | wb_cyc_o | wb_ack_i | wb_ack_o | hsync)
          wd_cnt <= #1 0;
        else
          wd_cnt <= #1 wd_cnt + 1;
 
 
always @(wd_cnt)
        if(wd_cnt>9000)
           begin
                $display("\n\n*************************************\n");
                $display("ERROR: Watch Dog Counter Expired\n");
                $display("*************************************\n\n\n");
                $finish;
           end
 
 
always @(posedge int)
  if(int_warn)
   begin
        $display("\n\n*************************************\n");
        $display("WARNING: Recieved Interrupt (%0t)", $time);
        $display("*************************************\n\n\n");
   end
 
always #2.5 clk = ~clk;
always #(PCLK_C/2) pclk_i = ~pclk_i;
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE VGA/LCD IP Core
//
 
 
// Module Prototype
 
vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
                .wb_clk_i     ( clk             ),
                .wb_rst_i     ( 1'b0            ),
                .rst_i        ( rst             ),
                .wb_inta_o    ( int             ),
 
                //-- slave signals
                .wbs_adr_i    ( wb_addr_i[11:0] ),
                .wbs_dat_i    ( wb_data_i       ),
                .wbs_dat_o    ( wb_data_o       ),
                .wbs_sel_i    ( wb_sel_i        ),
                .wbs_we_i     ( wb_we_i         ),
                .wbs_stb_i    ( wb_stb_i        ),
                .wbs_cyc_i    ( wb_cyc_i        ),
                .wbs_ack_o    ( wb_ack_o        ),
                .wbs_rty_o    ( wb_rty_o        ),
                .wbs_err_o    ( wb_err_o        ),
 
                //-- master signals
                .wbm_adr_o    ( wb_addr_o[31:0] ),
                .wbm_dat_i    ( wbm_data_i      ),
                .wbm_sel_o    ( wb_sel_o        ),
                .wbm_we_o     ( wb_we_o         ),
                .wbm_stb_o    ( wb_stb_o        ),
                .wbm_cyc_o    ( wb_cyc_o        ),
                .wbm_cti_o    ( wb_cti_o        ),
                .wbm_bte_o    ( wb_bte_o        ),
                .wbm_ack_i    ( wb_ack_i        ),
                .wbm_err_i    ( wb_err_i        ),
 
                //-- VGA signals
                .clk_p_i      ( pclk_i          ),
        `ifdef VGA_12BIT_DVI
                .dvi_pclk_p_o ( dvi_pclk_p_o    ),
                .dvi_pclk_m_o ( dvi_pclk_m_o    ),
                .dvi_hsync_o  ( dvi_hsync_o     ),
                .dvi_vsync_o  ( dvi_vsync_o     ),
                .dvi_de_o     ( dvi_de_o        ),
                .dvi_d_o      ( dvi_d_o         ),
        `endif
                .clk_p_o      ( pclk            ),
                .hsync_pad_o  ( hsync           ),
                .vsync_pad_o  ( vsync           ),
                .csync_pad_o  ( csync           ),
                .blank_pad_o  ( blanc           ),
                .r_pad_o      ( red             ),
                .g_pad_o      ( green           ),
                .b_pad_o      ( blue            )
        );
 
wb_mast m0(     .clk(           clk             ),
                .rst(           rst             ),
                .adr(           wb_addr_i       ),
                .din(           wb_data_o       ),
                .dout(          wb_data_i       ),
                .cyc(           wb_cyc_i        ),
                .stb(           wb_stb_i        ),
                .sel(           wb_sel_i        ),
                .we(            wb_we_i         ),
                .ack(           wb_ack_o        ),
                .err(           wb_err_o        ),
                .rty(           1'b0            )
                );
 
wb_slv #(24) s0(.clk(           clk             ),
                .rst(           rst             ),
                .adr(           {1'b0, wb_addr_o[30:0]}  ),
                .din(           32'h0           ),
                .dout(          wbm_data_i      ),
                .cyc(           wb_cyc_o        ),
                .stb(           wb_stb_o        ),
                .sel(           wb_sel_o        ),
                .we(            wb_we_o         ),
                .ack(           wb_ack_i        ),
                .err(           wb_err_i        ),
                .rty(                           )
                );
 
`include "tests.v"
 
endmodule

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Top Level Test Bench ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40	54	rherveille	`// $Id: test_bench_top.v,v 1.8 2003-05-07 14:39:19 rherveille Exp $`
41	16	rudi	`//`
42	54	rherveille	`// $Date: 2003-05-07 14:39:19 $`
43			`// $Revision: 1.8 $`
44	24	rherveille	`// $Author: rherveille $`
45	16	rudi	`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50	54	rherveille	`// Revision 1.7 2003/05/07 09:45:28 rherveille`
51			`// Numerous updates and added checks`
52			`//`
53	52	rherveille	`// Revision 1.6 2003/03/19 17:22:19 rherveille`
54			`// Added WISHBONE revB.3 sanity checks`
55			`//`
56	46	rherveille	`// Revision 1.5 2003/03/19 12:20:53 rherveille`
57			`// Changed timing section in VGA core, changed testbench accordingly.`
58			`// Fixed bug in 'timing check' test.`
59			`//`
60	44	rherveille	`// Revision 1.4 2002/02/07 05:38:32 rherveille`
61			`// Added wb_ack delay section to testbench`
62	16	rudi	`//`
63			`//`
64			`//`
65	44	rherveille	`//`
66	52	rherveille	`//`
67	16	rudi
68	44	rherveille	`timescale 1ns/10ps
69	16	rudi
70			`module test;`
71
72			`reg clk;`
73			`reg rst;`
74
75			`parameter LINE_FIFO_AWIDTH = 7;`
76
77			`wire int;`
78			`wire [31:0] wb_addr_o;`
79			`wire [31:0] wb_data_i;`
80			`wire [31:0] wb_data_o;`
81			`wire [3:0] wb_sel_o;`
82			`wire wb_we_o;`
83			`wire wb_stb_o;`
84			`wire wb_cyc_o;`
85	46	rherveille	`wire [2:0] wb_cti_o;`
86			`wire [1:0] wb_bte_o;`
87	16	rudi	`wire wb_ack_i;`
88			`wire wb_err_i;`
89			`wire [31:0] wb_addr_i;`
90			`wire [31:0] wbm_data_i;`
91			`wire [3:0] wb_sel_i;`
92			`wire wb_we_i;`
93			`wire wb_stb_i;`
94			`wire wb_cyc_i;`
95			`wire wb_ack_o;`
96	52	rherveille	`wire wb_rty_o;`
97	16	rudi	`wire wb_err_o;`
98	52	rherveille	`reg pclk_i;`
99			`wire pclk;`
100	16	rudi	`wire hsync;`
101			`wire vsync;`
102			`wire csync;`
103			`wire blanc;`
104			`wire [7:0] red;`
105			`wire [7:0] green;`
106			`wire [7:0] blue;`
107	52	rherveille	`wire dvi_pclk_p_o;`
108			`wire dvi_pclk_m_o;`
109			`wire dvi_hsync_o;`
110			`wire dvi_vsync_o;`
111			`wire dvi_de_o;`
112			`wire [11:0] dvi_d_o;`
113	16	rudi
114	52	rherveille
115	24	rherveille	`wire vga_stb_i;`
116			`wire clut_stb_i;`
117	16	rudi
118			`reg scen;`
119
120			`// Test Bench Variables`
121			`integer wd_cnt;`
122			`integer error_cnt;`
123
124			`// Misc Variables`
125			`reg [31:0] data;`
126			`reg [31:0] pattern;`
127			`reg int_warn;`
128
129			`integer n;`
130			`integer mode;`
131
132			`reg [7:0] thsync, thgdel;`
133			`reg [15:0] thgate, thlen;`
134			`reg [7:0] tvsync, tvgdel;`
135			`reg [15:0] tvgate, tvlen;`
136			`reg hpol;`
137			`reg vpol;`
138			`reg cpol;`
139			`reg bpol;`
140			`integer p, l;`
141			`reg [31:0] pn;`
142			`reg [31:0] pra, paa, tmp;`
143			`reg [23:0] pd;`
144			`reg [1:0] cd;`
145			`reg pc;`
146			`reg [31:0] vbase;`
147			`reg [31:0] cbase;`
148			`reg [31:0] vbara;`
149			`reg [31:0] vbarb;`
150			`reg [7:0] bank;`
151
152			`/////////////////////////////////////////////////////////////////////`
153			`//`
154	52	rherveille	`// Defines`
155	16	rudi	`//`
156
157			`define CTRL 32'h0000_0000
158			`define STAT 32'h0000_0004
159			`define HTIM 32'h0000_0008
160			`define VTIM 32'h0000_000c
161			`define HVLEN 32'h0000_0010
162			`define VBARA 32'h0000_0014
163			`define VBARB 32'h0000_0018
164
165			`define USE_VC 1
166
167	44	rherveille	`parameter PCLK_C = 20;`
168	24	rherveille
169	16	rudi	`/////////////////////////////////////////////////////////////////////`
170			`//`
171			`// Simulation Initialization and Start up Section`
172			`//`
173
174			`initial`
175			`begin`
176			`$timeformat (-9, 1, " ns", 12);`
177			`$display("\n\n");`
178			`$display("******************************************************");`
179			`$display("* WISHBONE VGA/LCD Controller Simulation started ... *");`
180			`$display("******************************************************");`
181			`$display("\n");`
182			`ifdef WAVES
183			`$shm_open("waves");`
184			`$shm_probe("AS",test,"AS");`
185			`$display("INFO: Signal dump enabled ...\n\n");`
186			`endif
187			`scen = 0;`
188			`error_cnt = 0;`
189			`clk = 0;`
190	52	rherveille	`pclk_i = 0;`
191	16	rudi	`rst = 0;`
192			`int_warn=1;`
193
194			`repeat(20) @(posedge clk);`
195			`rst = 1;`
196			`repeat(20) @(posedge clk);`
197
198			`// HERE IS WHERE THE TEST CASES GO ...`
199
200			`if(0) // Full Regression Run`
201			`begin`
202
203			`end`
204			`else`
205			`if(1) // Quick Regression Run`
206			`begin`
207	52	rherveille	`// reg_test;`
208			`// tim_test;`
209	29	rherveille
210	54	rherveille	`// pd1_test;`
211			`// pd2_test;`
212
213			`ifdef VGA_12BIT_DVI
214			`dvi_pd_test;`
215			`endif
216	29	rherveille
217	52	rherveille	`// ur_test;`
218	16	rudi	`end`
219			`else`
220			`begin`
221
222			`//`
223			`// TEST DEVELOPMENT AREA`
224			`//`
225			`$display("\n\n");`
226			`$display("*****************************************************");`
227			`$display("* XXX Test *");`
228			`$display("*****************************************************\n");`
229
230			`s0.fill_mem(1);`
231
232	52	rherveille	`repeat(10) @(posedge clk);`
233	16	rudi
234			`vbara = 32'h0000_0000;`
235			`vbarb = 32'h0001_0000;`
236
237			m0.wb_wr1( `VBARA, 4'hf, vbara );
238			m0.wb_wr1( `VBARB, 4'hf, vbarb );
239
240			`thsync = 0;`
241			`thgdel = 0;`
242			`thgate = 340;`
243			`thlen = 345;`
244
245			`tvsync = 0;`
246			`tvgdel = 0;`
247			`tvgate = 240;`
248			`tvlen = 245;`
249
250			`/*`
251			`thsync = 0;`
252			`thgdel = 0;`
253			`thgate = 63;`
254			`thlen = 70;`
255
256			`tvsync = 0;`
257			`tvgdel = 0;`
258			`tvgate = 32;`
259			`tvlen = 36;`
260			`*/`
261
262			`hpol = 0;`
263			`vpol = 0;`
264			`cpol = 0;`
265			`bpol = 0;`
266
267			m0.wb_wr1( `HTIM, 4'hf, {thsync, thgdel, thgate} );
268			m0.wb_wr1( `VTIM, 4'hf, {tvsync, tvgdel, tvgate} );
269			m0.wb_wr1( `HVLEN, 4'hf, {thlen, tvlen} );
270
271			`mode = 2;`
272
273			`//for(mode=0;mode<1;mode=mode+1)`
274			`for(bank=0;bank<3;bank=bank + 1)`
275			`begin`
276			`case(mode)`
277			`0:`
278			`begin`
279			`cd = 2'h2;`
280			`pc = 1'b0;`
281			`end`
282			`1:`
283			`begin`
284			`cd = 2'h0;`
285			`pc = 1'b0;`
286			`end`
287			`2:`
288			`begin`
289			`cd = 2'h0;`
290			`pc = 1'b1;`
291			`end`
292			`3:`
293			`begin`
294			`cd = 2'h1;`
295			`pc = 1'b0;`
296			`end`
297			`endcase`
298
299			m0.wb_wr1( `CTRL, 4'hf, {
300			`16'h0, // Reserved`
301			`bpol, cpol,`
302			`vpol, hpol,`
303			`pc, // 1'b0, // PC`
304			`cd, // 2'h2, // CD`
305			`2'h0, // VBL`
306			`1'b0, // Reserved`
307			`1'b1, // CBSWE`
308			`1'b1, // VBSWE`
309			`1'b0, // BSIE`
310			`1'b0, // HIE`
311			`1'b0, // VIE`
312			`1'b1 // Video Enable`
313			`});`
314
315			`$display("Mode: %0d Screen: %0d", mode, bank);`
316			`//repeat(2) @(posedge vsync);`
317			`@(posedge vsync);`
318
319			`// For Each Line`
320			`for(l=0;l<tvgate+1;l=l+1)`
321			`// For each Pixel`
322			`for(p=0;p<thgate+1;p=p+1)`
323			`begin`
324			`while(blanc) @(posedge pclk); // wait for viewable data`
325
326			`//$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);`
327
328			`if(bank[0]) vbase = vbarb[31:2];`
329			`else vbase = vbara[31:2];`
330	24	rherveille	`if(bank[0]) cbase = 32'h0000_0c00;`
331			`else cbase = 32'h0000_0800;`
332	16	rudi
333			`// Depending on Mode, determine pixel data`
334			`// pixel number = line * (thgate + 1) + p`
335			`pn = l * (thgate + 1) + p;`
336
337			`case(mode)`
338			`0: // 24 bit/pixel mode`
339			`begin`
340			`pra = pn[31:2] * 3; // Pixel relative Address`
341			`paa = pra + vbase; // Pixel Absolute Address`
342
343			`// Pixel Data`
344			`case(pn[1:0])`
345			`0:`
346			`begin`
347			`tmp = s0.mem[paa];`
348			`pd = tmp[31:8];`
349			`end`
350			`1:`
351			`begin`
352			`tmp = s0.mem[paa];`
353			`pd[23:16] = tmp[7:0];`
354			`tmp = s0.mem[paa+1];`
355			`pd[15:0] = tmp[31:16];`
356			`end`
357			`2:`
358			`begin`
359			`tmp = s0.mem[paa+1];`
360			`pd[23:8] = tmp[15:0];`
361			`tmp = s0.mem[paa+2];`
362			`pd[7:0] = tmp[31:24];`
363			`end`
364			`3:`
365			`begin`
366			`tmp = s0.mem[paa+2];`
367			`pd = tmp[23:0];`
368			`end`
369			`endcase`
370			`end`
371
372			`1: // 8 bit/pixel grayscale mode`
373			`begin`
374			`pra = pn[31:2]; // Pixel relative Address`
375			`paa = pra + vbase; // Pixel Absolute Address`
376			`case(pn[1:0])`
377			`0:`
378			`begin`
379			`tmp = s0.mem[paa];`
380			`pd = { tmp[31:24], tmp[31:24], tmp[31:24] };`
381			`end`
382			`1:`
383			`begin`
384			`tmp = s0.mem[paa];`
385			`pd = { tmp[23:16], tmp[23:16], tmp[23:16] };`
386			`end`
387			`2:`
388			`begin`
389			`tmp = s0.mem[paa];`
390			`pd = { tmp[15:8], tmp[15:8], tmp[15:8] };`
391			`end`
392			`3:`
393			`begin`
394			`tmp = s0.mem[paa];`
395			`pd = { tmp[7:0], tmp[7:0], tmp[7:0] };`
396			`end`
397			`endcase`
398			`end`
399
400			`2: // 8 bit/pixel Pseudo Color mode`
401			`begin`
402			`pra = pn[31:2]; // Pixel relative Address`
403			`paa = pra + vbase; // Pixel Absolute Address`
404			`case(pn[1:0])`
405			`0:`
406			`begin`
407			`tmp = s0.mem[paa];`
408			`tmp = s0.mem[cbase[31:2] + tmp[31:24]];`
409			`pd = tmp[23:0];`
410			`end`
411			`1:`
412			`begin`
413			`tmp = s0.mem[paa];`
414			`tmp = s0.mem[cbase[31:2] + tmp[23:16]];`
415			`pd = tmp[23:0];`
416			`end`
417			`2:`
418			`begin`
419			`tmp = s0.mem[paa];`
420			`tmp = s0.mem[cbase[31:2] + tmp[15:8]];`
421			`pd = tmp[23:0];`
422			`end`
423			`3:`
424			`begin`
425			`tmp = s0.mem[paa];`
426			`tmp = s0.mem[cbase[31:2] + tmp[7:0]];`
427			`pd = tmp[23:0];`
428			`end`
429			`endcase`
430			`end`
431
432			`3: // 16 bit/pixel mode`
433			`begin`
434			`pra = pn[31:1]; // Pixel relative Address`
435			`paa = pra + vbase; // Pixel Absolute Address`
436			`case(pn[0])`
437			`0:`
438			`begin`
439			`tmp = s0.mem[paa];`
440			`tmp[15:0] = tmp[31:16];`
441			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
442			`end`
443			`1:`
444			`begin`
445			`tmp = s0.mem[paa];`
446			`pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};`
447			`end`
448			`endcase`
449			`end`
450
451			`endcase`
452
453			`if(pd !== {red, green, blue} )`
454			`begin`
455			`$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",`
456			`pd, red, green, blue);`
457			`$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);`
458			`error_cnt = error_cnt + 1;`
459			`end`
460
461			`@(posedge pclk);`
462
463	46	rherveille	`end`
464	16	rudi	`end`
465
466			`show_errors;`
467			`$display("*****************************************************");`
468			`$display("* Test DONE ... *");`
469			`$display("*****************************************************\n\n");`
470
471
472			`end`
473
474			`repeat(10) @(posedge clk);`
475			`$finish;`
476			`end`
477
478			`/////////////////////////////////////////////////////////////////////`
479			`//`
480			`// Sync Monitor`
481			`//`
482
483	52	rherveille	`ifdef VGA_12BIT_DVI
484			`sync_check #(PCLK_C*2) ucheck(`
485			`else
486	46	rherveille	`sync_check #(PCLK_C) ucheck(`
487	52	rherveille	`endif
488	16	rudi	`.pclk( pclk ),`
489			`.rst( rst ),`
490			`.enable( scen ),`
491			`.hsync( hsync ),`
492			`.vsync( vsync ),`
493			`.csync( csync ),`
494			`.blanc( blanc ),`
495			`.hpol( hpol ),`
496			`.vpol( vpol ),`
497			`.cpol( cpol ),`
498			`.bpol( bpol ),`
499			`.thsync( thsync ),`
500			`.thgdel( thgdel ),`

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